JP3315287B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a wiring and an electrode pattern having a laminated structure of a high melting point metal film, a reaction barrier layer and a polycrystalline silicon film, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, demands for higher integration and higher speed of semiconductor devices have been increasing. In order to fulfill these demands, while reductions and miniaturization between elements and element dimensions have been promoted, reduction of the internal wiring material and the like have been studied.

[0003] In particular, in a word line in which an RC delay appears remarkably, reduction in resistance is a major problem. Therefore, recently, in order to reduce the resistance, a polycide gate employing a two-layer structure of a metal silicide film and a polycrystalline silicon film has been widely adopted. The refractory metal silicide has a specific resistance about one digit lower than that of the polycrystalline silicon film and is excellent in oxidation resistance, and is promising as a low-resistance wiring. As the silicide, tungsten silicide (WSix) is most widely used.

[0004] However, from the 0.25 µm generation onward, further reduction in delay time is required. If a gate electrode having a sheet resistance of 1Ω / □ or less is realized by the polycide structure, the thickness of the silicide film becomes large and the aspect ratio of the gate electrode becomes extremely high. As a result, it becomes difficult to process the gate electrode pattern and the interlayer film on the electrode. Therefore, it is necessary to use a material having a lower specific resistance than metal silicide as the gate electrode material.

Recently, a polymetal gate structure comprising a refractory metal film, a reaction barrier layer and a polycrystalline silicon film has been receiving attention. For example, the specific resistance of tungsten is about one digit smaller than WSix, and the RC delay can be greatly reduced. Tungsten easily reacts with polycrystalline silicon by heat treatment at about 800 ° C. By sandwiching a reaction barrier layer between the tungsten film and the polycrystalline silicon film, a low-resistance gate structure having excellent heat resistance is obtained. It can be formed.

[0006]

As described above, a polymetal structure composed of a laminate of a high melting point metal film, a reaction barrier layer and a polycrystalline silicon film is expected as a next-generation low-resistance gate material. However, the refractory metal film generally has a coefficient of thermal expansion that is about an order of magnitude higher than that of an interlayer film such as a silicon oxide film. Therefore, when a refractory metal film is used for an electrode or a wiring, a large stress is applied between the electrode and an interlayer film covering the electrode.
Particularly, in the electrode of a MOS transistor, the stress applied to the side surface of the electrode has a large adverse effect on the thin gate oxide film immediately below the electrode, and significantly deteriorates the reliability of the oxide film. Therefore, it is necessary to suppress the stress acting on the electrode side surfaces as much as possible, and a structure considering the thermal expansion coefficient is desired.

In manufacturing the polymetal structure,
There are many problems to overcome. First, refractory metal films such as tungsten are very easily oxidized, for example,
Tungsten is oxidized at about 500 ° C. Tungsten oxide is an insulator and, furthermore, causes deposition expansion with oxidation, so that an electrode having a polymetal structure cannot be heated in an oxidizing atmosphere.

Generally, in the LSI manufacturing process, a post-oxidation process is required after the gate electrode is formed to improve the reliability of the oxide film. The need for the polymetal structure remains the same, but since the tungsten is oxidized as described above, a post-oxidation step cannot be performed.

Further, after ion implantation, heat treatment is performed to activate impurities. However, residual oxygen cannot be ignored in a commonly used heat treatment furnace. Therefore, the heat treatment cannot be performed while W is exposed.

In order to solve these oxidation problems, there has been proposed a method of selectively oxidizing silicon without oxidizing tungsten (Japanese Patent Publication No. 4-58688). According to this method, it is possible to oxidize only silicon by controlling the partial pressure of hydrogen and water vapor.

However, since this method uses a large amount of hydrogen gas, it has a problem in terms of safety, and its practical use is difficult. Furthermore, there is a problem that it is necessary to maintain special equipment, which is costly.

Further, a new problem arises in forming a pattern of a laminated electrode such as a polymetal structure. Normally, in the case of forming an electrode pattern consisting of a single layer of a polycrystalline silicon film, the polycrystalline silicon film is anisotropically and selectively processed with respect to an etching mask, and the polycrystalline silicon film is formed with a high selectivity with respect to a thin gate oxide film as an underlayer. The silicon film must be etched. In addition, when forming a polymetal electrode pattern composed of a refractory metal film and a polycrystalline silicon film, it is necessary to selectively etch the refractory metal film with respect to the polycrystalline silicon film and the thin oxide film.

However, the etching technique currently used cannot selectively etch the high melting point metal film with respect to the polycrystalline silicon film. The crystalline silicon film is greatly shaved and, in the worst case, is etched down to the silicon substrate.

Further, the metal film has a relatively large particle size, and the value is as large as 0.1 μm or more. Generally, dry etching easily proceeds at a grain boundary portion, and the pattern is not etched linearly in the longitudinal direction, but has a jagged shape. When the pattern size reaches the generation of about 0.2 μm, the jaggedness cannot be ignored and causes a variation in the size of the wiring, which greatly affects the operation characteristics of the transistor. SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a semiconductor device capable of improving reliability and reducing RC delay, and a method of manufacturing the same.

[0015]

A semiconductor device according to the present invention is characterized in that wirings and electrodes including a high melting point metal film are covered with an insulating film having a thermal expansion coefficient close to that of the high melting point metal film. . In the method of manufacturing a semiconductor device according to the present invention, when forming a wiring and an electrode pattern including a high melting point metal film, an insulating film having a thermal expansion coefficient close to that of the high melting point metal film is deposited on a substrate and the insulating film Forming a groove on the insulating film, sequentially depositing a reaction barrier layer and the refractory metal film on the insulating film, filling the groove, and planarizing the reaction barrier layer and the refractory metal film. , Is provided.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the step of forming the groove includes the steps of: depositing a polycrystalline silicon film on a substrate; and forming a silicon oxide film on the polycrystalline silicon film. Performing a step of patterning a laminated film including the polycrystalline silicon film and the silicon oxide film; a step of depositing the insulating film on the substrate including the patterned laminated film; and planarizing the insulating film. And a step of selectively removing the silicon oxide film. In this case, the method may further include a step of flattening the polycrystalline silicon film after depositing the polycrystalline silicon film and before depositing the silicon oxide film.

In another aspect of the method for manufacturing a semiconductor device according to the present invention, the step of forming the groove includes the steps of: depositing a polycrystalline silicon film on a substrate; and patterning the polycrystalline silicon film. Depositing the insulating film on the substrate including the patterned polycrystalline silicon film, flattening the insulating film so that the patterned polycrystalline silicon film is exposed, and The method includes the steps of: exposing a polycrystalline silicon film to an oxidizing atmosphere to form a silicon oxide film on the polycrystalline silicon film; and selectively removing the silicon oxide film.

[0018]

According to the present invention, the periphery of the high melting point metal is surrounded by a material having a close thermal expansion coefficient, so that internal stress due to thermal expansion hardly occurs. Therefore, by employing this structure, the stress applied to the electrode side surface can be significantly reduced, and the reliability of the gate oxide film can be improved.

According to the present invention, a reaction barrier layer and a refractory metal film are formed inside a groove of an insulating film having a polycrystalline silicon film at the bottom when a semiconductor device having the electrodes and wirings having the above-described structures is manufactured. By embedding, it becomes possible to form a structure composed of a refractory metal film, a reaction barrier layer, and a polycrystalline silicon film.

The polycrystalline silicon film is etched by etching the silicon oxide film and the polycrystalline silicon film with the same resist pattern, covering the entire surface with a silicon nitride film and flattening, and selectively removing only the oxide film. Grooves can be selectively formed on the film, so that the reaction barrier layer and the refractory metal film can be embedded in a self-aligned manner.

That is, according to the present invention, the problem of misalignment between the polycrystalline silicon film and the overlying reaction barrier layer and refractory metal film does not occur. Furthermore, a post-oxidation step can be performed before the deposition of the refractory metal film, so that the reliability of the oxide film can be improved and the special oxidation technique such as the selective oxidation described above is not required.

Also, when performing the heat treatment after the ion implantation, the heat treatment can be performed before the deposition of the refractory metal film, and there is no need to worry about the influence of the residual oxygen. Further, since the refractory metal film is formed by filling the groove, it is not necessary to selectively etch the refractory metal film with respect to the underlying polycrystalline silicon film. Same as formation. Further, according to the present method, since the wiring does not have a jagged shape peculiar to the etching of the metal film, the dimensional variation can be reduced.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1 to 4 are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. More specifically, the present embodiment relates to formation of a gate electrode pattern of a MOS field effect transistor.

First, as shown in FIG. 1A, a thin oxide film 101 (7 nm thick) is formed as a gate insulating film on a substrate 100 made of single crystal silicon, and then a chemical vapor phase is formed thereon. Polycrystalline silicon film 1 using growth (CVD) method
02 (film thickness 100 nm) was deposited. Next, a silicon oxide film 103 (with a film thickness of 10) is formed on the polycrystalline silicon film by a CVD method.
0 nm). Note that the silicon oxide film 103 is made of P
Or a doped glass containing TE or B or a TEOS film. Then, a photoresist (1 μm thick) is formed on the silicon oxide film.
Was applied by a spin coat method, and the photoresist was exposed through a photomask and developed to form a resist pattern 104 having a width of, for example, 0.25 μm.

Next, as shown in FIG. 1B, the silicon oxide film 103 was etched along the resist pattern 104 using a dry etching apparatus. The etching conditions at this time are as follows: power density 2.9 W / cm 2, pressure 50
mTorr, flow rate CHF3 / CF4 = 74/78 SCC
M and the electrode temperature was kept at 35 ° C.

Further, as shown in FIG. 1C, the polycrystalline silicon film 102 was etched using the resist 104 and the silicon oxide film 103 as a mask pattern. The etching conditions are a power density of 0.8 W / cm @ 2, a pressure of 75 mTorr.
r, the flow rate HBr = 100 SCCM, and the electrode temperature is 65
C. was maintained. Note that the remaining resist pattern 104
Was removed by O2 ashing after etching the polycrystalline silicon film 102.

Thereafter, as shown in FIG. 2D, post-oxidation is performed to recover the thin silicon oxide film 101 shaved during the etching of the polycrystalline silicon film 102 and to round the corner portion 105 of the polycrystalline silicon film 102. An oxidation called process was performed. As a result, the gate oxide film 101 recovers to its original thickness, and the corner portion 10 of the polycrystalline silicon film 102
5 is rounded. As a result, electric field concentration at the corner portion 105 of the gate electrode is avoided, and the reliability of the gate oxide film 101 is further improved.

As shown in FIG. 2 (e), for example, As.sup. +
The substrate was doped under the conditions of eV and an implantation amount of 3 × 10 14 cm −2, and further, a heat treatment was performed at 900 ° C. for about 30 seconds in, for example, a nitrogen atmosphere to form an N-type diffusion layer 106.

Next, as shown in FIG. 2F, a silicon nitride film 107 (150 nm thick) is formed thereon by the CVD method.
Was deposited. The silicon nitride film is a material having a thermal expansion coefficient close to that of the high melting point metal film. The silicon nitride film 107 was etched back by a dry etching method, and was left only on the side walls of the silicon oxide film 103 and the polycrystalline silicon film 102. The etching conditions were a power density of 0.8 W / cm 2, a pressure of 20 mTorr,
The flow rate was CHF3 / CF4 = 74/78 SCCM, and the electrode temperature was maintained at 60.degree. The thickness of the side wall portion 107 was about 50 nm.

Further, as shown in FIG. 3 (g), the substrate is doped with As.sup. + Ions from above by ion implantation under the conditions of an acceleration voltage of 45 keV and a dose of 3.times.10@15 cm @ -2. 800 in nitrogen atmosphere
A heat treatment at about 30 ° C. was performed to form an N + diffusion layer 108.

Thereafter, as shown in FIG. 3 (h), the refractory metal film is surrounded by an insulating film having a thermal expansion coefficient close to that of the refractory metal film.
On this, a silicon nitride film 109 (thickness: 400 nm) was deposited again by the CVD method. Next, in order to flatten the silicon nitride film 109, a resist was applied thereon by spin coating, and the silicon nitride film 109 was etched back to a height at which the upper surface of the silicon oxide film appeared. Note that, as a method of flattening the silicon nitride film 109, a chemical mechanical polishing (CMP) method can be used instead of the etch back.

Next, as shown in FIG. 3I, the silicon oxide film 103 on the polycrystalline silicon film 102 was selectively removed from the silicon nitride film 109 by dry etching. The etching conditions were a power density of 2.9 W / cm 2, a pressure of 40 mTorr, and a flow rate of C 4 F 8 / CO / Ar = 10 /.
The electrode temperature was kept at 30 ° C. at 100/200 SCCM. At this time, the silicon oxide film 103 has a thickness of about 400 nm /
In contrast, the silicon nitride film 109 was etched at about 20 nm / min, whereas the selectivity of the silicon oxide film 103 to the silicon nitride film 109 was about 20. Note that as a method for selectively removing the silicon oxide film 103 from the silicon nitride film 109, for example, the substrate to be processed can be immersed in a hydrofluoric acid (HF) aqueous solution diluted to 5%.

As a result, as shown in FIG. 3I, a groove 110 made of a silicon nitride film 109 having a polycrystalline silicon film 102 at the bottom was formed on the substrate 100. Next, as shown in FIG. 4 (j), a tungsten nitride film 111 (thickness: 10 nm) was deposited on the entire surface by a reactive sputtering method using an N2 / Ar mixed gas. Note that the tungsten nitride film 111 was used as a reaction barrier layer between the tungsten film 112 and the polycrystalline silicon film 102.
Next, a tungsten film 112 is formed in the groove 110 by CVD.
Was deposited so as to be embedded.

As shown in FIG. 4K, the tungsten film 112 and the tungsten nitride film 111 were etched back by a dry etching method until the silicon nitride film 109 was exposed. The etching condition is a power density of 1.5 W / c.
m2, pressure 40 mTorr, flow rate SF6 / O2 = 25 /
75 SCCM, and the electrode temperature was kept at 80 ° C. The tungsten film 112 and the tungsten nitride film 11
As a method for performing the flattening of No. 1, in addition to the etch back,
It is also possible by the MP method.

As a result, the tungsten film 1 is formed only inside the trench.
12 and the tungsten nitride film 111 remained, and a gate electrode pattern composed of a refractory metal film surrounded by a silicon nitride film, a reaction barrier layer, and a polycrystalline silicon film was formed.

As described above, in this embodiment, the side surfaces of the refractory metal film and the polycrystalline silicon film are covered with the silicon nitride film. The stress acting between the electrode and the insulating film covering it not only has a bad effect on the electrode itself, but also when used for the gate electrode of a MOS transistor as in this embodiment, a thin oxide film just under the electrode There is a possibility that the reliability may be deteriorated. When the coefficient of thermal expansion of each material is shown, a refractory metal film, for example, tungsten is about 1 × 10 10 dyn / cm.
2. The polycrystalline silicon film has a thickness of about 8.times.10@9 dyn / cm.
2 The value of a reaction barrier layer, for example, a tungsten nitride film is almost the same as that of a tungsten film. On the other hand, a silicon oxide film usually used as an insulating film is about 5.times.10@8 dyn / cm @ 2, which is smaller by about an order of magnitude than a refractory metal film, and has a large stress between the silicon oxide film and the refractory metal film. Is added. However, the thermal expansion coefficient of the silicon nitride film is close to that of tungsten, and its value is about 8 × 10 9 dy.
Since it is n / cm2, the stress applied to the electrodes and the wiring can be greatly reduced by surrounding the side wall of the refractory metal film with the silicon nitride film.

In this embodiment, tungsten (W) is used as the refractory metal film.
o), niobium (Nb), and tantalum (Ta). Although a tungsten nitride film was used as a reaction barrier layer,
A refractory metal film nitride, nitrided oxide, carbide, or boride may be used. Furthermore, a silicon nitride film and a silicon carbide film can also be used as a reaction barrier layer.

In this embodiment, the silicon nitride film is used as the insulating film having a thermal expansion coefficient close to that of the high melting point metal film.
A silicon nitride oxide film (oxynitride) may be used. (Embodiment 2) FIGS. 5 to 8 are sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps. More specifically, the present embodiment relates to formation of a gate electrode pattern of a MOS field effect transistor.

First, as shown in FIG. 5A, a thin silicon oxide film 202 (thickness: 7 nm) is formed as a gate insulating film on a substrate 200 having an element isolation 201, and then a chemical vapor is formed thereon. A polycrystalline silicon film 203 (thickness: 200 nm) was deposited using a phase growth (CVD) method. Thereafter, a photoresist (1 μm thick) is formed on the polycrystalline silicon film 203.
Was applied by spin coating, and the photoresist was exposed through a photomask and developed to form a resist pattern 204.

Next, as shown in FIG. 5B, the polycrystalline silicon film 203 was etched along the resist pattern 204 using a dry etching apparatus. Note that the remaining resist pattern 204 was peeled off by O2 ashing after etching the polycrystalline silicon film 203.

Thereafter, as shown in FIG. 5 (c), post-oxidation is performed to recover the thin silicon oxide film 202 shaved during the etching of the polycrystalline silicon film 203 and to round the corners of the polycrystalline silicon film. Was. From above, the substrate 200 was doped with, for example, As @ + ions by an ion implantation method under the conditions of an acceleration voltage of 30 keV and a dose of 3.times.10@14 cm @ -2 to form an N-type diffusion layer 205.

Next, as shown in FIG. 6D, a silicon nitride film 206 (150 nm thick) was deposited by the CVD method. The silicon nitride film 206 was etched back by a dry etching method, and was left only on the side walls of the polycrystalline silicon film 203.

Further, as shown in FIG. 6 (e), the substrate is doped with As + ions from above by ion implantation under the conditions of an acceleration voltage of 45 keV and a dose of 3.times.10@15 cm @ -2. The diffusion layer 207 was formed.

Thereafter, as shown in FIG. 6 (f), the refractory metal film is surrounded by an insulating film having a thermal expansion coefficient close to that of the refractory metal film.
On this, a silicon nitride film 208 (thickness: 400 nm) was deposited again by the CVD method. Next, the silicon nitride film 208
In order to planarize the polycrystalline silicon film 203, a resist is applied thereon by spin coating, and a thin oxide film 2 is formed.
The surface was planarized to the height of the polycrystalline silicon film 203 on the substrate 02.

Next, as shown in FIG. 7G, the polycrystalline silicon film 203 was oxidized in an oxygen atmosphere by a thickness corresponding to about 100 nm to form a silicon oxide film 209 on the polycrystalline silicon film 203. . At this time, the polycrystalline silicon film 203 on the element isolation region 201 hardly remains, but the polycrystalline silicon film 203 having a thickness of 100 nm remains on the thin oxide film 202.

Thereafter, as shown in FIG. 7H, only the silicon oxide film 209 was selectively removed from the silicon nitride film 208 by dry etching. As a result, the polycrystalline silicon film 2 is formed on the substrate 200 having the element isolation region 201.
A groove made of a silicon nitride film 208 having 03 at the bottom was formed.

As shown in FIG. 7 (i), N2
A tungsten nitride film 210 (thickness: 10 nm) was deposited on the entire surface by a reactive sputtering method using a mixed gas of / Ar, and a tungsten film 211 was deposited by a CVD method so as to fill the trench.

Thereafter, as shown in FIG. 8J, the tungsten film 211 and the tungsten nitride film 210 were etched back by dry etching until the silicon nitride film 208 was exposed. As a result, the tungsten film 211 and the tungsten nitride film 210 remained only inside the trench, and a gate electrode pattern composed of the refractory metal film, the reaction barrier layer, and the polycrystalline silicon film was formed.

Although the polycrystalline silicon film 203 hardly remains on the element isolation region 201, the gate electrode itself is electrically connected by the tungsten film 211, and there is no problem in the operation characteristics of the transistor. (Embodiment 3) FIGS. 9 to 12 are sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.
More specifically, the present embodiment relates to formation of a gate electrode pattern of a MOS field effect transistor.

First, as shown in FIG. 9A, a thin oxide film 302 (thickness: 7 nm) is formed as a gate insulating film on a substrate 300 having an element isolation region 301, and then a chemical gas is formed thereon. A polycrystalline silicon film 303 (thickness: 100 nm) was deposited using a phase growth (CVD) method.

Thereafter, as shown in FIG. 9B, the polycrystalline silicon film 303 was flattened to the height of the element isolation 301 by the CMP method. In addition, as a method of flattening the polycrystalline silicon film 303, an etch back can be used instead of the CMP method.

Next, as shown in FIG. 9C, a silicon oxide film 304 is formed on the polycrystalline silicon film 303 by CVD.
(Thickness: 100 nm). Thereafter, a resist pattern 305 was formed on the silicon oxide film 304.

Next, as shown in FIG. 10D, the silicon oxide film 304 and the polycrystalline silicon film 303 were etched along the resist pattern 305 using a dry etching apparatus. Note that the remaining resist pattern 305
Was removed by O2 ashing after etching the polycrystalline silicon film 303.

Thereafter, as shown in FIG. 10E, post-oxidation was performed in order to recover the thin oxide film 302 shaved during the etching of the polycrystalline silicon film 303 and to round the corners of the polycrystalline silicon film. . Further, from above, for example, As @ + ions were accelerated by ion implantation at an acceleration voltage of 30 keV,
The substrate 300 was doped under the conditions of an implantation amount of 3 × 10 14 cm −2 to form an N-type diffusion layer 306.

Next, as shown in FIG.
A silicon nitride film 307 (film thickness 150 nm) was deposited by the method. The silicon nitride film 307 was etched back by a dry etching method, and was left only on the side walls of the silicon oxide film 304 and the polycrystalline silicon film 303.

Further, as shown in FIG. 11 (g), the substrate 300 is doped from above with, for example, As + ions by ion implantation under the conditions of an acceleration voltage of 45 keV and a dose of 3.times.10@15 cm @ -2. + A diffusion layer 308 was formed.

Thereafter, as shown in FIG. 11H, the silicon nitride film 309 is again formed thereon by a CVD method so as to be surrounded by an insulating film having a thermal expansion coefficient close to that of the refractory metal film.
(Thickness: 400 nm). Next, the silicon nitride film 3
In order to flatten 09, a resist was applied thereon by spin coating, and the silicon nitride film 309 was etched back to a height at which the upper surface of the silicon oxide film 304 appeared.

Next, as shown in FIG. 11I, the silicon oxide film 304 on the polycrystalline silicon film 303 was selectively removed from the silicon nitride film 309 by dry etching. As a result, a groove made of the silicon nitride film 309 having the polycrystalline silicon film 303 at the bottom was formed.

Further, as shown in FIG. 12J, a tungsten nitride film 310 (thickness: 10 nm) was deposited thereon by a reactive sputtering method, and then a tungsten film 311 was deposited by a CVD method so as to fill the grooves.

Thereafter, as shown in FIG. 12K, the tungsten film 311 and the tungsten nitride film 310 were etched back by dry etching until the silicon nitride film 309 was exposed. As a result, the tungsten film 311 and the tungsten nitride film 310 remained only inside the trench, and a gate electrode pattern composed of the refractory metal film, the reaction barrier layer, and the polycrystalline silicon film was formed.

Although the polycrystalline silicon film 303 hardly remains on the element isolation region 301, the gate electrode itself is electrically connected by the tungsten film 311 and there is no problem in the operating characteristics of the transistor. In the first to third embodiments, the example relating to the gate electrode has been described. However, the present invention can be applied to other electrodes and wirings.

[0062]

According to the present invention, a wiring and an electrode composed of a refractory metal, a reaction barrier layer and a polycrystalline silicon film are surrounded by an insulating film having a thermal expansion coefficient close to that of the refractory metal film. Stress on the high melting point metal film and the insulating film can be greatly reduced.

Further, according to the present invention, the reaction barrier layer and the refractory metal film are embedded in the trench of the nitride film having the polycrystalline silicon film at the bottom, so that the refractory metal, the reaction barrier layer and the polycrystalline silicon film are formed. Can be formed.

Further, a groove can be selectively formed on the polycrystalline silicon film, whereby the reaction barrier layer and the refractory metal film can be embedded in a self-aligned manner.
Further, it is possible to perform a post-oxidation step of the electrode and the wiring before depositing the refractory metal film, so that the reliability of the oxide film can be improved and deterioration of the refractory metal due to oxidation does not pose a problem.

Further, since the refractory metal film is formed by filling the groove, it is not necessary to selectively etch the refractory metal film with respect to the underlying polycrystalline silicon film. Same as layer pattern formation.

With such an effect, it is possible to form an electrode and a wiring pattern having a laminated structure of a refractory metal film, a reaction barrier layer, and a polycrystalline silicon film, thereby improving the performance of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps following FIG. 1;

FIG. 3 is a sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps following FIG. 2;

FIG. 4 is a sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps following FIG. 3;

FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps following FIG. 5;

FIG. 7 is a sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps following FIG. 6;

FIG. 8 is a sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps following FIG. 7;

FIG. 9 is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps following FIG. 9;

FIG. 11 is a sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps following FIG. 10;

FIG. 12 is a sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps following FIG. 11;

[Explanation of symbols]

100: substrate, 101: thin silicon oxide film, 102: polycrystalline silicon film, 103: silicon oxide film, 104: resist, 105: corner portion, 106: N-type diffusion layer, 10
7 ... side wall portion, 108 ... N + type diffusion layer, 109 ... silicon nitride film, 110 ... groove, 111 ... tungsten nitride film, 1
12: tungsten film, 200: substrate, 201: element isolation, 202: thin silicon oxide film, 203: polycrystalline silicon film, 204: resist, 205: N-type diffusion layer, 206 ...
Silicon nitride film, 207: N + type diffusion layer, 208: silicon nitride film, 209: silicon oxide film, 210: tungsten nitride film, 211: tungsten film, 300: substrate, 30
DESCRIPTION OF SYMBOLS 1 ... Element isolation, 302 ... Thin silicon oxide film, 303 ... Polycrystalline silicon film, 304 ... Silicon oxide film, 305 ... Resist, 306 ... N-type diffusion layer, 307 ... Silicon nitride film, 30
8 N + type diffusion layer, 309 silicon nitride film, 310 tungsten nitride film, 311 tungsten film.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-167717 (JP, A) JP-A-3-27551 (JP, A) JP-A-6-342766 (JP, A) JP-A-6-342766 77246 (JP, A) JP-A-58-154270 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768 H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/43 H01L 29/47 H01L 29/872 H01L 21/336 H01L 29/76 H01L 29/772 H01L 29/78

Claims (6)

(57) [Claims] 1. A polycrystalline silicon film formed on a substrate via a gate insulating film, and a refractory metal selected from the group consisting of tungsten, molybdenum, niobium, and tantalum formed on the polycrystalline silicon film. A wiring and an electrode having a film, a silicon nitride film covering side surfaces of the wiring and the electrode , and a film formed at an interface between the refractory metal film and the silicon nitride film.
And a tungsten nitride . 2. The polycrystalline silicon film and the silicon nitride film
Characterized by further comprising an oxide film formed at the interface of
2. The semiconductor device according to claim 1, wherein: 3. A pre-Symbol semiconductor device according to claim 1 or 2, further comprising a surfactant to form tungsten nitride with the refractory metal film and the polycrystalline silicon film. 4. A wiring and an electrode pattern containing a refractory metal.
Upon formation, a step of depositing a polycrystalline silicon film on a substrate , a step of flattening the polycrystalline silicon film, a step of forming a silicon oxide film on the polycrystalline silicon film, A step of patterning the laminated film made of the silicon oxide film; a step of depositing an insulating film on the substrate including the patterned laminated film; a step of flattening the insulating film; and selecting the silicon oxide film. Of removing the groove and forming the groove
And a reaction barrier layer and the refractory metal film on the insulating film in order.
Depositing and filling the trench, and planarizing the reaction barrier layer and the refractory metal film
And a method of manufacturing a semiconductor device. 5. A wiring and electrode pattern containing a high melting point metal.
A step of depositing a polycrystalline silicon film on the substrate when forming; a step of patterning the polycrystalline silicon film; a step of depositing an insulating film on the substrate including the patterned polycrystalline silicon film; Flattening the insulating film so that the patterned polycrystalline silicon film is exposed; and exposing the patterned polycrystalline silicon film to an oxidizing atmosphere to form a silicon oxide film on the polycrystalline silicon film. Forming a groove by selectively removing the silicon oxide film.
And a reaction barrier layer and the refractory metal film on the insulating film in order.
Depositing and filling the trench, and planarizing the reaction barrier layer and the refractory metal film
When manufacturing method of a semi-conductor device characterized by comprising a. 6. The method according to claim 4, wherein the wiring and the electrode pattern are gate electrode patterns.