JP4196898B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a wiring formation method, an electrode formation method, and a contact hole formation method in a semiconductor device.

Conventionally, there is a technique shown in FIG. 3 as a technique in this field. Hereinafter, a dynamic random access memory (hereinafter abbreviated as DRAM) will be taken as an example and described in detail with reference to the drawings.
[I] (first prior art)
(1) First, as shown in FIG. 3A, an element isolation region (not shown), a transfer gate 202, and a plug 203 are formed through a normal semiconductor device manufacturing process. The plug 203 is formed on the silicon substrate 201 at a location where it makes contact with the bit line and the capacitor electrode. Note that 201A is an insulating film.

  (2) Next, as shown in FIG. 3B, after depositing an insulating film 204, it is planarized by a chemical mechanical polishing method (hereinafter abbreviated as CMP), and a hole pattern 205 is formed by a normal lithography process. Then, the bit line contact hole 206 is opened in the plug 203 by etching the insulating film 204.

  (3) Next, as shown in FIG. 3C, by depositing a conductive material constituting the bit line, the bit line contact hole 206 is filled, and then through a normal lithography process and an etching process, Bit line 207 is formed.

  (4) Next, as shown in FIG. 3D, an insulating film 208 is deposited on the bit line 207 and then flattened by CMP. After a hole pattern 209 is formed by a normal lithography process, insulation is performed. By etching the films 208 and 204 and the bit line 207, a capacitor electrode contact hole 210 is opened with respect to the plug 203.

Thereafter, the capacitor electrode and subsequent parts are formed through a normal semiconductor device manufacturing process, and the semiconductor device is manufactured.
[II] (Second Prior Art)
With the miniaturization of semiconductor devices, both the transfer gate width and the contact hole dimensions are steadily decreasing. However, since the alignment margin in the lithography process is not scaled, an etching technique that absorbs the alignment margin and secures insulation between the contact hole and the transfer gate is indispensable in the manufacture of semiconductor devices in the future.

  Conventionally, there are technologies shown in FIGS. 4 and 5 as techniques in this field. Hereinafter, it demonstrates in detail according to a figure.

  (1) First, as shown in FIG. 4A, after forming an element isolation region 302 on a silicon substrate 301, a transfer gate 304 loaded with an offset silicon oxide film 303 is formed by ordinary lithography and etching. Thereafter, a mask pattern is formed by ordinary lithography, and n-type impurities are implanted into the silicon substrate 301 by ion implantation. For simplicity, the resist pattern at the time of ion implantation is not shown.

  (2) Next, as shown in FIG. 4B, a silicon oxide film is deposited on the entire surface of the wafer by a chemical vapor deposition method (hereinafter abbreviated as a CVD method) and anisotropically etched to form a side surface. A wall 305 is formed.

  (3) Next, as shown in FIG. 4C, a mask pattern is formed by a normal lithography process, and n-type impurities and p-type impurities are implanted into the silicon substrate 301 by ion implantation. For simplicity, the resist pattern at the time of ion implantation is not shown.

  (4) Next, as shown in FIG. 4D, a silicon oxide film (not shown) is deposited, a silicon nitride film 307 having a film thickness that functions as a stopper is deposited, and then a silicon oxide film 308 is deposited. And flattening by CMP.

  (5) Next, as shown in FIG. 5A, a hole pattern 309 for opening the contact hole 310 is formed in the silicon substrate 301 by ordinary lithography, and a silicon oxide film is formed using the silicon nitride film 307 as a stopper. After etching 308, the silicon nitride film 307 and the silicon oxide film (not shown) are etched to open a contact hole 310 in the silicon substrate 301.

  (6) Next, as shown in FIG. 5B, the contact hole 310 is filled with a polycrystalline silicon film and etched back to form a plug 311.

  (7) Next, as shown in FIG. 5C, after depositing the silicon oxide film 312, a contact hole pattern 313 for connecting the silicon substrate 301 and the bit line is formed by ordinary lithography. After etching the silicon oxide films 312 and 308 using the silicon nitride film 307 as a stopper, the silicon nitride film 307 and the silicon oxide film are etched to form the bit line contact hole 314 in the silicon substrate 301.

Thereafter, the semiconductor device is manufactured through a normal semiconductor device manufacturing process.
[III] (Third prior art)
Conventionally, there are technologies disclosed in FIGS. 6 and 7 as techniques in this field. Hereinafter, it demonstrates in detail according to a figure.

  (1) First, as shown in FIG. 6A, after forming up to the bit line 403 by a normal DRAM manufacturing process, a silicon oxide film 404 is deposited as an interlayer insulating film, and then flattened by CMP, for example. A silicon nitride film 405 is deposited. Although the transfer gate is originally formed to face the bit line, it is not shown for simplicity.

  (2) Next, as shown in FIG. 6B, after depositing a polycrystalline silicon film 406, a hole pattern 407 is formed by a normal lithography process. Thereafter, the polycrystalline silicon film 406 is anisotropically etched using the silicon nitride film 405 as a stopper to form a hole 408.

  (3) Next, as shown in FIG. 6C, after the resist 407 is incinerated, a polycrystalline silicon film is deposited and anisotropically etched to form a sidewall 409, which is more than the hole 408. An etching mask 410 made of a polycrystalline silicon film having a small opening diameter is formed.

  (4) Next, as shown in FIG. 6D, under the condition that a sufficient selection ratio is obtained with respect to the etching mask 410, the layers below the silicon nitride film 405, the silicon oxide film 404, and the bit line 403 are provided. A contact hole 411 is opened on the silicon substrate 401 by etching the insulating film 402 at once. Hereinafter, this contact hole is referred to as a cell contact hole.

  (5) Next, as shown in FIG. 7A, after depositing a polycrystalline silicon film and filling the cell contact hole 411, the polycrystalline silicon film is etched back to form a plug 412.

  (6) Next, as shown in FIG. 7B, after the silicon oxide film 413 is deposited, a hole pattern 414 for opening the contact hole 415 with respect to the plug 412 in the cell contact hole 411 is usually formed. The lithography process is used. Hereinafter, this contact hole is referred to as a capacitor electrode contact hole. Thereafter, the capacitor electrode contact hole 415 is opened by etching the silicon oxide film 413 until it reaches the plug 412 in the cell contact hole 411 under a sufficiently high selection ratio with respect to the silicon nitride film 405.

  (7) Next, as shown in FIG. 7C, after the resist 414 is ashed, a polycrystalline silicon film 416 constituting the capacitor electrode and a silicon oxide film 417 for embedding the capacitor electrode contact hole 415 are sequentially formed. accumulate. Thereafter, the silicon oxide film 417 is etched back until the polycrystalline silicon film 416 is exposed, and then the exposed portion of the polycrystalline silicon film 416 is etched.

(8) Next, as shown in FIG. 7D, by using the silicon nitride film 405 as a stopper, the silicon oxide films 417 and 413 are removed with an aqueous hydrogen fluoride solution, thereby forming a capacitor electrode 418. Thereafter, a capacitor insulating film 419 and a polycrystalline silicon film for forming a cell plate electrode are deposited, and a cell plate electrode 420 is formed by normal lithography and etching.
None

  However, in the conventional method for manufacturing a semiconductor device of [I] described above, as the semiconductor device is further miniaturized, the wiring interval is also reduced, so that it is difficult to secure an alignment margin in the lithography process. However, it is difficult to open contact holes stably. On the other hand, in order to secure an alignment margin in the lithography process, the wiring width must be reduced rather than the miniaturization ratio of the semiconductor device, but it is not easy to form a fine wiring pattern in the lithography process. was there.

  As described above, the above-mentioned [1] conventional semiconductor device manufacturing method has a fatal problem that it is difficult to increase the yield of semiconductor device manufacturing.

  In the above-described conventional method for manufacturing a semiconductor device of [II], the semiconductor device is manufactured through two steps of opening the contact hole in a self-aligning manner using the silicon nitride film as a stopper. In order to increase the manufacturing yield, it is indispensable to stably open a contact hole having a fine opening diameter with respect to a silicon nitride film having a fine slit width in response to the progress of miniaturization of semiconductor devices. . In general, the selectivity to a silicon nitride film and the workability of a fine contact hole are difficult to achieve at the same time, so that there is a problem that it is not always easy to realize a high manufacturing yield by the above method.

  Further, in the above-described conventional method for manufacturing a semiconductor device [III], it is indispensable to ensure an alignment margin in the lithography process when opening the capacitor electrode contact hole with respect to the cell contact hole.

  If the alignment margin cannot be secured, the capacitor electrode contact hole is opened with a deviation from the cell contact hole. Therefore, in the step of etching the silicon oxide film with a hydrogen fluoride aqueous solution using the silicon nitride film as a stopper, the side wall of the cell contact hole is formed. This is because the silicon oxide film is etched and the manufacturing yield decreases due to a short circuit between the capacitor electrode and the bit line or collapse of the capacitor electrode. In order to avoid this, it is necessary to make the recess amount of the plug smaller than the silicon nitride film thickness, but it is never possible to stably reduce the recess of the plug in the etch back below the film thickness of the silicon nitride film. It's not easy.

  In general, the processing size of each process is reduced corresponding to the miniaturization of the semiconductor device, but the alignment margin of the lithography process is not reduced corresponding to the miniaturization of the semiconductor device. The problem becomes more and more obvious.

  The first object of the present invention is to eliminate the above-mentioned problems, to stably form contact holes between wirings even when the semiconductor device is miniaturized, and to easily form wirings and electrodes. It is to provide a method of manufacturing a semiconductor device that can be performed.

  A second object of the present invention is to provide a method of manufacturing a semiconductor device that eliminates the above-mentioned problems, can open contact holes in a simple and self-aligned manner, and has a high manufacturing yield. It is.

In order to achieve the above object, the present invention provides
[1] In a semiconductor device manufacturing method including a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate, and a capacitor electrode forming step, (a) a first polycrystalline silicon film (609), a first A step of processing a laminated film of one silicon oxide film (608) and a first silicon nitride film (607) by a lithography process and an etching process; and (b) using the first polycrystalline silicon film (609) as a mask. The second silicon nitride film (604, 605) is formed on the bit line (603) having a structure in which the upper and side walls are covered with the second silicon nitride film (604, 605). ) etched as a stopper plug (60 previously formed in the interlayer insulating film (602) is connected to the silicon substrate (600) ) Forming a contact hole (611) with respect to, (c) after depositing a second polycrystalline silicon film having a thickness which does not block the contact hole (611) (612), the second by depositing a silicon oxide film (613), a step of filling the contact hole (611), (d) is the second polycrystalline silicon film of the step (c) (612) as a stopper, the contact hole (611) embedded the second silicon oxide film (613) after the etching back, the second silicon oxide film (613) as a mask, the second polysilicon film of the step (c) (612) and a step of isotropically etching back said step the first polycrystalline silicon film (a) (609), (e) the first silicon nitride film (607) As a stopper, by etching using a first hydrogen fluoride aqueous solution the silicon oxide film (608) of the second silicon oxide film (613) and the process of the step (d) (a), the capacitor electrodes ( applying and forming a 614), which was to form in (f) the contact hole for connecting the silicon substrate and the capacitor electrode (614) (600), and the capacitor electrode (614) lithographic 1 step It is.

[2] [1] A method of manufacturing a semiconductor device, wherein the second of said second polycrystalline silicon film of the step (c) a silicon film (613) oxide as a mask (612) and the step ( The first polycrystalline silicon film (609) of a) is anisotropically etched back instead of isotropically.

[3] In the method of manufacturing a semiconductor device according to [1] , after depositing the second polycrystalline silicon film (612) in the step (c) having a thickness that does not block the contact hole (611), By depositing an organic film, the contact hole (611) is buried, the organic film , the second polycrystalline silicon film (612) in the step (c), and the first polycrystalline film in the step (a) . The silicon film (609) is etched back at once.

[4] [1] above method of manufacturing a semiconductor device according plug (601) wherein the top layer first third silicon oxide film which is laminated on the interlayer insulating film was formed (602) (606) The silicon nitride film (607) .

[5] In the method of manufacturing a semiconductor device according to the above [1], after etching the first polycrystalline silicon film (609) and then ashing the resist (610), the first polycrystalline silicon film wherein the (609) as a mask the first silicon oxide film (608), said first silicon nitride film (607) after etching, said bit line (603) said second silicon nitride film of the upper and side walls ( a portion of the third the interlayer insulating film a silicon film and (606) oxidation of the 605,604) laminated on the interlayer insulating film as a stopper (602) (602) is obtained so as to etching.

[6] In the method for manufacturing a semiconductor device according to [1], the first polycrystalline silicon film (609) and the first silicon oxide film (608) are etched, and then the resist (610) is ashed. after the first polysilicon film wherein a (609) as a mask the first silicon nitride film (607) after etching, said bit line (603) said second silicon nitride film of the upper and side walls ( a portion of the third the interlayer insulating film a silicon film and (606) oxidation of the 605,604) laminated on the interlayer insulating film as a stopper (602) (602) is obtained so as to etching.

  According to the present invention, the following effects can be achieved.

  (A) Since a bit line can be formed without passing through a special lithography process after opening a contact hole in a previously formed plug, it is possible to form a bit line suitable for miniaturization of a semiconductor device. In addition, it is possible to reduce the number of manufacturing steps and the manufacturing cost.

  (B) Since a contact hole can be formed in a self-aligned manner with respect to the substrate and a plug for connecting the bit line and the capacitor electrode can be formed without performing a special lithography process. It is possible to reduce the number and manufacturing cost.

  (C) Since a capacitor electrode can be formed without a special lithography process after a contact hole is opened in a plug formed in advance, the number of manufacturing steps and manufacturing cost can be reduced. Is possible.

The present invention relates to a semiconductor device manufacturing method including a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate, and a capacitor electrode forming step. (A) a first polycrystalline silicon film, a first A step of processing a laminated film of the silicon oxide film and the first silicon nitride film by a lithography process and an etching process; and (b) an upper portion and a sidewall formed in advance using the first polycrystalline silicon film as a mask. against a bit line having a covered structure in the second silicon nitride film, etching the second silicon nitride film as a stopper, it was previously formed in the interlayer insulating film is connected to the silicon substrate forming a contact hole to the plug, the second polycrystalline silicon film having a thickness which does not cover the (c) the contact hole After the product, by depositing a second silicon oxide film, a step of filling the contact hole, as a stopper of the second polycrystalline silicon film (d) the step (c), the contact hole the second silicon oxide film embedded after etch back, as a mask the second silicon oxide film, the first of the second polycrystalline silicon film and the step of said step (c) (a) 1 a step of isotropically etching back the polycrystalline silicon film, the in (e) the first silicon nitride film as a stopper, the second silicon oxide film and the step of said step (d) (a) by etching using a first silicon oxide film hydrogen fluoride aqueous solution, subjected to a step of forming a capacitor electrode, connecting the silicon substrate and (f) the capacitor electrode That the contact hole, and forming the capacitor electrode in a lithographic 1 step. Therefore, a contact hole can be opened easily and in a self-aligning manner, and a method for manufacturing a semiconductor device with a high manufacturing yield can be provided.

  Hereinafter, embodiments of the present invention will be described in detail.

  FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device showing a first reference example of the present invention. Here, a DRAM will be taken as an example and described in detail with reference to the drawings. Note that the memory cell array portion shown in FIG. 1 schematically shows a cross section observed in the AA ′ direction in FIG.

  (1) First, as shown in FIG. 1A, up to a device isolation region 102, a transfer gate 104 on which an offset insulating film 103 is loaded, and a plug 106 are formed through a normal semiconductor device manufacturing process. The plug 106 is formed on the silicon substrate 101 at a position where contact is made with the bit line and the capacitor electrode, and at a position where contact is made between the bit line and the transfer gate 104. Here, the uppermost layer of the interlayer insulating film on which the plug 106 is formed is composed of the first insulating film 105 that can ensure a selection ratio with respect to the insulating film deposited in the next step.

  (2) Next, as shown in FIG. 1B, a second insulating film 107 is deposited and then planarized by CMP. Thereafter, an inverted pattern 108 of the bit line is formed by a normal lithography process, and the second insulating film 107 is etched until the plug 106 is reached using the first insulating film 105 as a stopper to form a groove (contact hole). 109 is formed.

  (3) Next, as shown in FIG. 1C, the groove 109 is filled with the bit line 110, and the bit line 110 is formed by removing the groove 109 from the upper surface of the second insulating film 107. To do. After that, by depositing a third insulating film 111 that can ensure a sufficient selection ratio with respect to the second insulating film 107, the third recess film is completely filled, and then the third insulating film 107 is exposed until the second insulating film 107 is exposed. The insulating film 111 is removed.

  Here, the recess amount when the bit line 110 is removed is such that the third insulating film 111 can ensure the withstand voltage of the capacitor electrode and the bit line 110 and the remaining film of the bit line film satisfying a predetermined bit line resistance. It is set to ensure the thickness.

  (4) Next, as shown in FIG. 1D, after the second insulating film 107 is selectively removed, an insulating film made of the same material as the third insulating film 111 existing in the bit line 110 is formed. The sidewall 112 is formed by depositing and anisotropically etching back. Here, the amount of removal of the second insulating film 107 may be at least the thickness of the third insulating film 111 on the bit line 110, and may be part or all of it.

  (5) Next, as shown in FIG. 1E, after depositing a fourth insulating film 113 capable of ensuring a sufficient selection ratio with respect to the first insulating film 105 and the third insulating film 111. Then, the hole pattern 114 is formed by a normal lithography process. Thereafter, the fourth insulating film 113 is etched while securing the insulation with the bit line 110 by using the third insulating film 111 and the sidewall 112 as stoppers, and the second insulating film 105 is used as the stopper with the first insulating film 105 as a stopper. The capacitor electrode contact hole 115 is opened in the plug 106 by etching the insulating film 107 with a sufficient overetching amount.

  Thereafter, through the normal semiconductor device manufacturing process, the capacitor electrode and subsequent parts are formed, and the semiconductor device is manufactured.

  Thus, according to the first reference example, (1) an interlayer having the first insulating film 105 as the uppermost layer capable of ensuring a sufficient selection ratio with respect to the second insulating film 107 deposited in the second stage. A step of forming a plug 106 for connecting to the upper bit line 110 and the capacitor electrode in the insulating film; and (2) a second insulating film 107 capable of ensuring a sufficient selection ratio with respect to the first insulating film 105. And then flattening, and then etching the second insulating film 107 using the reverse pattern 108 of the bit line 110 as a mask and the first insulating film 105 as a stopper; and (3) Conductivity constituting the bit line 110. Forming the bit line 110 by embedding the pattern 108 with a conductive material and removing the conductive material so that the conductive material has a recess in the second insulating film 107; By depositing a third insulating film 111 capable of securing a sufficient selection ratio with respect to the insulating film 107, the third insulating film 111 is removed until the second insulating film 107 is exposed after the recess is filled. Then, a step of removing the second insulating film, and (5) depositing an insulating film similar to the third insulating film 111, and then anisotropically etching the side surfaces of the bit line 110 completely. And (6) depositing and planarizing a fourth insulating film 113 capable of ensuring a sufficient selection ratio with respect to the first insulating film 105 and the third insulating film 111, and then covering the upper surface of the bit line 110 and By etching the fourth insulating film 113 and the second insulating film 107 using the third insulating film 111 and the first insulating film 105 on the side as stoppers, a contact hole 115 for forming a capacitor electrode is formed. Since so as to manufacture a semiconductor device and a process of formation of the bit lines corresponding to the miniaturization of the semiconductor device becomes possible. In addition, since the bit line can be formed without going through a special lithography process, it is possible to reduce the number of manufacturing steps and the manufacturing cost.

  Next, a second reference example of the present invention will be described.

  In the second reference example, the first insulating film 105 and the third insulating film 111 in the first reference example are made of the same material.

  As described above, according to the second reference example, since the materials of the first insulating film 105 and the third insulating film 111 in the first reference example are the same, the same effects as in the first reference example can be obtained. It is possible to realize.

  Next, a third reference example of the present invention will be described.

  In the third reference example, the materials of the second insulating film 107 and the fourth insulating film 113 in the first reference example are the same.

  As described above, according to the third reference example, since the materials of the second insulating film 107 and the fourth insulating film 113 in the first reference example are the same, the same effects as in the first reference example can be obtained. It is possible to realize.

  Next, a fourth reference example of the present invention will be described.

  In the fourth reference example, the materials of the first insulating film 105 and the third insulating film 111 in the first reference example are the same, and the materials of the second insulating film 107 and the fourth insulating film 113 are the same. It is a thing.

  Thus, according to the fourth reference example, the materials of the first insulating film 105 and the third insulating film 111 in the first reference example are the same, and the second insulating film 107 and the fourth insulating film 113 are the same. Since the materials are the same, it is possible to achieve the same effect as the first reference example.

  Next, a fifth reference example of the present invention will be described.

  In the fifth reference example, a silicon nitride film is used for the first insulating film 105 and the third insulating film 111 in the fourth reference example, and a silicon oxide film is used for the second insulating film 107 and the fourth insulating film 113. It is a thing.

Here, when the conductive material forming the bit line 110 is tungsten polycide, as a method of removing the conductive material so as to have a recess with respect to the second insulating film 107, that is, the silicon oxide film, for example, electrons Some etch back using a cyclotron resonance etching apparatus at a pressure of 5 mTorr, Cl ₂ / O ₂ = 190/10 cc / min, microwave power = 400 W, RF power = 40 W, and electrode temperature = 20 ° C.

  Next, as a method for removing the second insulating film 107, that is, the silicon oxide film, for example, there is a method in which the silicon oxide film is wet-etched with a hydrogen fluoride aqueous solution.

As a method of removing the silicon nitride film until the upper surface of the second insulating film 107, that is, the silicon oxide film is exposed after the recess of the bit line 110 is filled with the third insulating film 111, that is, the silicon nitride film, for example Etching at a pressure = 80 Pa, CF ₄ / O ₂ / Cl ₂ / N ₂ = 270/270/170/80 cc / min, microwave power = 600 W, electrode temperature = 20 ° C. using a wave downflow etching apparatus There is something to do. As a condition for forming the sidewall by anisotropically etching after depositing the third insulating film 111, for example, using a parallel plate type etching apparatus, a pressure of 300 mTorr, Ar / CHF ₃ / CF ₄ = 400 Some are etched at / 25/15 cc / min, RF power = 350 W, electrode temperature = 0 ° C.

As a condition for etching the fourth insulating film 113, that is, the silicon oxide film, using the third insulating film 111 and the first insulating film 105, that is, the silicon nitride film, as a stopper, using a magnetron etching apparatus, pressure = 40 mTorr, Etching is performed at Ar / C ₄ F ₈ / CH ₂ F ₂ = 500/20/7 cc / min, RF power = 1500 W, cooling He pressure, center / edge = 3/40 Torr, and electrode temperature = 40 ° C.

  As described above, according to the fifth reference example, the silicon nitride film is used for the first insulating film 105 and the third insulating film 111 in the fourth reference example, and the second insulating film 107 and the fourth insulating film 113 are used. Since the silicon oxide film is used, the same effect as that of the first reference example can be realized.

  Next, a sixth reference example of the present invention will be described.

  FIG. 8 is a sectional view of a manufacturing process of a semiconductor device showing a sixth reference example of the present invention, and FIG. 9 is a schematic diagram of the contact hole pattern.

  (1) First, as shown in FIG. 8A, after forming an element isolation region on a silicon substrate 501, a transfer gate 503 loaded with an offset insulating film 502 is formed by normal lithography and etching. Needless to say, the transfer gate 503 is set to perform a desired operation through a normal semiconductor device manufacturing process after the formation of the transfer gate 503.

  (2) Next, as shown in FIG. 8B, after depositing the first insulating film 504 and the second insulating film 505, the second insulating film 505 is planarized by CMP. Note that the first insulating film 504 and the second insulating film 505 are combined so that the value of the etch rate ratio, that is, the selectivity is sufficiently high.

  (3) Next, as shown in FIG. 8C, a contact hole pattern (resist) 506 is formed by a normal lithography process. As shown in FIG. 9, the contact hole pattern 506 is a region in which the activation region formed in the step of FIG. 8A is connected to the region where the upper layer wiring or electrode and the plug for connecting the silicon substrate are present. Are designed so that they can be etched at once.

  (4) Next, as shown in FIG. 8D, the second insulating film 505 is etched using the first insulating film 504 as a stopper, and then the first insulating film 504 is etched, thereby plugging. A contact hole 507 for filling in is opened in the silicon substrate.

  (5) Next, as shown in FIG. 8E, after the contact pattern (resist) 506 is ashed, the contact hole 507 is filled with a conductive material that constitutes a plug, and then the offset insulating film 502 is coated. The plug 508 is formed by removing the conductive material until reaching a position lower than the upper surface.

  Thereafter, an electrode or a wiring is connected to the plug 508 via the contact hole 507, whereby a semiconductor device is manufactured.

  As described above, according to the sixth reference example, after the element isolation region and the transfer gate 503 are formed through a normal semiconductor device manufacturing method, (1) a combination of insulating films that can ensure a sufficient selection ratio A step of laminating 504 and 505; and (2) etching the region where the activation region and the region where the plug 508 for connecting to the upper layer wiring or electrode is present are connected to the insulating films 504 and 505 at once. A pattern 506 that can be formed by normal lithography, and the upper insulating film 505 is etched in a self-aligning manner using the insulating film 504 existing in the lower layer of the stacked insulating films 504 and 505 as a stopper. Then, a step of opening a contact hole 507 in the silicon substrate 501 by etching the lower insulating film 504, and this contour Since the hole 507 is filled with a conductive material and the conductive material is removed until reaching a position lower than the upper surface of the offset insulating film 502 on the transfer gate 503, the contact is made in a self-aligning manner. Since the depth to be etched can be suppressed at the stage of forming the hole 507, a semiconductor device manufacturing method with a high manufacturing yield can be provided.

  In addition, since a combination of insulating films 504 and 505 that can secure a sufficient selection ratio is deposited, the plug 508 is formed through a self-aligned etching process using the pattern disclosed in this reference example as a mask. Thereafter, when one or both of the insulating films 504 and 505 are deposited and then a contact hole 507 for connecting a wiring or an electrode is opened to the plug 508, the contact hole 507 is made to the plug 508. Even when the opening is shifted, excessive etching of one of the insulating films 504 and 505 is prevented, so that the semiconductor device is manufactured with only one step of opening the contact hole 507 in a self-aligning manner. It is possible to provide a method for manufacturing a semiconductor device with a high manufacturing yield.

  Next, a seventh reference example of the present invention will be described.

  In the seventh reference example, after the upper (second) insulating film 505 in the sixth reference example is planarized, the lower (first) insulating film 504 on the transfer gate is exposed until the lower insulating film 504 is exposed. In contrast, the upper insulating film 505 is removed with a sufficiently high selection ratio.

  Thus, according to the seventh reference example, it is sufficiently higher than the lower insulating film 504 until the lower insulating film 504 on the transfer gate 503 is exposed after the upper insulating film 505 in the sixth reference example is planarized. Since the upper insulating film 505 is removed at a selection ratio, the depth of the contact hole can be suppressed more than in the sixth reference example, and a semiconductor device manufacturing method with a high manufacturing yield can be provided.

  Next, an eighth reference example of the present invention will be described.

  In the eighth reference example, the offset insulating film 502 in the sixth reference example is made of a silicon oxide film, the lower insulating film 504 used as an etching stopper is made of a silicon nitride film, and the upper insulating film 505 is made of a silicon oxide film. Is. Note that in the case where a silicon nitride film is used for the lower insulating film 504, in order to ensure insulation between the transfer gate 503 and the silicon substrate 501 and the plug 508, the side surfaces of the silicon substrate 501 and the transfer gate 503 are oxidized and then the lower layer. An insulating film 504 may be deposited and is not excluded from the scope of the present invention.

Here, as a condition for etching the silicon oxide film of the upper insulating film 505 using the silicon nitride film of the lower insulating film 504 as a stopper, for example, using a magnetron etching apparatus, pressure = 40 mTorr, Ar / CO / C ₄ F ₈ = 200/150/9 cc / min, RF power = 1300 W, electrode temperature = 30 ° C., electrode spacing = 27 mm, cooling He pressure, center / edge = 3/45 Torr.

Next, as conditions for etching the lower insulating film 504, for example, using a magnetron etching apparatus, pressure = 50 mTorr, Ar / CHF ₃ / O ₂ = 100/20/20 cc / min, RF power = 300 W, electrode temperature = 30 ° C., electrode spacing = 32 mm, cooling He pressure, center / edge = 3/45 Torr.

  Thus, according to the eighth reference example, in the sixth reference example, a silicon oxide film is used as the offset insulating film 502, a silicon nitride film is used as the lower insulating film 504 used as an etching stopper, and a silicon oxide film is used as the upper insulating film 505. Since it did in this way, it is possible to implement | achieve the effect equivalent to a 6th reference example.

  Next, a ninth reference example of the present invention will be described.

  In the ninth reference example, a silicon nitride film is used as the offset insulating film 502 in the eighth reference example.

  Thus, according to the ninth reference example, since the silicon nitride film is used for the offset insulating film 502 in the eighth reference example, it is possible to achieve the same effect as the sixth reference example.

  Next, a tenth reference example of the present invention will be described.

  In the tenth reference example, the offset insulating film 502 in the sixth reference example is formed of a laminated film, and a silicon oxide film is used as the uppermost insulating film 505.

  As described above, according to the tenth reference example, the offset insulating film 502 in the sixth reference example is formed of a laminated film, and the silicon oxide film is used as the uppermost insulating film 505. It is possible to achieve the same effect as. Next, an eleventh reference example of the present invention will be described.

  In the eleventh reference example, the offset insulating film 502 in the sixth reference example is formed of a laminated film, and a silicon nitride film is used as the uppermost insulating film 505.

  As described above, according to the eleventh reference example, the offset insulating film 502 in the sixth reference example is formed of a laminated film, and the silicon nitride film is used as the uppermost insulating film 505. It is possible to achieve the same effect as.

  Next, a first embodiment of the present invention will be described.

  FIG. 10 is a cross-sectional view of a semiconductor device manufacturing process showing the first embodiment of the present invention (part 1), and FIG. 11 is a cross-sectional view of the semiconductor device manufacturing process showing the first embodiment of the present invention (part 2). Hereinafter, it demonstrates in detail according to a figure.

  (1) First, as shown in FIG. 10A, through a normal semiconductor device manufacturing process, an element isolation region, a word line (both not shown), a plug 601 on a silicon substrate 600, a silicon oxide film 602, Bit lines 603 are formed sequentially. Here, the bit line 603 is characterized by being covered with an upper silicon nitride film 604 and a sidewall silicon nitride film 605. As a typical example, the interval between the silicon nitride films 605 on the side walls of the bit line 603 is set to about 0.08 μm. Thereafter, a silicon oxide film 606 is deposited and planarized by CMP, and then a silicon nitride film 607 is deposited.

(2) Next, as shown in FIG. 10B, after a silicon oxide film 608 and a polycrystalline silicon film 609 are sequentially deposited, a hole pattern 610A for forming a capacitor electrode is formed by a normal lithography process. Form. Then, using the silicon oxide film 608 as a stopper, using a parallel plate etching apparatus, for example, a polycrystal under the conditions of pressure 20 mTorr, SF ₆ / HBr = 26/8 cc / min, RF power = 300 W, and cooling He pressure = 4 Torr. After etching the silicon film 609, using the silicon nitride film 607 as a stopper, for example, using a magnetron etching apparatus, pressure = 40 mTorr, Ar / CO / C ₄ F ₈ = 250/100/8 cc / min, RF power = 1300 W The silicon oxide film 608 is etched under the conditions of electrode temperature = 40 ° C., cooling He pressure center / edge = 3/45 Torr, and pressure = 50 mTorr, Ar / CHF ₃ / O ₂ = 100 using, for example, a magnetron etching apparatus. / 25 / 15cc / min, RF power The silicon nitride film 607 is etched under the conditions of − = 300 W, electrode temperature = 40 ° C., cooling He pressure, center / edge = 3/45 Torr.

(3) Next, as shown in FIG. 10C, after the resist 610 is ashed, the silicon nitride film 604 on the bit line 603 and the silicon nitride film 605 on the side wall are used as stoppers, for example, with a magnetron etching apparatus. Silicon oxide under conditions of pressure = 40 mTorr, Ar / CO / C ₄ F ₈ = 200/150/8 cc / min, RF power = 1300 W, electrode temperature = 40 ° C., cooling He pressure center / edge = 3/45 Torr By etching the films 606 and 602, the cell contact hole 611 is opened in a self-aligned manner with respect to the plug 601.

(4) Next, as shown in FIG. 11A, after depositing a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611, the cell contact hole 611 is buried with the silicon oxide film 613. . Thereafter, the silicon oxide film 613 is formed using, for example, a parallel plate etching apparatus, pressure = 500 mTorr, Ar / CHF ₃ / CF ₄ = 400/20/20 cc / min, RF power = 200 W, electrode temperature = 0 ° C. Etching back is performed until the polycrystalline silicon film 612 is exposed under the condition of cooling He pressure = 15 Torr.

(5) Next, as shown in FIG. 11B, using the silicon oxide film 613 as a stopper, for example, using a microwave downflow etching apparatus, pressure = 40 Pa, CF ₄ / O ₂ = 150/60 cc / The silicon oxide film 608 is exposed by isotropically etching back the polycrystalline silicon films 612 and 609 under the conditions of min, microwave power = 700 W, and electrode temperature = 25 ° C.

  (6) Next, as shown in FIG. 11C, the silicon oxide film 608 and 613 are etched with an aqueous hydrogen fluoride solution using the silicon nitride film 607 as a stopper, thereby forming a capacitor electrode 614.

  Then, after depositing a capacitor insulating film, a polycrystalline silicon film is deposited, and a semiconductor device is manufactured through a process of forming a cell plate electrode by a normal lithography process and an etching process.

  According to the first embodiment, (1) a process of processing a laminated film of a polycrystalline silicon film 609, a silicon oxide film 608 and a silicon nitride film 607 by a normal lithography process and an etching process, and (2) the polycrystalline film A silicon oxide film using the silicon nitride films 605 and 604 as a stopper for a bit line 603 having a structure in which the upper and side walls are covered with silicon nitride films 604 and 605 using the silicon film 609 as a mask. Etching the films 606 and 602 to form a cell contact hole 611 in a plug 601 formed in advance; and (3) forming a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611. After the deposition, the contact hole 611 is embedded by depositing a silicon oxide film 613. (4) Etching back the silicon oxide film 613 in which the cell contact hole 611 is buried using the polycrystalline silicon film 612 of the above step (3) as a stopper, and then using the silicon oxide film 613 as a mask. (3) the step of isotropically etching back the polycrystalline silicon film 612 of step (1) and the polycrystalline silicon film 609 of step (1); and (5) oxidation of step (4) using the silicon nitride film 607 as a stopper. Since the silicon film 613 and the silicon oxide film 608 in the above step (1) are etched using an aqueous hydrogen fluoride solution to form a capacitor electrode 614, a semiconductor device is manufactured. It is possible to improve the problem of alignment margin in As a result, a semiconductor device with a high manufacturing yield can be manufactured.

  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.

  Further, in the first embodiment, since the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 609 as a mask when the cell contact hole 611 is etched, the etching can be performed while suppressing the mask height. Therefore, it is possible to cope with further miniaturization.

  In the first embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted, from the viewpoint of securing the contact area with respect to the plug 601, the distance between the silicon nitride films 605 on the side wall + 2 × lithography process It is necessary to form the hole pattern 610A for forming the capacitor electrode 614 with a margin of alignment. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated for the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the first embodiment, the step of forming a sidewall using a polycrystalline silicon film, which was disclosed in the prior art, can be completely eliminated. It is.

  Next, a second embodiment of the present invention will be described.

  In the second embodiment, the polycrystalline silicon films 609 and 612 in the first embodiment are anisotropically etched back, and then the silicon oxide film 608 is etched with an aqueous hydrogen fluoride solution using the silicon nitride film 607 as a stopper. Thus, the capacitor electrode 614 is formed.

  According to the second embodiment, (1) a process of processing a laminated film of the polycrystalline silicon film 609, the silicon oxide film 608 and the silicon nitride film 607 by a normal lithography process and an etching process, and (2) the polycrystalline film A silicon oxide film using the silicon nitride films 604 and 605 as a stopper for a bit line 603 having a structure in which the upper and side walls are covered with the silicon nitride films 604 and 605 using the silicon film 609 as a mask. Etching the films 606 and 602 to form a cell contact hole 611 in a plug 601 formed in advance; and (3) forming a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611. After the deposition, the cell contact hole 611 is formed by depositing a silicon oxide film 613. (4) Etching back the silicon oxide film 613 in which the cell contact hole 611 is buried using the polycrystalline silicon film 612 of the above step (3) as a stopper, and then using the silicon oxide film 613 as a mask. The step of anisotropically etching back the polycrystalline silicon film 612 in the step (3) and the polycrystalline silicon film 609 in the step (1), and the silicon oxide in the step (4) using the silicon nitride film 607 as a stopper Since the film 613 and the silicon oxide film 608 of the above step (1) are etched using an aqueous hydrogen fluoride solution to form a capacitor electrode 614, a semiconductor device is manufactured. It is possible to improve the problem of alignment margin. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.

  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.

  Furthermore, in the second embodiment, since the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 609 as a mask when the cell contact hole 611 is etched, the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.

  In the second embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted, from the viewpoint of securing a contact area with respect to the plug 601, the interval between the silicon nitride films 605 on the side wall + 2 × lithography process It is necessary to form the hole pattern 610A for forming the capacitor electrode with a sufficient margin. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated for the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the second embodiment, it is possible to completely eliminate the step of forming a sidewall using a polycrystalline silicon film, which was disclosed in the prior art. is there.

  Next, a third embodiment of the present invention will be described.

In the third embodiment, the cell contact hole 611 for forming the capacitor electrode 614 is filled using the organic film in the first embodiment, and the organic film and the polycrystalline silicon films 609 and 612 are etched back collectively. Is. In this etch back process, for example, using a magnetron etching apparatus, pressure = 20 mTorr, Cl ₂ / O ₂ = 30/3 cc / min, RF power = 400 W, magnetic field strength = 30 Gauss, electrode temperature = 20 ° C. Conditions apply.

  According to the third embodiment, (1) a process of processing a laminated film of the polycrystalline silicon film 609, the silicon oxide film 608 and the silicon nitride film 607 by a normal lithography process and an etching process, and (2) the polycrystalline film A silicon oxide film using the silicon nitride films 605 and 604 as a stopper with respect to the bit line 603 having a structure in which the upper and side walls are covered with the silicon nitride films 605 and 604 using the silicon film 609 as a mask. Etching the films 606 and 602 to form a cell contact hole 611 in a plug 601 formed in advance; and (3) forming a polycrystalline silicon film 612 having a thickness that does not block the cell contact hole 611. A step of filling the cell contact hole 611 by depositing and then depositing an organic film; (4) Etching back the organic film, the polycrystalline silicon film 612 in the step (3) and the polycrystalline silicon film 609 in the step (1) at a time, and (5) ashing the organic film Then, using the silicon nitride film 607 as a stopper, the silicon oxide film 608 in the above step (1) is etched using an aqueous hydrogen fluoride solution to form a capacitor electrode 614 to manufacture a semiconductor device. Therefore, it is possible to completely solve the alignment margin problem in the lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.

  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.

  Furthermore, in the third embodiment, since the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 609 as a mask when the cell contact hole 611 is etched, it is possible to perform etching while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.

  In the third embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted, from the viewpoint of securing the contact area with respect to the plug 601, the interval between the silicon nitride films 605 on the side wall + 2 × lithography process It is necessary to form the hole pattern 610A for forming the capacitor electrode 614 with a margin of alignment. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated for the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the third embodiment, it is possible to completely eliminate the step of forming a sidewall using a polycrystalline silicon film, which was disclosed in the prior art. is there.

  Next, a fourth embodiment of the present invention will be described.

  In the fourth embodiment, the uppermost layer of the interlayer insulating film in which the plug 601 is formed in the first embodiment is a silicon nitride film.

  According to the fourth embodiment, since the uppermost layer of the interlayer insulating film 602 in which the plug 601 is formed in the first embodiment is a silicon nitride film, the cell contact hole 611 is added to the effect of the first embodiment. Even if the overetching time is increased by this etching, the interlayer insulating film 602 on which the plug 601 is formed is not excessively etched. As a result, the processing margin of the cell contact hole etching process can be expanded, and the yield of the semiconductor device can be further improved.

  Next, a fifth embodiment of the present invention will be described.

  In the fifth embodiment, after the polycrystalline silicon film 609 is etched in the first embodiment and then the resist 610 is ashed, the silicon oxide film 608 and the silicon nitride film 607 are etched using the polycrystalline silicon film 609 as a mask. After that, the silicon oxide films 606 and 602 are etched using the silicon nitride films 605 and 604 on the top and side walls of the bit line 603 as stoppers so that the cell contact holes 611 are opened in the plugs 601 formed in advance. It is a thing.

  According to the fifth embodiment, (1) a process of processing the polycrystalline silicon film 609 by a normal lithography process and an etching process, and (2) a silicon oxide film 608 and a nitrided film using the polycrystalline silicon film 609 as a mask. After etching the laminated film of the silicon film 607, the silicon nitride films 605 and 604 are formed on the bit line 603 formed in advance and covered with the silicon nitride films 605 and 604 at the top and side walls. A step of etching the silicon oxide films 606 and 602 by using as a stopper to form a cell contact hole 611 with respect to the plug 601 formed in advance, and (3) a film thickness that does not block the cell contact hole 611. After the crystalline silicon film 612 is deposited, the silicon oxide film 613 is deposited, whereby the cell controller And (4) using the polycrystalline silicon film 612 of the above step (3) as a stopper, the silicon oxide film 613 in which the cell contact hole 611 is buried is etched back, and then the silicon oxide film 613 is masked. The step (3) isotropically etch back the polycrystalline silicon film 612 and the step (1) polycrystalline silicon film 609, and (5) the step (1) using the silicon nitride film 607 as a stopper. The silicon oxide film 613 of 4) and the silicon oxide film 608 of the above step (1) are etched using an aqueous hydrogen fluoride solution to form a capacitor electrode 614 to manufacture a semiconductor device. Therefore, it is possible to improve the problem of alignment margin in the lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.

  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.

  Furthermore, in the fifth embodiment, when the cell contact hole 611 is etched, the silicon oxide film 608, the silicon nitride film 607, and the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 609 as a mask. Etching with reduced thickness becomes possible, and it becomes possible to cope with further miniaturization of the semiconductor device.

  In the fifth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted, from the viewpoint of securing the contact area with respect to the plug 601, the interval between the silicon nitride films 605 on the side wall + 2 × lithography process It is necessary to form the hole pattern 610A for forming the capacitor electrode 614 with a margin of alignment. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated as the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the fifth embodiment, it is possible to completely eliminate the process of forming the sidewall using the polycrystalline silicon film.

  Next, a sixth embodiment of the present invention will be described.

  In the sixth embodiment, after etching the polycrystalline silicon film 609 and the silicon oxide film 608 in the first embodiment and then ashing the resist 610, the silicon nitride film 607 is etched using the polycrystalline silicon film 609 as a mask. After that, the silicon oxide films 606 and 602 are etched using the silicon nitride films 605 and 604 on the top and side walls of the bit line 603 as stoppers so that the cell contact holes 611 are opened in the plugs 601 formed in advance. It is a thing.

  According to the sixth embodiment, (1) a process of processing the polycrystalline silicon film 609 and the silicon oxide film 608 by a normal lithography process and an etching process, and (2) nitriding using the polycrystalline silicon film 609 as a mask. After etching the silicon film 607, the silicon nitride films 605 and 604 are used as stoppers for the bit line 603 formed in advance and covered with the silicon nitride films 605 and 604. Etching the silicon oxide films 606 and 602 to form a cell contact hole 611 in a plug 601 formed in advance; and (3) a polycrystalline silicon film having a thickness that does not block the cell contact hole 611. 612 is deposited, and then a silicon oxide film 613 is deposited, whereby the cell contact hole is formed. And (4) using the polycrystalline silicon film 612 of the above step (3) as a stopper and etching back the silicon oxide film 613 in which the cell contact hole 611 is buried, and then using the silicon oxide film 613 as a mask. A step of isotropically etching back the polycrystalline silicon film 612 in the step (3) and the polycrystalline silicon film 609 in the step (1); and (5) the step (4) using the silicon nitride film 607 as a stopper. ) And the silicon oxide film 608 in the above step (1) are etched using an aqueous hydrogen fluoride solution to form a capacitor electrode 614 to manufacture a semiconductor device. Therefore, it is possible to improve the alignment margin problem in the lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.

  In addition, since the cell contact hole 611 and the capacitor electrode 614 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.

  Further, in the sixth embodiment, when the cell contact hole 611 is etched, the silicon nitride film 607 and the silicon oxide films 606 and 602 are etched using the polycrystalline silicon film 612 as a mask. Therefore, it becomes possible to cope with further miniaturization of the semiconductor device.

  In the sixth embodiment, even when the alignment of the cell contact hole 611 with respect to the bit line 603 is shifted, from the viewpoint of securing the contact area with respect to the plug 601, the interval between the silicon nitride films 605 on the side wall + 2 × lithography process It is necessary to form the hole pattern 610A for forming the capacitor electrode 614 with a margin of alignment. For example, when the interval between the silicon nitride films 605 is 0.08 μm, the minimum size of the hole pattern 610A to be formed is 0.28 μm when 0.1 μm is estimated as the alignment margin in the lithography process. Since this can be formed by a normal lithography process, in the sixth embodiment, the step of forming the sidewall using the polycrystalline silicon film can be completely eliminated.

  Next, a twelfth reference example of the present invention will be described.

  The twelfth reference example uses a capacitor electrode film other than the polycrystalline silicon film in the first embodiment.

  FIG. 12 is a cross-sectional view of a manufacturing process of a semiconductor device showing a twelfth reference example of the present invention (No. 1), and FIG. 13 is a cross-sectional view of a manufacturing process of a semiconductor device showing a twelfth reference example of the present invention.

  (1) First, FIG. 12A to FIG. 12C are not different from the first embodiment of the present invention shown in FIG. 700 is a silicon substrate, 701 is a plug, 702 is a silicon oxide film, 703 is a bit line, 704 and 705 are silicon nitride films, 706 is a silicon oxide film, 707 is a silicon nitride film, 708 is a silicon oxide film, and 709 is A polycrystalline silicon film, 710 is a resist, 711 is a hole pattern, and 712 is a cell contact hole.

  (2) Next, as shown in FIG. 12D, a titanium film having a thickness that does not block the cell contact hole 712 is deposited by, for example, CVD, and then the polycrystalline silicon film of the plug 701 is formed by heat treatment. The titanium film is reacted to form a titanium silicide layer 713. Thereafter, for example, titanium in an unreacted portion is removed with a mixed aqueous solution of ammonia and hydrogen peroxide. At this time, a titanium silicide layer 713 also exists in the mask due to the reaction between the polycrystalline silicon film constituting the mask (polycrystalline silicon film) 709 and the titanium film.

  (3) Next, as shown in FIG. 13A, a titanium nitride film 714 having a thickness that does not block the cell contact hole 712 is deposited by, for example, CVD. Thereafter, the cell contact hole 712 is filled with the silicon oxide film 715, and the silicon oxide film 715 is etched back until the titanium nitride film 714 is exposed.

  (4) Next, as shown in FIG. 13B, using the silicon oxide film 715 as a mask, a titanium nitride film 714, a titanium silicide layer 713 generated by the reaction with the mask, and a polycrystalline silicon film 709 as a mask are formed. Etch back until the silicon oxide film 708 is exposed.

  (5) Next, as shown in FIG. 13 (c), this step is the same as the first embodiment of the present invention shown in FIG. That is, the capacitor electrode 716 is formed by etching the silicon oxide film 708 and the silicon oxide film 715 with a hydrogen fluoride aqueous solution using the silicon nitride film 707 as a stopper.

  Then, after depositing a tantalum oxide film as a capacitor insulating film, for example, by CVD, and then depositing a titanium nitride film as a cell plate electrode film, for example, by CVD, and forming a cell plate electrode by normal lithography and etching After that, the semiconductor device is manufactured.

  According to the twelfth reference example, (1) a process of processing a laminated film of the polycrystalline silicon film 709, the silicon oxide film 708 and the silicon nitride film 707 by a normal lithography process and an etching process; With respect to the bit line 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705 using the silicon film 709 as a mask, silicon oxide is used with the silicon nitride films 704 and 705 as a stopper. A step of etching the films 708 and 706 to form a cell contact hole 712 in the plug 701 formed in advance, and (3) a polycrystalline silicon film of the plug 701 by depositing a titanium film and then performing heat treatment. And a step of forming a titanium silicide layer 713 by reacting a titanium film with (4) nitriding The step of filling the cell contact hole 712 by depositing the silicon oxide film 715 after the deposition of the titanium film 714, and (5) the cell contact hole 712 using the titanium nitride film 714 in the step (4) as a stopper. After the buried silicon oxide film 715 is etched back, the titanium nitride film 714 in the step (4), the titanium silicide layer 713 in the step (3), and the step (1) using the silicon oxide film 715 as a mask. (6) Using the silicon nitride film 707 as a stopper, the silicon oxide film 715 in the above step (5) and the silicon oxide film 708 in the above step (1) are treated with hydrogen fluoride. The capacitor electrode 716 is formed by etching using an aqueous solution. Subjected to extent. Thus the production of semiconductor devices, it is possible to improve the problem of alignment margin in lithography process. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.

  In addition, since the cell contact hole 712 and the capacitor electrode 716 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.

  Further, in the twelfth reference example, since the silicon oxide films 708 and 706 are etched using the polycrystalline silicon film 709 as a mask when the cell contact hole 712 is etched, the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.

  In addition to the above, since the capacitor electrode is composed of a titanium nitride film, a capacitor insulating film having a high relative dielectric constant such as tantalum oxide can be used.

  In the twelfth reference example, even when the alignment of the cell contact hole 712 with respect to the bit line 703 is deviated, from the viewpoint of securing the contact area with respect to the plug 701, the interval between the silicon nitride films 705 on the side wall + 2 × in the lithography process It is necessary to form the hole pattern 711 for forming the capacitor electrode 716 with a margin of alignment. For example, when the interval between the silicon nitride films 705 is 0.08 μm, if 0.1 μm is estimated for the alignment margin in the lithography process, the minimum size of the hole pattern 711 to be formed is 0.28 μm. Since this can be formed by a normal lithography process, in the twelfth reference example, the step of forming the sidewall using the polycrystalline silicon film can be completely eliminated.

  Next, a thirteenth reference example of the present invention will be described.

  The thirteenth reference example embeds a cell contact hole 712 for forming the capacitor electrode 716 using an organic film in the twelfth reference example, fills the organic film with a titanium nitride film 714, a titanium silicide layer 713, and a polycrystalline silicon film 709. Are etched back at once.

  According to the thirteenth reference example, (1) a process of processing a laminated film of a polycrystalline silicon film 709, a silicon oxide film 708, and a silicon nitride film 707 by a normal lithography process and an etching process; With respect to the bit line 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705 using the silicon film 709 as a mask, the silicon nitride films 704 and 705 are used as a stopper to oxidize the bit line 703. Etching the silicon films 706 and 702 to form a cell contact hole 712 in the plug 701 formed in advance; and (3) depositing a titanium film having a thickness that does not block the cell contact hole 712. Then, a step of forming a titanium silicide layer 713 by heat treatment, and (4) titanium nitride A step of filling the cell contact hole 712 by depositing an organic film after depositing 714, (5) the organic film, the titanium nitride film 714 in the step (4), and the titanium film in the step (3). Etch back the silicide layer 713 and the polycrystalline silicon film 709 in the step (1) at a time, and (6) oxidation of the step (1) using the silicon nitride film 707 as a stopper after the organic film is ashed. By etching the silicon film 708 using an aqueous hydrogen fluoride solution to perform the step of forming the capacitor electrode 716 to manufacture the semiconductor device, the problem of alignment margin in the lithography process is improved. Is possible. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.

  In addition, since the cell contact hole 712 and the capacitor electrode 716 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.

  Further, in the thirteenth reference example, when the cell contact hole 712 is etched, the silicon oxide films 706 and 702 are etched using the polycrystalline silicon film 709 as a mask, so that the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.

  In addition to the above, since the capacitor electrode 716 is formed of a titanium nitride film, a capacitor insulating film having a high relative dielectric constant such as tantalum oxide can be used.

  In the thirteenth reference example, even when the alignment of the cell contact hole 712 with respect to the bit line 703 is deviated, from the viewpoint of securing the contact area with respect to the plug 701, the interval between the silicon nitride films 705 on the side wall + 2 × in the lithography process It is necessary to form the hole pattern 711 for forming the capacitor electrode 716 with a margin of alignment. For example, when the interval between the silicon nitride films 705 is 0.08 μm, the minimum size of the hole pattern 711 to be formed is 0.28 μm when the alignment margin in the lithography process is estimated to be 0.1 μm. Since this can be formed by a normal lithography process, in the thirteenth reference example, the step of forming the sidewall using the polycrystalline silicon film can be completely eliminated.

  Next, a fourteenth reference example of the present invention is described.

  In the fourteenth reference example, after the cell contact hole 712 in the thirteenth reference example is opened, the cell contact hole 712 is filled with an organic film, and the polycrystalline silicon film 709 constituting the organic film and the mask is etched back collectively. The titanium film is deposited after the organic film is ashed.

  According to the fourteenth reference example, (1) a process of processing a laminated film of a polycrystalline silicon film 709, a silicon oxide film 708, and a silicon nitride film 707 by a normal lithography process and an etching process; Using the silicon film 709 as a mask, a bit line 703 having a structure in which the upper and side walls are covered with the silicon nitride films 704 and 705 is etched using the silicon nitride films 704 and 705 as a stopper. A step of forming a cell contact hole 712 in the plug 701 formed in advance, and (3) filling the cell contact hole 712 with an organic film, and the organic film and the polycrystalline silicon film in the step (1). (4) ashing the organic film, and the cell contact hole 712 A step of forming a titanium silicide layer 713 by a heat treatment after depositing a titanium film having an unblocked thickness; and (5) depositing a titanium nitride film 714 and then depositing an organic film to thereby form the contact hole 712. (6) Etching back the organic film and the titanium nitride film 714 in the above step (5), and (7) ashing the organic film, and then using the silicon nitride film 707 as a stopper Since the silicon oxide film 708 in the first step is etched using an aqueous hydrogen fluoride solution to form the capacitor electrode 716, the semiconductor device is manufactured. It is possible to improve the problem of margin. Thereby, it is possible to manufacture a semiconductor device with a high manufacturing yield.

  In addition, since the cell contact hole 712 and the capacitor electrode 716 are formed in one lithography process, a semiconductor device can be manufactured at a low manufacturing cost.

  Furthermore, in the fourteenth reference example, when the cell contact hole 712 is etched, the silicon oxide films 708 and 702 are etched using the polycrystalline silicon film 709 as a mask, so that the etching can be performed while suppressing the mask height. It becomes possible to cope with further miniaturization of the apparatus.

  In addition to the above, since the capacitor electrode 716 is composed of the titanium nitride film 714, a capacitor insulating film having a high relative dielectric constant such as tantalum oxide can be used.

  In the fourteenth reference example, even when the alignment of the cell contact hole 712 with respect to the bit line 703 is deviated, from the viewpoint of securing the contact area with respect to the plug 701, the interval between the silicon nitride films 705 on the side wall + 2 × in the lithography process It is necessary to form the hole pattern 711 for forming the capacitor electrode 716 with a margin of alignment. For example, when the interval between the silicon nitride films 705 is 0.08 μm, the minimum size of the hole pattern 711 to be formed is 0.28 μm when the alignment margin in the lithography process is estimated to be 0.1 μm. Since this can be formed by a normal lithography process, the step of forming a sidewall using a polycrystalline silicon film can be completely eliminated in this reference example.

  Next, a fifteenth reference example of the present invention is described.

  FIG. 14 is a cross-sectional view of a semiconductor device manufacturing process (part 1) showing a fifteenth reference example of the present invention, and FIG. 15 is a cross-sectional view of a semiconductor device manufacturing process (part 2) showing a fifteenth reference example of the present invention.

  (1) First, as shown in FIG. 14A, an element isolation region, a word line (both not shown), a silicon substrate 801, a plug 801A, and a bit line 804 are sequentially formed through a normal semiconductor device manufacturing process. To do. Here, the interlayer insulating film between the plug 801A and the bit line 804 is characterized in that a lower layer is formed of a silicon nitride film 802 and an upper layer is formed of a silicon oxide film 803. Thereafter, a silicon oxide film 805 is deposited and planarized by CMP, and then a silicon nitride film 806 is deposited.

(2) Next, as shown in FIG. 14B, a silicon oxide film 807 and a polycrystalline silicon film 808 are sequentially deposited, and then a hole pattern 809 is formed by a normal lithography process. Thereafter, for example, using a parallel plate etching apparatus, the polycrystalline silicon film 807 is used as a stopper under the conditions of a pressure of 20 mTorr, SF ₆ / HBr = 26/8 cc / min, RF power = 300 W, and cooling He pressure = 4 Torr. After anisotropically etching the silicon film 808, for example, using a magnetron etching apparatus, pressure = 40 mTorr, Ar / CO / C ₄ F ₈ = 250/100/8 cc / min, RF power = 1300 W, electrode temperature The hole 810 is formed by anisotropically etching the silicon oxide film 807 using the silicon nitride film 806 as a stopper under the conditions of = 40 ° C. and cooling He pressure center / edge = 3/45 Torr.

(3) Next, as shown in FIG. 14C, after the resist (hole pattern) 809 is ashed, a polycrystalline silicon film is deposited, for example, an electron cyclotron resonance (hereinafter abbreviated as ECR) etching apparatus. Is used to anisotropically etch under conditions of pressure = 5 mTorr, Cl ₂ = 100 cc / min, microwave power 400 W, RF power = 50 W, electrode temperature = −20 ° C., thereby forming a sidewall 811, An etching mask 812 made of polycrystalline silicon having an opening diameter smaller than that of the hole 810 is formed.

(4) Next, as shown in FIG. 14 (d), under a condition that a sufficient selection ratio is obtained with respect to the etching mask 812, for example, using a magnetron etching apparatus in the first step, a pressure of 35 mTorr, CHF _The silicon nitride film 806 is etched under the conditions of ₃ / CO = 30/170 cc / min, RF power = 1600 W, cooling He back pressure, center / edge = 3/70 Torr, and electrode temperature −10 ° C.

Then, in a second step, by using a magnetron etching apparatus, pressure _{= 30mTorr, Ar / C 4 F} 8/02 = 300/10 / 8cc / min, RF power = 1500 W, the cooling He backpressure Center / Edge = The silicon oxide film 805 and the silicon oxide film 803 below the bit line 804 are anisotropically etched using the silicon nitride film 802 as a stopper under the conditions of 3/45 Torr and electrode temperature = −10 ° C. In step, pressure = 40 mTorr, Ar / CH ₂ F ₂ / O ₂ = 100/10/20 cc / min, RF power = 300 W, cooling He back pressure, center / edge = 3/45 Torr, electrode temperature = −10 ° C. By etching the silicon nitride film 802, a contact hole 813 is opened over the plug 801A. Hereinafter, the contact hole 813 is referred to as a cell contact hole.

  (5) Next, as shown in FIG. 15A, after depositing a polycrystalline silicon film 814 having a thickness that does not embed the cell contact hole 813, a silicon oxide film 815 is deposited to thereby form the cell contact hole 813. Embed.

Thereafter, the silicon oxide film 815 is subjected to pressure = 500 mTorr, Ar / CHF ₃ / CF ₄ = 400/20/20 cc / min, RF power using, for example, a parallel plate etching apparatus until the polycrystalline silicon film 814 is exposed. Etch back under the conditions of = 200 W, electrode temperature = 0 ° C, cooling He pressure = 15 Torr.

(6) Next, as shown in FIG. 15 (b), using the silicon oxide film 815 as a mask, the polycrystalline silicon film 814 and the etching mask 812 are subjected to pressure = 40 Pa using a microwave downflow etching apparatus, for example. , CF ₄ / O ₂ = 150/60 cc / min, microwave power = 700 W, electrode temperature = 25 ° C.

  (7) Next, as shown in FIG. 15C, the silicon oxide films 807 and 815 are etched with a hydrogen fluoride aqueous solution using the silicon nitride film 806 as a stopper to form a capacitor electrode 816.

  Thereafter, after depositing a capacitor insulating film, a polycrystalline silicon film for forming a cell plate electrode is deposited, and a step of forming a cell plate electrode by a normal lithographic process is performed to manufacture a semiconductor device.

  According to the fifteenth reference example, (1) a hole formed in the laminated film of the polycrystalline silicon film 808 and the silicon oxide film 807 using the silicon nitride film 806 as a stopper by a normal lithography process and an etching process is formed from the polycrystalline silicon. (2) using the polycrystalline silicon film 812 with a reduced opening diameter as a mask and using the silicon nitride film 802 immediately above the plug 801A as a stopper, a contact hole 813 with respect to the plug 801A. And (3) a step of burying the cell contact hole 813 by depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813 and then depositing a silicon oxide film 815. And (4) the polycrystalline silicon film 814 in the above step (3) is a stopper. The silicon oxide film 815 in which the cell contact hole 813 is buried is etched back, and then the polycrystalline silicon film 814 in the step (3) and the polycrystalline silicon in the step (2) are used with the silicon oxide film 815 as a mask. Using the step of isotropically etching back the film 812, and using the silicon nitride film 806 as a stopper, the silicon oxide film 815 in the above step (4) and the silicon oxide film 807 in the above step (1) are used with an aqueous hydrogen fluoride solution. Since the semiconductor device is manufactured by performing the process of forming the capacitor electrode 816 by etching, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography process, and the manufacturing cost is reduced. A semiconductor device which is low and has a high manufacturing yield can be manufactured.

  In the fifteenth reference example, since self-alignment cannot be expected in the direction perpendicular to the bit lines 804, a sufficient alignment margin can be secured for the mask size in the direction perpendicular to the bit lines 804 with respect to the interval between the bit lines 804. It must be reduced to a degree. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.

  Next, a sixteenth reference example of the present invention will be described.

  In the sixteenth reference example, the polycrystalline silicon film 814 and the etching mask 812 are anisotropically etched back using the silicon oxide film 815 in which the cell contact hole 813 in the fifteenth reference example is embedded as a mask, and then the silicon nitride film The capacitor electrode 816 is formed by etching the silicon oxide films 815 and 807 with an aqueous hydrogen fluoride solution using 806 as a stopper.

  According to the sixteenth reference example, (1) a hole 810 having an opening with a silicon nitride film 806 as a stopper is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 by a normal lithography process and an etching process. (2) using the polycrystalline silicon film 812 whose opening diameter is reduced as a mask, and using the silicon nitride film 802 immediately above the plug 801A as a stopper, a cell is formed with respect to the plug 801A. A step of forming a contact hole 813; and (3) depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing a silicon oxide film 815, thereby forming the contact hole 813. A step of burying, and (4) the polycrystalline silicon film 814 of the above step (3). As a topper, the silicon oxide film 815 in which the cell contact hole 813 is buried is etched back, and then the polycrystalline silicon film 814 in the step (3) and the polycrystalline in the step (2) are used with the silicon oxide film 815 as a mask. A step of anisotropically etching back the silicon film 812, and (5) using the silicon nitride film 806 as a stopper, the silicon oxide film 815 in the step (4) and the silicon oxide film 807 in the step (1) are hydrogen fluoride. Since the semiconductor device is manufactured by performing the step of forming the capacitor electrode 816 by etching using an aqueous solution, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography step. It is possible to manufacture semiconductor devices with low manufacturing cost and high manufacturing yield. .

  In the sixteenth reference example, since self-alignment cannot be expected in the direction perpendicular to the bit lines 804, a sufficient alignment margin can be secured for the mask size in the direction perpendicular to the bit lines 804 with respect to the interval between the bit lines 804. It must be reduced to a degree. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.

  Next, a seventeenth reference example of the present invention will be described.

  In the seventeenth reference example, the cell contact hole 813 in the fifteenth reference example is filled with an organic film, the organic film, the polycrystalline silicon film 814, and the etching mask 812 are etched back together, and then the organic film is incinerated. After that, the capacitor electrode 816 is formed by etching the silicon oxide film 807 with an aqueous hydrogen fluoride solution using the silicon nitride film 806 as a stopper.

  According to the seventeenth reference example, (1) a hole 810 having an opening with a silicon nitride film 806 as a stopper is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 by a normal lithography process and etching process. (2) using the polycrystalline silicon film 812 whose opening diameter is reduced as a mask, and using the silicon nitride film 802 immediately above the plug 801A as a stopper, a cell is formed with respect to the plug 801A. A step of forming the contact hole 813; and (3) depositing the polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing the organic film to bury the cell contact hole 813. Step (4) This organic film and the polycrystalline silicon film 81 in the above step (3) And a step of collectively etching back the polycrystalline silicon film 812 in the step (2), and (5) after the organic film is ashed, using the silicon nitride film 806 as a stopper, the silicon oxide film 807 in the step (1). Since the semiconductor device is manufactured by performing the process of forming the capacitor electrode 816 by etching using a hydrogen fluoride aqueous solution, the cell contact hole 813 and the capacitor electrode 816 are formed in one lithography process. Therefore, it is possible to manufacture a semiconductor device with a low manufacturing cost and a high manufacturing yield.

  In the seventeenth reference example, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, a sufficient alignment margin is secured for the mask size in the direction perpendicular to the bit line 804 with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.

  Next, an eighteenth reference example of the present invention will be described.

  In the eighteenth reference example, after the plug formation in the fifteenth reference example, the interlayer insulating film between the plug 801A and the bit line 804 is composed of a silicon nitride film 802 as an upper layer and a silicon oxide film 803 as a lower layer. is there.

  According to the eighteenth reference example, (1) a hole 810 having an opening with a silicon nitride film 806 as a stopper by a normal lithography process and an etching process is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 in a stacked film. (2) using the polycrystalline silicon film 812 whose opening diameter is reduced as a mask, and using the silicon nitride film 802 immediately below the bit line 804 as a stopper, with respect to the plug 801A. A step of forming a cell contact hole 813; and (3) depositing a polycrystalline silicon film 814 having a thickness that does not block the cell contact hole 813, and then depositing a silicon oxide film 815, thereby forming the cell contact hole. A step of embedding 813, and (4) the polycrystalline silicon film 81 of the above step (3). Is used as a stopper to etch back the silicon oxide film 815 in which the cell contact hole 813 is buried, and then using the silicon oxide film 815 as a mask, the polycrystalline silicon film 814 in the step (3) and the multiple steps in the step (2) are used. A step of isotropically etching back the crystalline silicon film 812, and (5) using the silicon nitride film 806 as a stopper, the silicon oxide film 815 in the step (4) and the silicon oxide film 807 in the step (1) are fluorinated. Since the semiconductor device is manufactured by performing the step of forming the capacitor electrode 816 by etching using an aqueous hydrogen solution, the cell contact hole 813 and the capacitor electrode 816 can be formed in one step of lithography. Therefore, it is possible to manufacture semiconductor devices with low manufacturing costs and high manufacturing yield. That.

  In the eighteenth reference example, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, a sufficient alignment margin is secured for the mask size in the direction perpendicular to the bit line 804 with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.

  Next, a nineteenth reference example of the present invention is described.

  In the nineteenth reference example, after the processes of FIGS. 14A to 14D are performed, the process of FIG. 12D and the processes of FIGS. 13A to 13C are performed. .

  That is, in the nineteenth reference example, after the cell contact hole 813 in the fifteenth reference example is opened, (1) a titanium film having a thickness that does not block the cell contact hole 813 is deposited by CVD, and then heat treatment is performed. A step of forming a silicide layer by reacting the polycrystalline silicon film of the plug with the titanium film; and (2) removing the unreacted portion of the titanium film with a mixed aqueous solution of ammonia and hydrogen peroxide, and then performing the cell by CVD. A step of depositing a titanium nitride film having a thickness that does not block the contact hole 813; and (3) filling the cell contact hole 813 with the silicon oxide film 815 and etching back the silicon oxide film 815 until the titanium nitride film is exposed. And (3) a titanium nitride film using the silicon oxide film 815 as a mask. Etching back the silicide layer and mask polycrystalline silicon film 812 until the silicon oxide film 807 is exposed, and (4) using the silicon nitride film 806 as a stopper, the silicon oxide film 815 and the silicon oxide film 807 used for filling are buried. After performing the step of forming the capacitor electrode 816 by etching with an aqueous hydrogen fluoride solution, after depositing a tantalum oxide film as a capacitor insulating film, for example, by CVD, as a cell plate electrode film, for example, as CVD A semiconductor device is manufactured by depositing a titanium nitride film and performing a process of forming a cell plate electrode by normal lithography and etching.

  According to the nineteenth reference example, (1) a hole 810 opened by using a silicon nitride film 806 as a stopper by a normal lithography process and an etching process is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 in a stacked film. (2) contact with the plug 801A using the polycrystalline silicon film 812 with a reduced opening diameter as a mask and the silicon nitride film 802 immediately above the plug 801A as a stopper; A step of forming a hole 813; and (3) by depositing a titanium film having a thickness that does not block the cell contact hole 813 by CVD, and then reacting the polycrystalline silicon film of the plug 801A with the titanium film by heat treatment. A step of forming a silicide layer, and (4) titani of an unreacted portion. (5) depositing a titanium nitride film having a thickness that does not block the cell contact hole 813 by CVD after removing the film with a mixed aqueous solution of ammonia and hydrogen peroxide; and (5) forming the contact hole 813 with silicon oxide. A step of etching back the silicon oxide film 815 until the titanium nitride film is exposed, and (6) using the silicon oxide film 815 as a mask, a titanium nitride film, a silicide layer, and a polycrystalline silicon film 812 serving as a mask are embedded. A step of etching back until the silicon oxide film 807 is exposed; and (7) using the silicon nitride film 806 as a stopper, the silicon oxide film 815 in the step (5) and the silicon oxide film 807 in the step (1) are hydrogen fluoride. Forming a capacitor electrode 816 by etching with an aqueous solution; Thus, the semiconductor device is manufactured, so that the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography process, and a semiconductor device with a low manufacturing cost and a high manufacturing yield can be manufactured. .

  Furthermore, in the nineteenth reference example, since the capacitor electrode 816 is made of a titanium nitride film, a capacitor electrode having a high relative dielectric constant such as tantalum oxide can be used.

  In the nineteenth reference example, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, the mask size in the direction perpendicular to the bit line 804 has a sufficient alignment margin with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.

  Next, a twentieth reference example of the present invention will be described.

  In the twentieth reference example, the cell contact hole 813 for forming the capacitor electrode 816 is filled using the organic film in the nineteenth reference example, and the organic film and the titanium nitride film / silicide layer / polycrystalline silicon film 812 are etched together. It is something to be backed.

  According to the twentieth reference example, (1) a hole 810 having an opening with a silicon nitride film 806 as a stopper is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 by a normal lithography process and an etching process. (2) Contact with the plug 801A using the polycrystalline silicon film 812 with the reduced opening diameter as a mask and the silicon nitride film 802 immediately above the plug 801A as a stopper. A step of forming a hole 813; and (3) by depositing a titanium film having a thickness that does not block the cell contact hole 813 by CVD, and then reacting the polycrystalline silicon film of the plug 801A with the titanium film by heat treatment. A step of forming a silicide layer, and (4) titani of an unreacted portion. And (5) depositing a titanium nitride film having a thickness that does not block the cell contact hole 813 by CVD, and (5) forming the cell contact hole 813 into an organic layer. A step of etching back the organic film, the titanium nitride film, the silicide layer, and the polycrystalline silicon film 812 as a mask, and (6) ashing the organic film and then using the silicon nitride film 806 as a stopper Since the silicon oxide film 807 in the above step (1) is etched with an aqueous hydrogen fluoride solution to form a capacitor electrode 816, a semiconductor device is manufactured. Therefore, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography process, and the manufacturing cost is low. Remain is possible to manufacture a semiconductor device with high.

  Furthermore, in the twentieth reference example, the capacitor electrode 816 is made of the titanium nitride film, so that it is possible to use a capacitor electrode having a high relative dielectric constant such as tantalum oxide.

  In the 20th reference example, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, a sufficient alignment margin is secured for the mask size in the direction perpendicular to the bit line 804 with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.

  Next, a twenty-first reference example of the present invention will be described.

  In the twenty-first reference example, after opening the cell contact hole 813 in the nineteenth reference example, the cell contact hole 813 is filled with an organic film, and the polycrystalline silicon film 812 constituting the organic film and the mask is etched back in a lump. The titanium film is deposited after the organic film is ashed.

  According to the twenty-first reference example, (1) a hole 810 having an opening with a silicon nitride film 806 as a stopper is formed in a polycrystalline silicon film 808 and a silicon oxide film 807 by a normal lithography process and an etching process. (2) Contact with the plug 801A using the polycrystalline silicon film 812 with the reduced opening diameter as a mask and the silicon nitride film 802 immediately above the plug 801A as a stopper. Forming a hole 813; (3) filling the cell contact hole 813 with an organic film; etching back the organic film and the polycrystalline silicon film 812 in the above step (2); and (4) organic After the film is ashed, a titanium film having a thickness that does not block the contact hole 813 is deposited. A step of forming a silicide layer by heat treatment, (5) a step of filling the contact hole 813 by depositing an organic film after depositing a titanium nitride film, and (6) the step of filling the organic film, step (5) (1) Etching back the titanium nitride film in a lump; (7) After ashing the organic film, using the silicon nitride film 806 as a stopper, the silicon oxide film 807 in the above step (1) using a hydrogen fluoride aqueous solution Since the semiconductor device is manufactured by performing the process of forming the capacitor electrode 816 by etching, the cell contact hole 813 and the capacitor electrode 816 can be formed in one lithography process, and the manufacturing cost is increased. And a semiconductor device with a high manufacturing yield can be manufactured.

  Furthermore, in the twenty-first reference example, since the capacitor electrode 816 is made of a titanium nitride film, a capacitor electrode having a high relative dielectric constant such as tantalum oxide can be used.

  In the twenty-first reference example, since self-alignment cannot be expected in the direction perpendicular to the bit line 804, a sufficient alignment margin is secured for the mask size in the direction perpendicular to the bit line 804 with respect to the interval between the bit lines 804. It must be reduced as much as possible. However, in the direction parallel to the bit line 804, the mask size can be increased within a range not exceeding the unit cell area. As a result, a sufficient capacitor capacity can be ensured, and a semiconductor device can be manufactured without sacrificing performance.

  In addition, this invention is not limited to the said Example, Based on the meaning of this invention, a various deformation | transformation is possible and these are not excluded from the scope of the present invention.

  The method for manufacturing a semiconductor device of the present invention is particularly suitable for a wiring formation method, an electrode formation method, and a contact hole formation method in a semiconductor device.

It is a manufacturing process sectional view of a semiconductor device showing the 1st reference example of the present invention. It is a schematic diagram which shows the observation direction of the semiconductor device which shows the 1st reference example of this invention. It is manufacturing process sectional drawing of the conventional 1st semiconductor device. It is manufacturing process sectional drawing (the 1) of the conventional 2nd semiconductor device. FIG. 10 is a manufacturing process cross-sectional view (No. 2) of the conventional second semiconductor device; It is manufacturing process sectional drawing (the 1) of the conventional 3rd semiconductor device. It is manufacturing process sectional drawing (the 2) of the conventional 3rd semiconductor device. It is sectional drawing of the manufacturing process of the semiconductor device which shows the 6th reference example of this invention. It is a schematic diagram of the contact hole pattern of the semiconductor device which shows the 6th reference example of this invention. FIG. 6 is a sectional view of the semiconductor device according to the first embodiment of the present invention in the manufacturing process (No. 1). FIG. 3 is a manufacturing process cross-sectional view (No. 2) of the semiconductor device showing the first embodiment of the invention; It is manufacturing process sectional drawing (the 1) of the semiconductor device which shows the 12th reference example of this invention. It is a manufacturing process sectional drawing (the 2) of the semiconductor device which shows the 12th reference example of this invention. It is manufacturing process sectional drawing (the 1) of the semiconductor device which shows the 15th reference example of this invention. It is manufacturing process sectional drawing (the 2) of the semiconductor device which shows the 15th reference example of this invention.

Explanation of symbols

101, 501, 600, 700, 801 Silicon substrate 102 Element isolation region 103, 502 Offset insulating film 104, 503 Transfer gate 105, 504 First insulating film 106, 508, 601, 701, 801A Plug 107, 505 Second Insulating film 108 Bit line inversion pattern 109 Groove (contact hole)
110, 603, 703, 804 Bit line 111 Third insulating film 112 Side wall 113 Fourth insulating film 114, 610A, 711, 809 Hole pattern 115 Capacitor electrode contact hole 506 Contact hole pattern (resist)
507 Contact hole 602, 606, 608, 613, 702, 706, 708, 715, 803, 805, 807, 815 Silicon oxide film 604, 704 Upper silicon nitride film 605, 705 Side silicon nitride film 607, 707, 802 , 806 Silicon nitride film 609, 612, 709, 808, 814 Polycrystalline silicon film 610, 710 Resist 611, 712, 813 Cell contact hole 614, 716, 816 Capacitor electrode 713 Titanium silicide layer 714 Titanium nitride film 810 Hole 811 Side Wall 812 Polycrystalline silicon film (etching mask)

Claims (6)

In a method for manufacturing a semiconductor device having a contact hole forming step for connecting a capacitor electrode of a semiconductor device and a silicon substrate, and a capacitor electrode forming step,
(A) a step of processing by the first polycrystalline silicon film, the first silicon oxide film and lithography a stacked film of the first silicon nitride film and etching steps,
(B) as a mask said first polycrystalline silicon film was previously formed, with respect to the bit line having a covered structure with top and side walls in the second silicon nitride film, the second nitride Etching using a silicon film as a stopper, forming a contact hole for a plug connected to the silicon substrate and previously formed in the interlayer insulating film ;
(C) burying the contact hole by depositing a second silicon oxide film after depositing a second polycrystalline silicon film having a thickness that does not block the contact hole;
Said second polycrystalline silicon film (d) the step (c) as a stopper, the second silicon oxide film embedded with the contact hole after the etching back, the second silicon oxide film as a mask a step of isotropically etching back said first polysilicon film in the above step (c) the second polycrystalline silicon film and the step (a), the
(E) the first silicon nitride film as a stopper, be etched using the first oxide silicon film hydrogen fluoride aqueous solution of the second silicon oxide film and the step of said step (d) (a) And a step of forming a capacitor electrode,
(F) a contact hole for connecting the capacitor electrode and the silicon substrate, and a method of manufacturing a semiconductor device characterized by forming the capacitor electrode in a lithographic 1 step. The method of manufacturing a semiconductor device according to claim 1, wherein the first polycrystalline silicon film of the second polycrystalline silicon film and the step of said step (c) said second silicon oxide film as a mask (a) A method for manufacturing a semiconductor device, characterized by anisotropically etching back instead of isotropically. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after depositing the second polycrystalline silicon film in the step (c) having a film thickness that does not block the contact hole, an organic film is deposited to deposit the contact film. A semiconductor device , wherein holes are filled and the organic film , the second polycrystalline silicon film in the step (c) and the first polycrystalline silicon film in the step (a) are etched back at once . Production method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an uppermost layer of a third silicon oxide film stacked on the interlayer insulating film in which the plug is formed is the first silicon nitride film. Manufacturing method. The method of manufacturing a semiconductor device according to claim 1, wherein the first polycrystalline silicon film in a resist is ashed after etching, the first silicon oxide film using the first polycrystalline silicon film as a mask , after etching the first silicon nitride film, a third silicon oxide film and the interlayer insulating film stacked on the interlayer insulating film using the second silicon nitride film of said bit lines top and side walls as a stopper A method for manufacturing a semiconductor device, wherein a part of the semiconductor device is etched. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after etching the first polycrystalline silicon film and the first silicon oxide film and ashing a resist, the first polycrystalline silicon film is masked. as the first silicon nitride film after etching the third silicon oxide film which is laminated on the interlayer insulating film using the second silicon nitride film of said bit lines top and side walls as a stopper for the interlayer insulating film A method for manufacturing a semiconductor device, wherein a part of the semiconductor device is etched.

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