JPH08331678A - Time slot replacement circuit - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Effectively prevent reading of unnecessary data to the output with a simple configuration. Each buffer circuit includes dual port memories 17 and 18 having a data readable / writable port P1 and a data writable port P2. After writing input data from the port P1, the stored data is stored in the port P1. From the port P to the same address after reading the data.
Predetermined data is written within the same memory cycle time as the data read from 2. Alternatively, each buffer circuit includes dual port memories 27 and 28 having a data writable port P1 and a data readable port P2, and after input data is written from the port P1, read from the port P2 and data is read. Predetermined data is written to the same address from the port P1 within the same memory cycle time as data reading.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time slot interchange circuit, and more specifically, it writes input data alternately in first and second buffer circuits in a random mode according to connection information of a system and stores the stored data in a sequential mode. The present invention relates to a double buffer type time slot switching circuit which alternately reads from the second and first buffer circuits to form output data.

The time slot replacement circuit is used for subscriber transmission equipment, switching equipment, digital cross-connect equipment, PBX.
It is widely used as a means for realizing a time switch in, for example. In recent years, as the number of accommodated subscribers has increased, the number of time slots accommodated per unit time (for example, one frame) has also increased. For this reason, the speed and capacity of the time switch memory have been increasing, but this type of time slot replacement circuit requires masking of unnecessary data, which will be described later, and is desired to be realized efficiently.

[0003]

2. Description of the Related Art FIG. 5 is a diagram for explaining the prior art.
FIG. 1A shows a block diagram of an example of a time slot switching circuit according to the conventional double buffer system. In the figure, 1
˜4 is a 3-state buffer circuit (BF), 5 and 6 are data selectors (SEL), 7 and 8 are RAM, 9 is a write counter (WC), 10 is an address control memory (ACM), and 11 is a sequential read. Counter (SR
C).

When the system surface switching signal FSL = 1, R
Input data is written in AM7, and output data is read from RAM8 at the same time. The details will be described below. On the side of the RAM 7, when FSL = 1, the buffer circuit 1 is energized,
Input data is added to the data terminal DA of the RAM 7.
The RAM 7 is in the data write mode W with FSL = 1. On the other hand, the write counter 9 sequentially counts up by the write clock signal WCK synchronized with the input data. The ACM 10 converts the count output of the write counter 9 into a corresponding random write address signal RWA according to the connection information of the system. Selector 5 is FS
The input a side is selected when L = 1, and the input b side is selected when FSL = 0. Since FSL = 1 now, the random write address RWA on the a side is selected. Along with this, the write clock signal WCK is selected, and this is applied to the strobe terminal STB of the RAM 7 as the data write pulse signal WP. In this way, the input data is sequentially written in the random write address RWA of the RAM 7.

On the side of the RAM 8, when FSL = 1, the buffer circuit 4 is energized and the read data of the RAM 8 becomes output data. The RAM 8 is in the data read mode R when FSL = 1. On the other hand, the sequential read counter 11 counts up sequentially by the read clock signal RCK. The selector 6 selects the input a side when FSL = 1 and the input b side when FSL = 0. Since FSL = 1 now, the a-side sequential read address SRA is selected. At the same time, if necessary, the read clock signal RCK is selected and added to the strobe terminal STB of the RAM 8 as the data read enable signal RE. In this way, the output data is sequentially read from the RAM 8.

The surface switching signal FSL is inverted every unit time (one frame), and when the surface switching signal FSL = 0, the operation is the reverse of the above case. In this way, time slot replacement processing between input and output data is continuously performed. next,
Problems of the conventional technique will be described with reference to FIG. Address AD of ACM 10 in the frame at time (t)
= 0 to 3 indicates time slot replacement data “0, 3,
2, * ”is stored. The symbol "*" represents a non-connected state, and is information indicating an impossible address in the RAM 7, for example.

In this state, the input data is "A, B, C,
If you enter in the order of "-", the first data "A" is in RAM7.
The second data “B” is stored in the RAM 7 at the address “0” of
The third data "C" at the address "3" of the RAM7
Are written in the respective addresses "2". The fourth input data "-" is unconnected (invalid) data and is written in the impossible address "*" of the RAM 7.

Data stored in RAM 7 "A,-, C, B"
Are sequentially read in the frame at time (t + 1), and the time slots are switched from the input channels "A, B, C,-" to the output channels "A,-, C, B". In this state, when a new request for connection, disconnection, switching, etc. of a call occurs, the system rewrites the time slot replacement data of the ADM 10. The data for time slot replacement is rewritten by utilizing the free time of the fum.

In the frame at time (t + 2), AC
Time slot replacement data “0, 3, *, *” is stored in the address AD = 0 to 3 of M10. That is,
Here, the input channel "2" is disconnected.
In this state, the input data continues to be "a, b,-,-"
, The first data “a” is written to the address “0” of the RAM 7 and the second data “b” is written to the address “3” of the RAM 7. The third and subsequent data "-" is unconnected data and is written in the impossible address "*" of the RAM 7.

As a result, the old data "C" at the address "2" in the RAM 7 remains unerased, and when this is read at the frame at time (t + 3), unnecessary data is read. Conventionally, the following two methods have been used to solve problems. Random write address RW of output of selector 5/6
The information of A is monitored over one frame, and information such as effective write address RWA = "0, 3" is stored.
In the next sequential read frame, the read data from the stored effective write address “0, 3” is output, but the read data from the other write addresses “1, 2” is not output (instead, it is not connected. The data "-" is output).

However, according to the above method, an extra memory or the like for storing the information of the effective write address and the like is required, and the circuit becomes complicated and large-scaled. RAM in the sequential read frame
Two memory access cycles of read and write are provided on 7/8, and unconnected data "-" is written to the same address immediately after reading output data.

However, according to the above method, the RAM 7
In the case of / 8 sequential read, the memory access time which is twice as long as that of read and write is required, which reduces the number of time slots that can be accommodated within a unit time (1 frame). It is possible to use the high-speed RAMs 7 and 8, but this causes increase in heat generation, power consumption, cost, and the like.

[0013]

According to the conventional method as described above, the circuit becomes complicated and large-scaled, or the number of time slots that can be accommodated in the system decreases.
Alternatively, there is a disadvantage that heat generation, power consumption, cost, and the like increase. An object of the present invention is to provide a time slot replacement circuit in which reading of unnecessary data to an output can be effectively prevented with a simple configuration.

[0014]

[Means for Solving the Problems] The above-mentioned problems are shown in FIG.
It is solved by the configuration of. That is, the time slot switching circuit of the present invention (1) alternately writes the input data to the first and second buffer circuits in the random mode according to the connection information of the system, and the stored data in the sequential mode to the second and second buffer circuits. In the double buffer type time slot interchange circuit which alternately reads from one buffer circuit to form output data, each buffer circuit includes a data readable / writable first port P1 and a data writable second port P2. The dual port memories 17 and 18 having the above are provided, and after input data is written from the first port P1, the stored data is read from the first port P1 and at the same address after reading the data from the second port P2. The predetermined data is written within the same memory cycle time as the data read.

The above problem can be solved by the structure of FIG. That is, in the time slot interchange circuit of the present invention (2), in the same time slot interchange circuit, each buffer circuit is a dual port having a data writable first port P1 and a data readable second port P2. Equipped with memories 27 and 28, input data to the first port P
After writing from 1, the stored data is read from the second port P2, and at the same address after reading the data, predetermined data is written within the same memory cycle time as the data read from the first port P1.

[0016]

According to each of the above inventions, since each buffer circuit has the dual port memory, the output data can be read and the predetermined data (for example, unconnected data) can be written in the same memory cycle time. Therefore, reading of unnecessary data to the output can be effectively prevented with a simple configuration.

[0017]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 is a block diagram of the time slot switching circuit of the first embodiment. The same components as those in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted.

In the figure, 10 is, for example, 10 bits × 20.
48 Word Address Control Memory (ADM), 1
5 and 16 are selectors (SEL), 17 and 18 are 8bi respectively
t × 2048 Word dual port RAM (DPRA
M) and 19 are delay circuits (DL), and 20 is a sequential write counter (SWC). Delay circuit 19 delays data read clock signal RCK by one clock to form delayed write clock signal WCKD. The sequential write counter 20 receives the delayed write clock signal W
1 more than the sequential read counter 11 by CKD
It counts up with a clock phase delay.

The first ports (left side in the figure) of the DPRAMs 17 and 18 are configured to be capable of reading / writing data. on the other hand,
The second port (on the right side of the figure) is dedicated to writing data, preferably to reduce circuit size. Focusing on the operation of the DPRAM 17, the first port of the DPRAM 17 is set to the data write mode W by the plane selection signal FSL = 1 of the system. Thereby, the input data is written in the random mode from the first port according to the random write address RWA of the ACM 10. Further, the first port is in the data read mode R when FSL = 0. This allows DPRA
The storage data of M17 is sequentially read from the first port according to the sequential read address SRA of SRC11.

On the other hand, the second port of the DPRAM 17 is dedicated to writing data, and the fixed unconnected data "-" is used.
Are sequentially written from the second port according to the sequential write address SWA of SWC20. However, when FSL = 1 (that is, when writing input data to the DPRAM 17), the selector 15 selects the LOW level on the input terminal b side, and therefore the data write pulse signal to the strobe signal terminal STB is selected. There is no WP input, and unconnected data "-" is not written. On the other hand, F
When SL = 0 (that is, when the output data is read from the DPRAM 17), the selector 15 selects the delayed write clock signal WCKD on the input terminal a side, and the data write pulse signal WP based on this selects the unconnected state. Data "-" is written.

The operation of DPRAM 18 is the reverse of the above,
It can be easily analogized. FIG. 3 is an operation timing chart of the time slot switching circuit of the first embodiment. However, in the figure, the buffer size of the DPRAMs 17 and 18 is set to 8 words for the sake of simplicity of description. Focusing on the operation of the DPRAM 17, in each frame at time (t) and (t + 2), the random write mode W of the input data and the intermediate time (t +).
In the frame 1), the output data is in the sequential read mode R.

In the frame at time (t), ACM1
Time slot replacement data "0, 3, 2, *, *, *, *, *" is stored in the address AD = 0 to 7 of 0. In this state, the input data is "A, B, C,-,
When inputting in the order of −, −, −, −, the first data “A” is stored in the address “0” of the DPRAM 17 and the second data “B” is stored in the address “3” of the DPRAM 17, 3
The second data "C" is the address "2" of DPRAM17.
Are randomly written from the first port. Each input data "-" after the 4th is unconnected data, and D
It is written in the impossible address “*” of the PRAM 17.

In the frame at time (t + 1), DP
The data stored in the RAM 17 is sequentially read from the first port according to the sequential read address SRA = "0" to "7" of the SRC 11. On the other hand, SWC
20 is 1 from the sequential read address SRA
Sequential write address S with a phase delay of clock
WA = “0” to “7” is generated. This allows DPRA
All the stored data in M17 are all rewritten by the unconnected data “−” from the second port after reading each stored data.

FIG. 3 shows a case where the timing of writing the unconnected data "-" to the final address "7" of the DPRAM 17 overlaps with the frame at time (t + 2). However, normally, there is a vacancy (time margin) within a frame or between frames, and in this case, no overlap occurs. In the frame at time (t + 2), AC
Time slot replacement data "0, 3, *, *, *, *, *, *" is stored in the address AD = 0 to 7 of M10. That is, the channel "2" is disconnected.
In this state, the input data continues to be "a, b,-,-,
When inputting in the order of −, −, −, −, the first data “a” is written in the address “0” of the DPRAM 17 and the second data “b” is written in the address “3” of the DPRAM 17. Each input data "-" after the third is unconnected data and is written in the impossible address "*" of the DPRAM 17.

According to the first embodiment, all the data stored in the DPRAM 17 is initialized by the unconnected data "-" in the frame at time (t + 1), so that at time (t + 2).
In this frame, the old data "C" at the address "2" in the DPRAM 17 will not remain unerased. Thus, with a simple structure, reading of unnecessary data is effectively prevented.

FIG. 4 is a block diagram of the time slot switching circuit of the second embodiment. In the figure, 21 and 22 are 3-state buffer circuits (BF), and 27 and 28 are dual port RAM (DPRAM). The first ports (left side in the figure) of the DPRAMs 27 and 28 are dedicated to data writing, and the second ports (right side in the figure) are dedicated to reading data.

Focusing on the operation of the DPRAM 27, the FS
When L = 1, input data, random write address RWA, and data write pulse WP are applied to the first port,
As a result, the input data is written from the first port of the DPRAM 27. On the other hand, since the input of the read enable terminal RE is LOW level, the second port does not read data.

When FSL = 0, the input of the read enable terminal RE of the second port becomes HIGH level, and DP
The data stored in the RAM 27 is sequentially read according to the sequential read address SRA. At the same time, unconnected data "-", delayed sequential write address SWA, and delayed data write pulse WP are applied to the first port, whereby unconnected data "-" is written from the first port of DPRAM 27.

The operation of DPRAM 28 is the reverse of the above,
It can be easily analogized. According to the second embodiment, general-purpose (commercially available) DPRAMs 27 and 28 can be used, and the circuit can be realized at low cost. In each of the above embodiments, the case where each counter circuit counts in ascending order has been described, but the present invention can be realized even when the counter circuit counts in descending order.

In each of the above embodiments, the case where the sequential write counter 20 counts up with a phase delay of one clock from the sequential read counter 11 has been described, but the present invention is not limited to this. It may be more than 2 clocks. Further, the delay sequential write address SWA may be generated by a method of subtracting a predetermined value from the count output SRA of the sequential read counter 11.

Although the preferred embodiments of the present invention have been described above, it goes without saying that various changes in configuration and control can be made without departing from the spirit of the present invention.

[0032]

As described above, according to the present invention, unnecessary data can be effectively prevented from being read to the output with a simple structure.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a time slot switching circuit of the first embodiment.

FIG. 3 is an operation timing chart of the time slot switching circuit of the first embodiment.

FIG. 4 is a block diagram of a time slot switching circuit according to a second embodiment.

FIG. 5 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 17, 18, 27, 28 Dual port memory

Claims (2)

[Claims] 1. Input data is alternately written to first and second buffer circuits in a random mode according to connection information of the system, and stored data is alternately read from the second and first buffer circuits in a sequential mode. In a double-buffer type time slot interchange circuit used as output data, each buffer circuit includes a dual port memory having a first port capable of reading / writing data and a second port capable of writing data, After writing from the first port, the stored data is read from the first port, and predetermined data is written to the same address after reading the data from the second port within the same memory cycle time as data reading. And time slot replacement circuit. 2. The input data is alternately written to the first and second buffer circuits in a random mode according to the connection information of the system, and the stored data is alternately read from the second and first buffer circuits in a sequential mode. In a double-buffer type time slot interchange circuit used as output data, each buffer circuit is provided with a dual port memory having a data writable first port and a data readable second port, and the input data After the data is written from the port, the stored data is read from the second port, and at the same address after the data is read, the predetermined data is written within the same memory cycle time as the data read from the first port. Time slot replacement circuit.