JPH08330606A - Zener zap diode and manufacture thereof - Google Patents

Abstract

PURPOSE: To form a Zener zap diode, without damaging the function of this diode even if using a high m.p. metal electrode material, such that unwanted capacitances are removed and reverse current increase is suppressed. CONSTITUTION: A Zener zap diode 1 is formed on a semiconductor film formed on an insulation film 12, its cathode electrode 17 and anode electrode 18 are formed after etching the semiconductor film on a contact part. Accordingly, even a Zener zap diode using a high, m. p. metal electrode material can be easily zapped at trimming. Unwanted capacitance is not added to the diode and reserve current increase is also avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for adjusting resistance by a Zener zap diode, and more particularly to a structure and manufacturing method of the Zener zap diode.

[0002]

2. Description of the Related Art When a reference voltage is generated in a semiconductor integrated circuit, resistance adjustment (trimming) is required to bring the voltage into the standard range. Conventionally, resistance trimming in a semiconductor integrated circuit has been performed by utilizing destruction of a Zener diode.
E Journal of Solid-StateC
ircuits, Vol. SC-10, No. 6, p
p. 412-416, (Dec. 1975). FIG. 5 shows a conventional structure of a Zener zap diode in this general semiconductor integrated circuit.

FIG. 5 shows an NP of a bipolar semiconductor integrated circuit.
Similar to the N-transistor part, a junction between the emitter and the base of this NPN transistor is used, and the emitter is used as the cathode and the base is used as the anode to form Zener diodes. The structure of the conventional Zener zap diode is intended to utilize the breakdown of the Zener diode when trimming. A Zener zap diode having an NPN transistor structure of a bipolar semiconductor integrated circuit will be described with reference to FIG.

In FIG. 5, a second conductivity type (N ⁺ type) buried diffusion layer 52 is formed on an upper layer of the first conductivity type (P type) semiconductor substrate 51. A second conductivity type (N type) epitaxial layer 53 is formed on the upper surface of the P type semiconductor substrate 51. In a part of the lower layer of the epitaxial layer 53, the impurities of the N ⁺ type buried diffusion layer 52 are diffused to form the N ⁺ type buried diffusion layer 52. Further, in the N-type epitaxial layer 53, a first conductivity type (P-type) element isolation layer 54 is formed so as to surround the epitaxial layer 53 above the buried diffusion layer 52 and reach the P-type semiconductor substrate 51. Are formed.

A first conductivity type (P type) diffusion layer 55 is formed in a portion above the N ⁺ type buried diffusion layer 52 and above the N type epitaxial layer 53.
The P-type diffusion layer 55 corresponds to the base diffusion layer of the NPN transistor. A part of the P type diffusion layer 55 is formed on the P ⁺ type diffusion layer 56 in order to improve the contact resistance with the electrode.
Are formed. A second conductivity type (N ⁺ type) high-concentration diffusion layer 57 is formed in a part of the upper layer of the P type diffusion layer 55 without being joined to the P ⁺ type diffusion layer 56. The N ⁺ type high concentration diffusion layer 57 corresponds to the emitter diffusion layer of the NPN transistor. Further, an N ⁺ -type high concentration diffusion layer 58 is formed on the N-type epitaxial layer 53 so as not to be joined to the P-type diffusion layer 55. This N
^{The +} type high-concentration diffusion layer 58 corresponds to the collector portion of the NPN transistor, and is configured to be connected to the N ⁺ type high-concentration diffusion layer 57 through the N-type epitaxial layer 53.

Further, an interlayer insulating film 61 is formed on the upper surface of the N type epitaxial layer 53. And P ⁺
A contact hole 62 is formed in the interlayer insulating film 61 on the mold diffusion layer 56, and P is formed through the contact hole 62.
A wiring 63 connected to the ⁺ type diffusion layer 56 is formed.
The wiring 63 is a base electrode and serves as an anode electrode of the Zener zap diode. In addition, the interlayer insulating film 6 on the N ⁺ type high concentration diffusion layer 57 and the N ⁺ type high concentration diffusion layer 58.
1, the contact holes 64 and 65 are formed,
Through the contact holes 64 and 65, the N ⁺ type high concentration diffusion layer 57 and the N ⁺ type high concentration diffusion layer 58 are connected by the wiring 66. The wiring 66 connects the emitter electrode and the collector electrode and becomes the cathode electrode wiring in the Zener zap diode.

In such a Zener zap diode using the emitter of the NPN transistor as the cathode and the base as the anode, the collector portion is surrounded by the P-type semiconductor and the insulating film, so that the potential is unstable. Therefore, it is a general Zener zap diode configuration in which the collector portion is connected to the emitter electrode by the power supply wiring or the wiring 66 as shown in FIG. By doing this, the junction capacitance between the base and collector is added in addition to the original parasitic capacitance of the Zener zap diode,
A large capacitance enters between the zener zap diode and the wiring or in parallel with the zener zap diode. Generally, the Zener zap diode used for trimming the resistor is configured in a semiconductor integrated circuit by connecting it in parallel with the resistor to be trimmed.Other Zener zap diodes that do not cause zener breakdown at the time of trimming the resistor are power supplies. It is regarded as a capacitance that enters between the wiring and the resistor or a capacitance that enters in parallel with the resistor, and becomes a problem when the semiconductor integrated circuit handles high frequency characteristics and the like. Further, in the Zener zap diode in which the emitter and the collector are connected to serve as the cathode, the NP junction area between the anode and the base becomes large, the reverse current of the zener zap diode increases, and accurate resistance trimming is performed. There is also the problem that it becomes impossible to do.

Furthermore, under the present circumstances in which the junction breakdown voltage of the integrated circuit constituent elements is also decreasing with the miniaturization of the semiconductor integrated circuit, a Zener zap diode having an NPN transistor structure in which the emitter and the collector are connected is a resistor. In some cases, the breakdown occurs between the collector and the silicon substrate (P-type semiconductor) at the time of breaking the zener for trimming.

On the other hand, due to the progress of semiconductor technology, the density of semiconductor integrated circuits has been further increased, and the miniaturization of elements has been promoted.
OI (Silicon on Insulator) and polysilicon films have been used as active elements and passive elements to form a three-dimensional semiconductor integrated circuit configuration. Further, with the miniaturization of elements, a shallower junction is required, and the electrode wiring material also melts with silicon and easily breaks the shallow junction. Instead of a low melting point metal such as aluminum, a high melting point metal and a low melting point metal are used. Stacked electrodes made of metal have come to be used. In this way, with the progress of high integration, when the collector portion is formed in such a manner that the refractory metal is joined to silicon, the Zener zap diode is zener-destructed to melt the metal in silicon and the short circuit due to the NP junction destruction. There has also been a problem that it is difficult to cause a condition (zapping).

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems. That is, according to the present invention, in the Zener zap diode using the emitter and the base of the NPN transistor of the semiconductor integrated circuit, since the collector part is connected to the emitter wiring or the power supply wiring, the zener zap diode which does not zapping is connected in parallel. Another problem is to solve the problem that the capacitance between the resistors or the capacitance between the resistor and the power supply wiring causes unnecessary capacitance on the integrated circuit.

Another object of the present invention is that when the conventional Zener zap diode described above has a collector portion connected to the emitter wiring, the reverse current of the zener zap diode that does not zapping becomes large, and an accurate resistance is obtained. It is to solve the problem that it becomes impossible to perform trimming.

Further, in the Zener zap diode utilizing the emitter and base of the NPN transistor of the semiconductor integrated circuit, in the structure in which the collector part is connected to the emitter part, the collector part and the silicon substrate (P-type semiconductor) are broken at the time of zener breakdown. Is to solve the problem of being destroyed.

Furthermore, it is another object to solve the problem that zapping is difficult when a high-melting-point metal wiring material comes to be used due to the demand for shallower junctions due to the advancement of miniaturization of elements due to the high integration circuit. .

[0014]

DISCLOSURE OF THE INVENTION The present invention is proposed in order to solve the above-mentioned problems. A semiconductor film is formed on an insulating film, and a semiconductor of the first conductivity type and a second conductivity type are formed on the semiconductor film. A zener zap diode is configured by forming a semiconductor junction and forming a second conductivity type semiconductor so as to surround the first conductivity type semiconductor in a ring shape.

According to the present invention, in the Zener zap diode formed by joining the semiconductor of the first conductivity type and the semiconductor of the second conductivity type on the semiconductor film on the insulating film, the contact portion of the semiconductor of the second conductivity type is etched. The method is characterized in that an electrode material is deposited later and then electrode wiring is formed.

Furthermore, according to the present invention, in the Zener zap diode configured to etch the contact portion of the second conductivity type semiconductor, overetching is performed when the semiconductor film is etched using the contact opening portion of the insulating film as a mask. After that, a high melting point metal and a low melting point metal are deposited, and the low melting point metal is in direct contact with the side wall of the etched semiconductor film.

[0017]

As described above, by forming the Zener zap diode on the semiconductor film on the insulating film, only the cathode and the anode are formed. Therefore, the NP of the conventional semiconductor integrated circuit
Unlike the Zener zap diode using the N-transistor, it is not necessary to connect the separated collector part to the other electrode terminal for potential stabilization, and the unnecessary capacitance of the above-mentioned unnecessary part due to the existence of the collector part is eliminated. There is no destruction of the junction between the collector and the semiconductor substrate (P type) at the time of addition or Zener breakdown. Further, there is no increase in the reverse current of the Zener zap diode, which is a problem in the conventional Zener zap diode in which the emitter and the collector are connected.

As described above, by forming the Zener zap diode on the insulating film, a three-dimensional structure is obtained and the degree of integration of the semiconductor integrated circuit can be improved.

Due to high integration of semiconductors, shallow junction is required, and contact with silicon by refractory metal wiring is indispensable. When trimming resistance by Zener zap diode, zapping becomes difficult. When the laminated wiring structure of the high melting point metal and the low melting point metal is taken after the etching of the semiconductor film as described above, the low melting point metal can be brought into contact with the sidewall of the etched semiconductor film, and zapping can be easily performed. It will be possible.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the accompanying drawings. However, the Zener zap diode of the present invention is used for resistance trimming of a semiconductor integrated circuit, and the attached drawings given as specific examples of the present invention show that a semiconductor integrated circuit formed in a semiconductor substrate is formed, It shows the structure after that.

Embodiment 1 The Zener zap diode of this embodiment will be described with reference to the schematic sectional view of FIG. 1A and the schematic plan view of FIG. 1B.
As shown in the figure, the insulating film 12 is formed on the semiconductor substrate 11. An island-shaped first conductivity type (P type) semiconductor 14 and a first conductivity type (P ⁺ type) semiconductor 16 are formed on the insulating film 12.
And the second conductivity type (N ⁺ type) semiconductor 15 is formed inside. An insulating film 13 is formed on the island-shaped semiconductor film.
And a contact opening is formed in the insulating film in a portion corresponding to the second conductivity type (N ⁺ type) semiconductor 15 and the first conductivity type (P ⁺ type) semiconductor 16. Electrode wirings 17 and 18 are formed through the contact portions so as to be connected to the respective conductivity types formed on the semiconductor film. This electrode wiring 17
And the electrode wiring 18 serve as the cathode and the anode of the Zener zap diode, respectively.

Next, a method of manufacturing the Zener zap diode of this embodiment will be described with reference to FIGS. First, as shown in FIG. 2A, 500 nm to 10 nm is formed on the semiconductor substrate 11 by atmospheric pressure CVD using silane and oxygen gas.
A 00 nm oxide film 12 is deposited. Next, boron was removed by about 1E by low pressure CVD using disilane and diborane gas.
A polysilicon film (first conductivity type (P-type) semiconductor) 14 doped with 18 / cm ³ is deposited to a thickness of about 200 nm. The doping of boron into this polysilicon film may be carried out by ion implantation of boron into the polysilicon film of the low pressure CVD using disilane gas. Next, as shown in FIG. 2B, a polysilicon film (first conductivity type (P type) semiconductor) 14 is formed.
Is etched into an island shape, and arsenic is ion-implanted into the polysilicon film at about 1E16 / cm ² using the photoresist as a mask to form a second conductivity type (N ⁺ type) semiconductor 15. Next, in order to reduce the contact resistance of the first conductivity type (P type) semiconductor 14 and the internal resistance of the Zener diode, the first conductivity type is adjacent to the second conductivity type (N ⁺ type) semiconductor 15 and is surrounded. The (P ⁺ type) semiconductor 16 is formed by ion implantation of boron (about 5E15 / cm ² ). Then C
A VD oxide film 13 is deposited to a thickness of about 500 nm.

Next, as shown in FIG. 2C, contact openings for taking out electrodes of the first conductivity type (P ⁺ type) semiconductor 16 and the second conductivity type (N ⁺ type) semiconductor 15 are formed in the CVD oxide film 13. It is formed by etching. Then, an aluminum film containing 1 to 3% silicon is deposited by sputtering to have a thickness of about 700 nm. By patterning this aluminum film, the electrode wiring 17 of the second conductivity type (N ⁺ type) semiconductor 15 and the electrode wiring 1 of the first conductivity type (P ⁺ type) semiconductor 16 are patterned.
8 is formed. In this way, the Zener diode is formed on the insulating film.

Embodiment 2 In this embodiment, a semiconductor integrated circuit is highly integrated, and a zener zap diode in a semiconductor integrated circuit in which the use of a refractory metal as an electrode material is essential is used. Regarding the Zener zap diode structure and the manufacturing method when the electrode material is made of a common refractory metal, FIG.
This will be described with reference to (b).

In this embodiment, FIG. 2 (a) used for explaining the method of manufacturing the Zener zap diode in the first embodiment.
2C, the manufacturing method and the structure up to the one shown in FIG. 2B are exactly the same, and thus duplicated description will be omitted.
Thereafter, as shown in FIGS. 3A and 3B, a contact for taking out electrodes of the first conductivity type (P ⁺ type) semiconductor 16 and the second conductivity type (N ⁺ type) semiconductor 15 from the CVD oxide film 13. The opening is formed by etching. Next, the CVD oxide film 13
Conductive type (P ⁺ type) by anisotropic RIE using as mask
The semiconductor 16 and the second conductivity type (N ⁺ type) semiconductor 15 are etched, and this etching is stopped halfway to form a structure as shown in FIG. 3A, or this etching is performed until the semiconductor film disappears. A structure as shown in FIG. 3B is formed.

Next, Ti / T which is an electrode material of high melting point metal
An iN film 19 is deposited to a thickness of about 200 nm by sputtering, and thereafter aluminum films 17 and 18 containing 1 to 3% of silicon are deposited to a thickness of about 700 nm by sputtering. Further, the Ti / TiN film and the aluminum film are patterned to form the electrodes of the Zener zap diode. In this way, when the electrode material is deposited by sputtering on the surface of the semiconductor film etched by anisotropic RIE using the CVD oxide film 13 as a mask, the side wall has a thickness of 1/2 or less of the electrode thickness on the plane. Is normal. Therefore, T
When the i / TiN film thickness is 200 nm, 100 n on the side wall
m or less, and not a uniform film surface but partially thin,
When the aluminum film is sputtered after the film surface is removed, the aluminum film on the side wall is in contact with silicon with a thin Ti / TiN film interposed, or there is a portion in direct contact with silicon. Therefore, generally, when a refractory metal is used as an electrode material, it is difficult to zapping the Zener zap diode, but the zener zap diode structure as shown in FIG. 3A or 3B is adopted. Then, zapping can be performed with the same ease as in the case of the first embodiment in which the electrode material of the refractory metal is not used.

Example 3 This example relates to a structure and a manufacturing method of a Zener zap diode using an electrode material of a refractory metal as in the case of Example 2. The structure and the manufacturing method are improved from Example 2. The function of the Zener zap diode is improved, which will be described with reference to FIGS. 4 (a) and 4 (b).

In this embodiment, FIG. 2A used for explaining the method of manufacturing the Zener zap diode in the first embodiment.
2C, the manufacturing method and the structure up to the one shown in FIG. 2B are exactly the same, and thus duplicated description will be omitted.
Thereafter, as shown in FIGS. 4A and 4B, a contact for taking out electrodes of the first conductivity type (P ⁺ type) semiconductor 16 and the second conductivity type (N ⁺ type) semiconductor 15 from the CVD oxide film 13. The opening is formed by etching. Next, the CVD oxide film 13
Of the first conductivity type (P
^{The (+} type) semiconductor 16 and the second conductivity type (N ⁺ type) semiconductor 15 are etched, and this etching is stopped midway.
The structure as shown in FIG. 4A is formed, or the structure as shown in FIG. 4B is formed by performing this etching until the semiconductor film is used up. By performing such isotropic RIE, the semiconductor film below the CVD oxide film 13 is etched larger than the contact opening of the CVD oxide film 13, that is, in the over-etched state.

Next, as in the second embodiment, a Ti / TiN film 19, which is an electrode material of a refractory metal, is deposited to a thickness of about 200 nm by sputtering, and then aluminum films 17 and 18 containing 1 to 3% of silicon are deposited. It is deposited to a thickness of about 700 nm by sputtering. Next, the Ti / TiN film and the aluminum film are patterned to form the electrodes of the Zener zap diode. The contact portion overetched in this way is sputtered with Ti / TiN.
When the film 19 is deposited to a thickness of about 200 nm, depending on the degree of overetching, if overetching of 100 nm or more is performed, Ti / Ti is formed on the sidewall of the contact.
A state in which the N film 19 is not deposited at all is realized. After that, the aluminum film deposited by sputtering is deposited so as to be in direct contact with the side wall of the etched semiconductor film at the contact portion unless the above-mentioned over-etching of the semiconductor film is excessive.

FIG. 4A, which is made by such a manufacturing method.
In the Zener diode structures shown in (b) and (b), the electrode material of the refractory metal is used, but the zapping of the Zener zap diode can be performed more reliably than in the second embodiment.
It was possible to realize a stable Zener zap diode which is exactly the same as that of the first embodiment.

Although the present invention has been described with reference to the three examples, the present invention is not limited to these examples.

For example, although a polysilicon film is taken as the semiconductor film, an SO film obtained by crystallizing the polysilicon film is also used.
An I film or an a-Si film formed by a plasma CVD method using silane gas or the like may be used. Further, although the cathode and anode of the Zener zap diode are taken as N ⁺ -P type, the cathode and anode may be P ⁺ -N type Zener zap diode. Therefore, in this case, the first conductivity type semiconductor is an N type semiconductor and the second conductivity type semiconductor is a P ⁺ type semiconductor. In addition, the second conductivity type (N ⁺ type) semiconductor 15 and the first zener diode shown in FIGS.
Although the diffusion of the conductive type (P ⁺ type) semiconductor 16 is described as being performed by ion implantation, a method of diffusing impurities in a diffusion furnace may be used. Further, although the Ti / TiN film is taken as the electrode material of the refractory metal, W or Mo may be used instead. In addition, the etching apparatus and process conditions can be changed as appropriate within the scope of the technical idea of the present invention.

[0033]

As is apparent from the above description, according to the present invention, the Zener zap diode using the NPN transistor of the conventional semiconductor integrated circuit has a problem by forming the Zener zap diode on the insulating film. The unnecessary capacitance existing between the source and the collector is prevented from entering, and the high frequency characteristics of the semiconductor integrated circuit can be improved. Further, the Zener zap diode of the present invention does not have the problem that the accurate trimming of the resistance cannot be performed due to the increase of the reverse current of the Zener zap diode, which is a problem due to the connection between the emitter and the collector, unlike the conventional Zener zap diode.

Further, in manufacturing a highly integrated cathode semiconductor integrated circuit, even if an electrode material made of a refractory metal is used due to the requirement of process commonality, it is possible to easily realize the zapping of the Zener zap diode at the time of trimming the resistance. Is possible.

[Brief description of drawings]

FIG. 1 is a zener zap diode according to a first embodiment of the present invention, in which (a) is a schematic sectional view and (b) is a schematic plan view.

2A to 2C are schematic cross-sectional views illustrating a zener zap diode manufacturing process of Example 1 to which the present invention is applied in the order of the processes, and FIG. 2A is a schematic cross-sectional view of the first half of the process.
(B) is a schematic sectional view of the middle stage of the process, and (c) is a schematic sectional view of the latter half of the process.

FIG. 3 is a schematic sectional view of a Zener zap diode of Example 2 to which the present invention is applied, in which (a) is a zener zap diode obtained by partially etching a semiconductor film of an electrode connecting portion by anisotropic RIE; [Fig. 4] is a schematic cross-sectional view of a Zener zap diode in which a semiconductor film of an electrode connection portion is etched to an underlying insulating film by anisotropic RIE.

FIG. 4 is a zener zap diode according to a third embodiment of the present invention, in which (a) is a zener in which a semiconductor film of an electrode connecting portion is partially etched isotropically and overetched from an insulating film opening of a contact. FIG. 3B is a schematic cross-sectional view of a zener diode, in which FIG. 6B is a schematic cross-sectional view of a zener zap diode in which a semiconductor film of an electrode connection portion is etched to the lower insulating film by isotropic RIE and is overetched from an insulating film opening of a contact. Is.

FIG. 5 is a schematic cross-sectional view of a conventional Zener zap diode in which an NPN transistor of a semiconductor integrated circuit is used and an emitter is a cathode and a base is an anode.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Zener zap diode 2 Cathode 3 Anode 11 Semiconductor substrate 12 Insulating film 13 CVD oxide film 14 First conductivity type (P type) semiconductor 15 Second conductivity type (N ⁺ type) semiconductor 16 First conductivity type (P ⁺ type) semiconductor 17 Low melting point metal cathode electrode 18 Low melting point metal anode electrode 19 High melting point metal electrode

Claims (7)

[Claims] 1. A Zener zap diode formed by a junction of a first conductivity type semiconductor and a second conductivity type semiconductor, wherein the zener zap diode is formed in a semiconductor film on an insulating film on a semiconductor substrate. Zener zap diode. 2. The zener zap diode according to claim 1, wherein the first conductivity type semiconductor is arranged so as to surround the second conductivity type semiconductor in a ring shape. 3. The zener zap diode according to claim 1, wherein the electrode wiring is formed after etching a part or all of the semiconductor film of the contact portion where the first conductivity type semiconductor and the second conductivity type semiconductor are connected to the electrode wire. A Zener zap diode characterized by being connected to a first conductivity type semiconductor and a second conductivity type semiconductor. 4. The Zener zap diode according to claim 3, wherein the electrode wiring material is formed by laminating a high melting point metal and a low melting point metal. 5. The Zener zap diode according to claim 4, wherein the connecting portion between the first conductive type semiconductor and the second conductive type semiconductor and the electrode wiring is a side surface and a lower surface, but the connecting portion on the side surface is at least a part. Zener zap diode characterized by being directly connected to a low melting point metal. 6. A method of manufacturing a Zener zap diode formed on a semiconductor film on an insulating film on a semiconductor substrate, comprising: a first step of forming an insulating film on the semiconductor substrate; and forming a semiconductor film on the insulating film. Forming the first semiconductor film
A second step of diffusing impurities to form a conductive type semiconductor, followed by etching in an island shape, and then depositing an insulating film, and opening a window for forming the second conductive type semiconductor in the insulating film Diffusion to make it a conductive semiconductor,
A contact window for connecting the conductive semiconductor and the electrode wiring is opened, and then an electrode material is deposited to form the electrode wiring.
A method of manufacturing a Zener zap diode, comprising the steps of: 7. A semiconductor film of a contact portion for connecting the first conductive type semiconductor and the second conductive type semiconductor to the electrode wiring is 1.
Part or all of them are etched, and the electrode wiring material is composed of a laminated layer of a high melting point metal and a low melting point metal. A method for manufacturing a Zener zap diode in which at least a part of the side surface is directly connected to the low melting point metal, the method includes: forming an insulating film on a semiconductor substrate; First step of forming a conductive type semiconductor and then depositing an insulating film, and etching the insulating film to form a contact window, and then overetching the semiconductor film to a size larger than the window opening using the contact window as a mask. And a third step of forming electrode wiring after depositing a high melting point metal feature and a low melting point metal, and a method of manufacturing a Zener zap diode.