JPH0832632A - Transmission system and its device - Google Patents

Abstract

PURPOSE:To provide a transmission system which can provide an interleaving system superior in correction capacity and in the embodiment hardware and to provide a device therefor. CONSTITUTION:An FEC encoding system is applied to the transmission system. At the time of sequentially arranging symbol strings after FEC encoding in the FEC encoding system in a matrix so as to constitute an interleaving block and executing interleaving, the symbol strings are sequentially and diagonally arranged in the interleaving block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission system and an apparatus thereof to which an interleave system and an error detection method used in combination with a convolutional coding or a trellis coding modulation system are applied.

[0002]

2. Description of the Related Art Generally, when transmitting digitalized video or audio information, a transmission error may occur due to the influence of noise or the like generated on a transmission line. An error correction technique is used to restore the information such as the video in which the transmission error has occurred. For example, a convolutional coded modulation method or a trellis coded-modulation (TCM) method is generally used for error correction for random noise. Both of these coded modulation systems are compared with Reed-Solomon (hereinafter simply abbreviated as RS) codes in error characteristics against bursty noise,
Somewhat inferior. As a countermeasure against this, interleaving in units of convolutional coded symbols or trellis coded symbols (hereinafter, simply referred to as coded symbol units) is used.

The structure of a transmitter / receiver using such interleaving will be described with reference to the overall block diagram shown in FIG. The most general and simple interleave method is the type shown in FIG. 14 (note that the symbol D is partially omitted in the figure to avoid complication of the figure). In the example shown in FIG. 14, the interleave depth is
ni = 3 symbols, and interleaving is realized in units of interleaving blocks of ni rows × ni columns.
The data string after interleaving is as shown in FIG. 15, and adjacent coded symbols can secure a distance equal to or more than ni symbols except for the boundary of interleaved blocks (indicated by A in the figure).

Therefore, the original coded symbols next to each other are separated from each other by more than ni symbols, and burst errors up to ni symbols on the transmission path are randomized after de-interleaving, and are subjected to Viterbi decoding or trellis. The error correction characteristic of decoding is improved.

FIG. 16 shows a circuit configuration example of interleaving or de-interleaving. The circuit shown in FIG. 16 alternately supplies a read address RA and a write address WA to the RAM 103c and outputs data after interleaving or after de-interleaving. As shown in FIG. 17, when the RAM 103c is controlled so as to be written after reading during one encoded symbol period, the memory required for de-interleaving has the configuration shown in FIG. This can be realized with a memory for at least (ni x ni -1) symbols.

FIG. 15 shows an example of RAM control timing in de-interleaving. For simplicity, the RAM addresses are associated with the rows and columns of the interleave matrix,
Row address and column address respectively. In this example, the delay amount of the de-interleave circuit is minimized, and the RAM output selection signal becomes "0" once every 9 symbols (= ni xni symbols), and the data input in FIG. It is output as output.

On the receiving side, when deinterleaving is performed, it is necessary to determine the interleave block synchronization. That is, if the head position of the interleave block does not match the head position of the address control for de-interleaving, de-interleaving cannot be performed correctly.

FIG. 19 shows an overall configuration diagram for performing this interleaved block synchronization. FIG. 19 shows the correlation between the data before FEC decoding and the data sequence after FEC decoding in the forward error correction (abbreviated as FEC) system in which error correction is performed on the receiving side using an error correction code. The error rate is estimated by taking In this case, when the error rate exceeds a value estimated in advance, it is determined that the synchronization is lost. This loss of synchronization is C / N
When the (carrier-to-noise ratio) is sufficient, it occurs when interleave block synchronization is not established. When the synchronization is lost, the timing of address generation is shifted by one symbol and the error rate is detected again to make a determination. In this way, the establishment of synchronization is repeated until the error rate becomes smaller than the value specified in advance (so-called symbol shift method).

The detection of the error rate is realized by the structure shown in FIG. 20, for example. The configuration shown in FIG. 20 is
In the example of convolutional coding / Viterbi decoding (coding rate 1 /
2), the modulation is BPSK, and Viterbi decoding is performed on the two symbols of the soft decision demodulation data. The upper 1 bit of this soft decision demodulation data is hard decision data. Simple decoding is performed from the hard decision data of 2 bits (for example, Japanese Patent Laid-Open No.
No. 244019), a delay is added to match the time required for Viterbi decoding. Next, the data string after Viterbi decoding is compared. At this time, when the C / N is high to some extent, the error rate of the data string after Viterbi decoding is sufficiently smaller than the error rate of the data string after simple decoding. become. Since the error rate of the data sequence after simple decoding and the error rate after Viterbi decoding have a correlation, the error rate of the data sequence after Viterbi decoding can be estimated.

[0010]

However, as shown in FIG.
In the interleaving method shown in FIG. 3, adjacent symbols continue in the data string after interleaving at the boundary of the interleaving block (A in FIG. 15), and the burst error cannot be randomized.

In contrast to the interleaving method of FIG. 14, when the interleave block synchronization is established by the symbol shift method, the worst is eight (= ni × ni −1).
(2 times) shift operation and error rate detection are required, and the processing takes time. For example, when ni = 10, the worst 99 shift operations are required. Further, in order to detect the error rate, a simple decoder 470 as shown in FIG. 20 is required.

Furthermore, when convolutional coding or trellis coding is used as an inner code and an outer code is combined with an RS code or the like, for example, when the number of bits constituting one coded symbol of the outer code is 1 byte, byte synchronization is performed. Since it is necessary to output in units of 1 byte, a means for achieving byte synchronization was needed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a transmission system and an apparatus therefor capable of providing an interleave system excellent in correction capability and hardware implementation.

[0014]

In order to achieve the above object, the first invention of the present application is a transmission system to which the FEC coding system is applied, in which a symbol sequence after FEC coding in the FEC coding system is used. The gist is that when the interleave blocks are sequentially arranged in a matrix form and interleaving is performed, the symbol columns are sequentially arranged obliquely with respect to the interleave blocks.

That is, the required interleaving depth is n
For i symbols, the input data symbol string is (ni +
1) This is a method in which an interleave block is divided by symbols and diagonal interleaving shown in FIG. 1 is performed to realize interleaving of a distance ni over all data after interleaving.

Specifically, it is a transmission method to which an FEC coding method based on convolutional coding or trellis coding modulation method is applied, and the symbol string after the FEC coding (hereinafter referred to as FEC coded symbol string). ) To (ni +1)
An interleave block is formed by dividing each symbol, diagonally arranged about the interleave block, an interleave matrix is formed, interleaving is performed, and an interleave symbol string having an interleave depth of ni symbols is transmitted, On the receiving side, the data sequence corresponding to the interleaved symbol sequence may be subjected to FEC decoding (Viterbi decoding or trellis decoding) by performing an operation (de-interleaving) opposite to that on the transmitting side.

The second invention of the present application is a transmission system to which the FEC coding system is applied, wherein nout to m0 are added to an input symbol sequence input in nout bit units on the transmission side.
To the symbol sequence obtained by this FEC encoding.
s Interleaved blocks are divided for each symbol, interleaved and interleaved symbol sequences are transmitted, and the receiving side deinterleaves and FEs the data sequence corresponding to the received interleaved symbol sequence.
FE including C0 decoding and including m0 bits per symbol
After the symbol sequence after C decoding is obtained, when the speed conversion from m0 to nout is performed and output in nout bit units, the product of ns, m0 and nout is the product of nos and m0.
The point is to set it so that it is divisible by.

That is, when the output of the FEC decoder on the receiving side is subjected to speed conversion and output in units of nout bits,
When the decoding unit of the data string after FEC decoding is m0 bits, the interleave block length is (in bit number expression) a common multiple of m0 and nout. This means that when the interleave block length is ns symbols, ns * m0 is chosen to be divisible by nout.

Specifically, it is a transmission method to which the FEC coding method based on the convolutional coding or the trellis coding modulation method is applied, and the input symbol sequence input in the unit of nout bits is subjected to the nout → m0 speed conversion. Then, FEC coding is performed for each m0 bit, an interleave block is configured by dividing each of the FEC coded symbol strings n s symbols, an interleave matrix is configured by using this interleave block as a unit, and interleaving is performed. Sending an interleaved symbol sequence, the receiving side performs an operation reverse to the transmitting side, that is, de-interleaves, on the data sequence corresponding to the interleaved symbol sequence,
F that has undergone FEC decoding and contains m0 bits per symbol
Symbol string after EC decoding (hereinafter FEC decoded symbol string)
Then, when performing m0 → nout speed conversion and outputting in nout bit units, it is preferable that n s × m0 be divisible by nout.

Further, in the third invention of the present application, when the interleave block according to claim 2 is constructed and interleaving is performed, symbol strings are sequentially arranged obliquely with respect to the interleave block. Use as a summary.

Further, a fourth invention of the present application is a coding device to which the FEC coding system is applied, and FEC coding means for coding by the convolutional coding modulation system or the trellis coding modulation system, The gist of the present invention is to have interleaving means for interleaving a symbol sequence obtained by encoding by the FEC encoding means, sequentially arranged obliquely to form an interleave block.

Preferably, an FEC encoder according to a convolutional coded modulation system or a trellis coded modulation system,
An interleave matrix is formed by dividing each of the FEC encoded symbol strings (ni + 1) symbols, diagonal arrangement is performed on the interleave blocks, an interleave matrix is formed, and interleave is performed,
It is preferable to have an interleaving means for transmitting an interleaved symbol sequence having an interleave depth of ni symbols.

The fifth invention of the present application is a coding apparatus to which the FEC coding method is applied, wherein the speed conversion of an input symbol sequence input in units of nout bits is converted from nout to m.
A speed conversion unit for performing 0 to 0, and an F which performs FEC encoding for each m0 bit of the symbol string output from this speed conversion unit.
The EC coding means and the FEC coded symbol string output from the FEC coding means are divided into n s symbols to form an interleave block.
Interleaving means for constructing an interleaving matrix in units of blocks, for performing interleaving and transmitting an interleaved symbol sequence, wherein n s and m 0
And nout are set such that the product of ns and m0 is divisible by nout, respectively.

Desirably, the input symbol sequence is changed from nout to m
0 Speed conversion circuit for speed conversion and FE for each m0 bit
An FEC encoder that performs C coding, and an interleave block that is divided for each n s symbol of the FEC encoded symbol sequence is configured, and an interleave matrix is configured using this interleave block as a unit, and interleaving is performed to perform interleaving. When composed of an interleave circuit for transmitting a symbol string, it is advisable that ns × m0 be divisible by nout for each of the above codes.

Further, in the sixth invention of the present application, when the interleaving means according to the fifth aspect constitutes an interleave block and performs interleaving, symbol sequences are sequentially arranged obliquely with respect to the interleave block. The main point is to go.

Further, the seventh invention of the present application is an interleaved interleave in which FEC encoded symbol sequences obtained by FEC encoding in the FEC encoding system are sequentially arranged obliquely to form an interleaved block. Decoding device for receiving and decoding a symbol string, de-interleaving means for de-interleaving a data string corresponding to the interleaved symbol string, and an FEC coding method for the output of the de-interleaving means And an output of the de-interleaver and an output of the FEC decoder are input to detect an error rate of the FEC decoding, and a synchronization flag is output corresponding to the detected error rate. Error rate detecting means for
The gist of the interleaving means is to establish the synchronization of the interleaved blocks by shifting the deinterleaving timing when the synchronization flag output from the error rate detecting means indicates an asynchronous state.

Desirably, regarding the FEC coding method by the convolutional coding or trellis coding modulation method,
The FEC-encoded symbol sequence (hereinafter referred to as FEC-encoded symbol sequence) is divided into (ni + 1) symbols to form an interleave block, and the interleave block
In a decoding device that performs diagonal arrangement of blocks to form an interleave matrix, performs interleaving, and receives and decodes an interleave symbol string with an interleave depth of ni symbols, the receiving side supports the interleave symbol string. De-interleaving means for performing de-interleaving on the data sequence to be performed and reverse operation to the transmitting side, an FEC decoder, and an error rate detecting means for detecting and estimating an error rate of FEC decoding. The means has a function of determining whether the error rate exceeds or does not exceed a predetermined value specified in advance, and outputs a synchronization flag indicating this, and the de-interleave circuit outputs when the synchronization flag indicates an asynchronous state. , Interleaving by shifting the deinterleaving timing (so-called symbol shift method) Tsu may be the way to establish the synchronization of the click.

Further, the eighth invention of the present application is obtained by performing FEC coding for every m0 bits by performing speed conversion from nout to m0 to an input symbol string input in nout bit unit, and obtaining by this FEC coding. A decoding device for receiving and decoding an interleaved interleaved symbol sequence, which is formed by dividing an interleaved symbol sequence for each n s symbol into an interleaved block, and deinterleaves a data sequence corresponding to the interleaved symbol sequence. De-interleaving means to be applied, and F-output including F0 decoding for the output of the de-interleaving means to include m0 bits per symbol.
FEC decoding means for obtaining an EC decoding symbol string and this FE
The speed conversion means for performing speed conversion from m0 to nout on the output of the C decoding means and outputting it in units of nout bits, and the output of the de-interleaving means and the output of the FEC decoding means are input to determine the error rate of FEC decoding. Error rate detecting means for detecting and outputting a synchronization flag corresponding to the detected error rate, wherein the de-interleave means indicates that the synchronization flag output from the error rate detecting means is in an asynchronous state. Occasionally, the deinterleaving timing is shifted to establish the synchronization of the interleaved block, and the speed conversion means performs the speed conversion at the timing of the interleaved block period based on the establishment of synchronization, and the n
s, m0 and nout are the product of ns and m0, respectively, and nou
The point is that it is set to be divisible by t.

Further, in a ninth aspect of the present invention, the deinterleaving means according to the eighth aspect arranges the symbol sequence obtained by encoding by the FEC encoding means, sequentially and obliquely to arrange the interleaving block. And deinterleaving the data sequence corresponding to the interleaved symbol sequence that has been configured and is interleaved.

The tenth invention of the present application is the above-mentioned claim 7.
Or a convolutional coding circuit for outputting all or some of the coded bits obtained by convolutionally coding the Viterbi-decoded bits obtained by Viterbi-decoding the FEC decoded symbol. A hard decision circuit that makes a hard decision on the FEC decoded symbol and outputs a hard decision coded bit, a delay circuit that delays the hard decision coded bit by the time required for the Viterbi decoding, and a delay circuit that outputs the hard decision coded bit. Counting the number of mismatches between the hard-decision coded bits and the coded bits output from the convolutional coding circuit,
The gist of the present invention is to have a comparison and determination unit that estimates and outputs an error rate from the mismatch frequency.

That is, the tenth invention of the present application delays all or some of the bits corresponding to the convolutionally coded bits of the hard decision result by the time required for the Viterbi decoding, and the result of the Viterbi decoding. To be the encoded bit reproduced and decoded by performing the same convolutional coding on the transmitting side again, and the error frequency of FEC decoding can be estimated by obtaining the mismatch frequency by all or part of it and the comparison determination means. Characterize.

Preferably, the error rate detection means for detecting and estimating the error rate of the FEC decoder convolutionally encodes the Viterbi-decoded bits in the FEC-decoded symbols, or all of the coded bits decoded and reproduced, or A convolutional coding circuit that outputs a part thereof, a hard decision circuit that makes a hard decision on the symbol of the FEC decoded input, and outputs a hard decision coded bit corresponding to the decoded and reproduced coded bit, and the hard decision A delay circuit that delays the coded bits by the time required for Viterbi decoding, a count of the number of mismatches between the delay circuit and the decoded and reproduced coded bits, and the frequency of mismatches is estimated to output the error rate. It is preferable that it is configured by a comparison and determination means that

The eleventh invention of the present application is the above-mentioned claim 1.
The comparison determination means described in 0 determines whether or not the mismatch frequency or the estimated error rate exceeds the threshold value by using a predetermined value as a threshold value, and outputs a synchronization flag indicating a synchronization state. And

The twelfth invention of the present application is the above-mentioned claim 1.
The gist of the comparison / determination means described in 1 is to prepare two different types of threshold values as predesignated values and to switch these threshold values as appropriate depending on the asynchronous state and the synchronous state.

The thirteenth invention of the present application is the above-mentioned claim 7.
Alternatively, the FEC decoding means described in 8 or 9 or 10 or 11 or 12 is for concatenated coding in which a convolutional coding modulation method or a trellis coding modulation method as an inner code and a block code as an outer code are combined. The essence is that erasure correction is performed at the time of outer FEC decoding by using the synchronization flag output from the error rate detection means as the erasure flag of the outer block code.

Desirably, FEC for concatenated coding in which a convolutional coding modulation method or a trellis coding modulation method is used as an inner code and a block code is combined with an outer code.
The decoder is composed of an inner FEC decoder, an error rate detecting means for detecting and estimating the error rate thereof, and an outer FEC decoder, and the synchronization flag of the output of the error rate detecting means is the erasure flag of the outer block code. Therefore, it is preferable that the outer FEC decoder performs erasure correction.

[0037]

The transmission method of the first invention of the present application, the encoding device of the fourth invention of the present application, and the decoding device of the seventh invention of the present application are FEC.
When the FEC-encoded symbol sequence in the encoding method is sequentially arranged in a matrix to form an interleave block and interleaving is performed, the symbol sequence is sequentially arranged obliquely with respect to the interleave block. By going to the interleave depth ni,
The interleaving distance can always be secured, and at the receiving side, since the interleaving block is (ni +1), the interleaving block synchronization can be established at the worst by ni shifting operations and error detection. A speed of 1 / ni can be realized.

In the transmission system of the second invention of the present application, the encoding device of the fifth invention of the present application, and the decoding device of the eighth invention of the present application, on the transmission side, from nout to m0 in the input symbol sequence input in nout bit units. After performing the speed conversion to m0 bits and performing FEC coding for each m0 bit, the symbol sequence obtained by this FEC coding is divided into every n s symbols to form an interleave block, and interleaving is performed to perform an interleave symbol sequence. Is sent. On the receiving side, the data sequence corresponding to the received interleaved symbol sequence is subjected to de-interleaving and FEC decoding to obtain a symbol sequence after FEC decoding including m0 bits per symbol. Further, after that, speed conversion from m0 to nout is performed, and the data is output in nout bit units. At this time, ns
By setting so that the product of ns and m0 is divisible by nout, the number of bits of the data string after FEC decoding included in the interleave block synchronization is divisible by nout. , The speed conversion timing can be used for the speed conversion of the interleaved block synchronization timing.

In the transmission system of the third invention of the present application, the encoding device of the sixth invention of the present application, and the decoding device of the ninth invention of the present application, when an interleave block is formed and interleaving is performed, the symbol sequence is sequentially applied. Since the interleave blocks are arranged diagonally, the interleave distance and the speed of synchronization establishment can be secured, and the speed conversion timing is used for the speed conversion of the interleave block synchronization timing. It becomes possible.

In the decoding device of the invention of the seventh, eighth, ninth or tenth aspect of the present invention, the error rate can be detected and estimated without complicated simple decoding.

The decoding device of the eleventh invention of the present application determines whether or not the mismatch frequency or the estimated error rate exceeds the threshold value by preparing a value designated in advance in the comparison / determination means as the threshold value. Thus, for example, when this threshold value is exceeded, the synchronization flag can be lowered to indicate an asynchronous state.

In the decoding device of the twelfth invention of the present application, two different kinds of threshold values are prepared for the comparison / determination means, and these threshold values are appropriately switched depending on the asynchronous state and the synchronous state, whereby the hysteresis characteristic can be provided and the synchronous characteristic can be obtained. It becomes possible to stabilize the generation of the flag.

In the decoding device of the thirteenth invention of the present application, the FEC decoding means performs the erasure correction during the outer FEC decoding by using the synchronization flag output from the error rate detection means as the erasure flag of the outer block code. By this erasure correction, the outer FEC
The decoding ability can be further enhanced.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIG. FIG. 1 is a diagram showing a configuration example of an interleave block according to the present invention, in which the interleave depth is ni.
It shows an oblique interleaving method when = 3. At this time, if the memory capacity is at least 9 symbols (= ni xni symbols) as shown in FIG. 2, de-interleaving can be realized. The data sequence after interleaving at this time is shown in FIG.

As is apparent from FIG. 3, in this embodiment, ni (= 3) symbols or more are used at all positions including the boundary of interleaved blocks (block size: 4 symbols = (ni +1) symbols). The distance is secured. Further, referring to an example of the read address and the write address shown in FIG. 3, in order for de-interleaving to be performed correctly, the first row in the interleave matrix shown in FIG. It suffices that it is sufficient, and it may be off in the column direction. For example,
As shown in FIG. 4, as compared with the case shown in FIG. 1, even if it is shifted by one column, the column address of the memory address for the data is shifted by one column, and as shown in FIG. There is no effect on the subsequent data sequence. Therefore, the uncertainty regarding the interleaved block synchronization is 4 (= ni +1) only in the row direction, and the worst case is 3 (= ni) when the interleaved block synchronization is established by the symbol shift method in the configuration of FIG. Synchronization is established by one shift operation. In addition to the configuration shown in FIG. 20, there is also a method for estimating the error rate from the maximum likelihood path metric of Viterbi decoding.

Next, the second embodiment will be described. FIG. 6 shows an example of the configuration around the inner FEC encoder when the trellis coded modulation method is applied as the inner code and the RS coded modulation method is applied as the outer code.

The configuration will be briefly described below. The speed converter 11 performs speed conversion from 8 bits to 3 bits,
8-bit Reed-Solomon encoded data is input.
The trellis-encoded input information symbol output from the speed converter 11 is input to the trellis encoder 13. The trellis encoder 13 is a convolutional encoder 131.
And a signal arrangement distributor 133. The trellis-coded modulation symbols Ii and Qi output from the trellis encoder 13 are input to the interleaving means 15, interleaved, and then output as modulation symbols I and Q to the 16QAM modulator. Further, the speed converter 11 and the interleaving means 15 are provided in the timing generator 1
It is connected to 7 and synchronized.

With the inner FEC encoder having such a structure,
The number of bits per coded symbol of the RS code that is most often used is 8 bits. On the other hand, the trellis coded modulation method in this embodiment uses 16QAM, and one trellis coded symbol, that is, 4 bits per trellis coded modulation symbol, has information bits at the trellis coded input included. Is 3 bits. Therefore, speed conversion from 8bit to 3bit is required.

If the interleaved block is made up of 8 trellis coded modulation symbols, then one interleaved block will contain 3 × 8 = 24 bits of information bits at the trellis coded input. This corresponds to three RS-coded symbols. Therefore, for example, the timing generation circuit 17 operates so that each RS coded 3 symbol of the input fits exactly in each interleave block.

FIG. 7 shows an example of the configuration around the inner FEC decoder corresponding to FIG. The configuration will be briefly described below. The de-interleaving means 21 performs de-interleaving, and the modulation symbols I and Q are input from the 16QAM modulator. The trellis coded modulation symbols Ii and Qi output from the de-interleaving means 21 are input to the trellis decoder 23 and error rate detecting means 27. The trellis decoded symbol output from the trellis decoder 23 is input to the rate converter 25, and the Viterbi decoded bit of the trellis decoded symbol is input to the error rate detection means 27. The synchronization flag output from the error rate detection means 27 is input to the timing generator 29,
The de-interleaving means 21 and the speed converter 25 are synchronized. Further, the speed converter 25 performs speed conversion of 3 bits → 8 bits and outputs Reed Solomon decoded data of 8 bits.

In the inner FEC decoder having such a configuration, of the 3 bits of the trellis decoded symbol output from the trellis decoder 23, the internally decoded bit of Viterbi decoding is 1 bit. This and trellis decoder 23
The error rate detecting means 27 estimates the error rate from the Ii data and the Qi data input to, and when it exceeds a preset value, the synchronous flag output to the timing generating circuit 29 is lowered to indicate an asynchronous state. The timing generation circuit 29
By inputting this synchronization flag, the de-interleaving means 21
The timing of is shifted by one symbol. This is also repeated until the error rate becomes smaller than the value specified in advance.

The timing control (address control) in the de-interleaving means 21 includes an interleave block period (eight demodulation symbols). At this time, the trellis-decoded symbols included in the interleaved block synchronization are 8 symbols in the same way, and therefore, 24 bits are included. When outputting the RS decoded input data in 1-byte units, 8 bits from the beginning of this 14-bit by the above agreement
It is possible to detect and determine the boundary of the byte without particularly providing the byte synchronization means by taking out each one (by the 3-8 speed converter 25). Byte boundaries are
It does not necessarily have to coincide with the boundary of the interleaved block, and may be shifted by 1 bit, for example. It suffices if the agreement is established between the transmitting side and the receiving side.

The inner FEC decoded symbol unit is 2bi.
For t, the interleaved block length can be a multiple of 4 symbols. At this time, for example, interleave
When the block length is 4 symbols, FEC decoding 4 symbols = 8bi during one interleave block synchronization.
It includes t and can be used as the RS decoded input data as it is. Generally, when the inner FEC decoding unit is m0 bits, the interleave block length is n with respect to n s.
It suffices if s × m0 is divisible by the outer FEC decoding unit.

When the diagonal interleaving of FIG. 1 is used, this condition, that is, "when the inner FEC decoding unit is m0 bits, if the interleaving block length is n s × m0 is divisible by the outer FEC decoding unit, For an interleave block length n s that satisfies "good", the interleave depth is (ns -1), so for the required interleave depth ni, ni ≤ (ns -1) is selected.

Even with interleaving of the type shown in FIG.
Byte synchronization can be established, and the interleave depth is √ (ns) for the interleave block length ns.
Ni ≤ √ (ns) for the required interleaving depth ni
To be However, when √ (ns) is not an integer, the interleave block does not have to be a square, but both the number of columns and the number of rows must be ni or more.

FIG. 8 shows that when the inner FEC decoding unit is not a divisor of 8 (rate conversion output unit), the required interleaving depth ni = 5, and ns = 56 is the minimum value of interleaving block length. Is.

FIG. 9 shows an example in which the interleave method described in US Pat. No. 4,559,625 is modified and applied to the present invention. A sub-block of (ni +1) symbols is formed in the column direction for a required ni, and diagonal interleaving of ni rows is performed to form an interleave block. This method has the effect of minimizing the memory. It can be used for byte synchronization with ns = 56 (because it is a coefficient of 8).

Comparing FIG. 8 and FIG. 10, the interleaving block length ns = 56 for the same interleaving depth ni = 7. Obviously, diagonal interleaving is more advantageous in terms of fast interleave block synchronization establishment.

Next, a third embodiment will be described. The third embodiment realizes error rate detection (estimation) without using the simple decoder 470 shown in FIG. First, with reference to FIG. 11, the configuration of the error rate detecting means according to the present invention corresponding to FIG. 20 will be described. The soft-decision demodulation data D ₁ and D ₂ are input to the Viterbi decoder 274, and the upper 1 bit (hard decision result) of the soft-decision demodulation data D ₁ and D ₂ is input to the delay circuit 271 or the delay circuit 275. . Further, Viterbi decoded data is obtained as an output from the Viterbi decoder 274, and this Viterbi decoded data is also output to the convolutional encoder 273. The outputs of the convolutional encoder 273 and the delay circuit 271 or the delay circuit 275 are compared and determined by the comparison / determination means 272, respectively.
It is supplied to 276 for comparison and determination, and the determination result is output as a synchronization flag and an error rate output.

When the modulation in the error rate detecting means shown in FIG. 11 is BPSK, the Viterbi decoder 27 using the soft decision demodulation data D ₁ and D ₂ for two symbols of the demodulation symbol.
In step 4, Viterbi decoding is performed. The obtained Viterbi-decoded data is supplied to the convolutional encoder 273, and the convolutional encoding is performed again to reproduce the decoded convolutional encoded bits.

On the other hand, since the upper 1 bit of the soft decision demodulation data D ₁ or D ₂ is a hard decision result, it is delayed by the delay circuit 271 or the delay circuit 275 by the time required for the Viterbi decoding in the Viterbi decoder 274. Then, the number of mismatch bits is counted by comparing this with the corresponding convolutionally coded bits calculated previously, the frequency of occurrence of the mismatch bits can be calculated, and the error rate can be estimated. Further, when the C / N is sufficient, the error rate of the Viterbi decoded bits is sufficiently smaller than the error rate of the hard decision bits and can be ignored. Therefore, the frequency of occurrence of the unmatched bits matches the error rate of the hard-decision bits, and the error rate of the Viterbi decoded data can be estimated from this.

FIG. 12 shows an error rate detecting means for the trellis coded modulation method. First, the configuration will be described with reference to FIG. The 5-bit soft-decision demodulated data I and Q are input to the trellis decoder 23 and the error rate detection means 27, respectively. The trellis decoder 23 includes an uncoded bit decoder 231, a Viterbi decoder 232, and a convolutional encoder 2.
33, the error rate detection means 27 is a hard decision circuit 27.
7, a delay circuit 278, and a comparison / determination unit 279.

The convolutional encoder 233 inside the trellis decoder 23 is for decoding uncoded bits, and this output (reproduced convolutional coded bits) is used for error rate detection. Available.

Since the soft-decision demodulated data I and Q input to the trellis decoder 23 are arrangement data directly corresponding to the mapping of the I / Q axis, the hard-decision of the convolutionally encoded bits is hard. A judgment circuit is required. This is RO
It can be realized by a decoder using M.

In addition, in the first and second embodiments, it is possible to indicate the asynchronous state by lowering the sync flag when the mismatch frequency exceeds a preset value. This can be used to establish the interleaved block synchronization of FIG.

In addition, two kinds of designated values are prepared in advance, and when a random asynchronous state is set, a lower value is set so as to have a hysteresis characteristic so that the synchronization flag is generated. Stabilization can be realized.

All the convolutionally coded bits used for the comparison judgment may be used, but a part of the bits is used as shown in the delay circuit 271 of FIG. 11, the comparison judgment means 272, and FIG. The delay circuit is smaller in size.

In each of the above embodiments, the case where the convolutional coding rate is r = 1/2 is shown, but the present invention can be applied even when the coding rate is r = 2/3. Is clear. Furthermore, when the synchronization flag indicates the asynchronous state, the trellis decoded symbol has low reliability, and therefore it can be used as the erasure flag of the outer code. Byte synchronization may also be necessary when connecting data after FEC decoding to ATM.

As described above, according to the above embodiments,
The diagonal interleaving allows the interleaving distance to be increased even at the boundary between the interleaving blocks, and the speed of synchronization establishment can be increased. Further, the timing of the interleave block can be utilized for speed conversion after the FEC decoding output, and can also be used for the output synchronization. Furthermore, the detection and estimation of the error rate is realized without a simple decoding circuit.

[0070]

As described above, the present invention can provide an excellent interleaving method with respect to correction capability and hardware implementation.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of an interleave block according to the present invention.

FIG. 2 is a diagram showing an example of addresses of an interleave block shown in FIG.

FIG. 3 is a timing chart showing deinterleaving timing of the interleave block shown in FIG.

FIG. 4 is a diagram showing a case where a relationship between a memory and data of an interleave block is shifted by one column according to the present invention.

5 is a timing chart showing de-interleaving address generation timing of the interleaving block shown in FIG.

FIG. 6 is a block diagram showing a configuration of an embodiment including an inner FEC encoder according to the present invention.

FIG. 7 is a block diagram showing a configuration of an embodiment including an inner FEC encoder according to the present invention.

FIG. 8 is a diagram showing a configuration example of an embodiment of an interleave block that can be used for byte synchronization according to the present invention.

FIG. 9 is a diagram showing a configuration example of an embodiment of an interleave block usable for byte synchronization according to the present invention.

FIG. 10 is a diagram showing a configuration example of an embodiment of an interleave block that can be used for byte synchronization according to the present invention.

FIG. 11 is a block diagram showing an example of a configuration of an error rate detecting means according to the present invention.

FIG. 12 is a block diagram showing an example of a configuration of an error rate detecting means according to the present invention.

FIG. 13 is a block diagram showing a schematic configuration of a transmission device and a reception device when interleaving is used.

FIG. 14 is a diagram showing a configuration example of a conventional interleave block and a transmission order thereof.

15 is a timing chart showing the timing of de-interleaving relating to the interleaving block shown in FIG.

FIG. 16 is a block diagram showing an example of the configuration of a conventional interleave / de-interleave circuit.

17 is a timing chart showing the timing in the interleave / de-interleave circuit shown in FIG.

FIG. 18 is a diagram showing an example of a memory configuration and addresses of the interleave block shown in FIG.

FIG. 19 is a block diagram showing an example of configurations of a conventional de-interleave circuit and an error rate detection circuit.

FIG. 20 is a block diagram showing an example of a configuration of a conventional error rate detection means.

[Explanation of symbols]

11 ... Velocity converter, 13 ... Trellis encoder, 15 ... Interleaving means, 17 ... Timing generator, 21 ... De
Interleaving means, 23 ... Trellis decoder, 25 ... Velocity converter, 27 ... Error rate detecting means, 29 ... Timing generator, 131 ... Convolutional encoder, 133 ... Signal arrangement distributor, 231 ... Uncoded bit decoding , 232 ... Viterbi decoder, 233 ... Convolutional encoder, 271 ... Delay circuit, 272 ... Comparison decision means, 273 ... Convolutional encoder, 274 ... Viterbi decoder, 275 ... Delay circuit, 276
... Comparison determining means, 277 ... Hard decision circuit, 278 ... Delay circuit, 279 ... Comparison determining means.

Claims (13)

[Claims] 1. A transmission method to which an FEC encoding method is applied, wherein symbol columns after FEC encoding in the FEC encoding method are sequentially arranged in a matrix to form an interleave block and interleaving is performed. In this case, the symbol sequence is sequentially arranged obliquely with respect to the interleave block. 2. A transmission method to which the FEC coding method is applied, wherein the transmission side performs a speed conversion from nout to m0 to an input symbol string input in nout bit units, and an FEC code for every m0 bit. The symbol sequence obtained by this FEC encoding is divided into n s symbols to form an interleave block, interleaved and interleaved symbol sequences are transmitted, and the interleaved symbol sequence received at the receiving side. After de-interleaving and FEC decoding the data sequence corresponding to, to obtain the FEC-decoded symbol sequence containing m0 bits per symbol, perform speed conversion from m0 to nout and output in nout bit units. Then, the product of ns and m0 is nou, and the product of ns and m0 is nou.
A transmission method characterized by setting to be divisible by t. 3. The transmission method according to claim 2, wherein when the interleave block is formed and interleaved, symbol strings are sequentially arranged obliquely with respect to the interleave block. 4. A coding device to which the FEC coding method is applied, wherein the FEC coding means performs coding by a convolutional coding modulation method or a trellis coding modulation method, and a code by the FEC coding means. An encoding device, comprising: interleaving means for sequentially interlacing and arranging the symbol sequences obtained by the conversion to form an interleave block. 5. An encoding device to which the FEC encoding method is applied, comprising: speed conversion means for performing speed conversion of an input symbol sequence input in nout bit units from nout to m0; and output from this speed conversion means. FEC encoding means for performing FEC encoding for each m0 bit of the symbol sequence to be generated, and the FEC encoded symbol sequence output from this FEC encoding means is divided into n s symbols to form an interleave block. · Having an interleaving means for constructing an interleave matrix in units of blocks and performing interleaving and transmitting an interleave symbol sequence, so that the product of ns, m0 and nout is divisible by nout, respectively. An encoding device characterized by being set to. 6. The interleaving means, when constructing an interleave block and performing interleaving, arranges the symbol sequence sequentially and obliquely with respect to the interleave block. Encoding device. 7. An FEC-encoded symbol sequence obtained by FEC encoding in the FEC encoding method is sequentially arranged obliquely to form an interleaved block, and an interleaved symbol sequence subjected to interleaving is received and decoded. De-interleaving means for de-interleaving a data sequence corresponding to the interleaved symbol sequence, and FEC decoding means for subjecting the output of the de-interleaving means to decoding in the FEC encoding method. And an error rate detecting means for inputting the output of the de-interleaving means and the output of the FEC decoding means to detect an error rate of FEC decoding and outputting a synchronization flag corresponding to the detected error rate. The de-interleaving means has a de-interleaving means when the synchronization flag output from the error rate detecting means indicates an asynchronous state. A decoding apparatus characterized by establishing interleave block synchronization by shifting interleave timing. 8. An input symbol sequence input in nout bit units is subjected to speed conversion from nout to m0, FEC coding is performed for each m0 bit, and the symbol sequence obtained by this FEC coding is performed for each ns symbol. A decoding device that receives and decodes an interleaved symbol sequence that is formed by dividing an interleaved block into interleaved blocks, and de-interleaving means that de-interleaves a data sequence corresponding to the interleaved symbol sequence, FEC decoding means for performing FEC decoding on the output of this de-interleaving means to obtain an FEC decoded symbol string containing m0 bits per symbol, and speed conversion from m0 to nout for the output of this FEC decoding means, and nout bits Speed conversion means for outputting in units, output of the de-interleave means and output of the FEC decoding means To detect the error rate of the FEC decoding, and to output a synchronization flag corresponding to the detected error rate, and the deinterleaving means from the error rate detecting means. When the output sync flag indicates an asynchronous state, the deinterleave timing is shifted to establish synchronization of the interleave block, and
The speed conversion means performs speed conversion at the timing of the interleave block cycle based on the establishment of synchronization, and the n s, m 0 and no t are set so that the product of n s and m 0 is divisible by no t. Decryption device. 9. The interleaved symbol sequence in which the deinterleaving means forms an interleaved block by sequentially arranging the symbol sequences obtained by encoding by the FEC encoding means in a slanted manner to form an interleaved symbol sequence. 9. The decoding device according to claim 8, wherein the data string corresponding to the data is de-interleaved. 10. The convolutional coding for outputting all or part of the coded bits obtained by convolutionally coding the Viterbi-decoded bits obtained by Viterbi-decoding the FEC-decoded symbols, by the error rate detection means. A circuit, a hard decision circuit that makes a hard decision on the FEC decoded symbol and outputs a hard decision coded bit, a delay circuit that delays the hard decision coded bit by the time required for the Viterbi decoding, and a delay circuit And a comparison / determination unit that counts the number of mismatches between the hard-decision coded bits that are output and the coded bits that are output from the convolutional coding circuit, estimates the error rate from the mismatch frequency, and outputs the error rate. 9. The decoding device according to claim 7, which is characterized in that. 11. The comparison / determination means determines whether the mismatch frequency or the estimated error rate exceeds the threshold value by using a value designated in advance as a threshold value, and outputs a synchronization flag indicating a synchronization state. The decoding device according to claim 10, wherein 12. The decoding device according to claim 11, wherein the comparison / determination means prepares two different types of threshold values as the pre-designated values, and appropriately switches these threshold values depending on an asynchronous state and a synchronous state. . 13. The FEC decoding means is for concatenated coding in which a convolutional coding modulation method or a trellis coding modulation method as an inner code and a block code as an outer code are combined, and the error is 13. The decoding apparatus according to claim 7, wherein the synchronization flag output from the rate detecting means is used as an erasure flag of the outer block code to perform erasure correction during outer FEC decoding.