CN100346590C - Error-code pattern generating circuit and decoding circuit using the same - Google Patents
Error-code pattern generating circuit and decoding circuit using the same Download PDFInfo
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- CN100346590C CN100346590C CNB021086338A CN02108633A CN100346590C CN 100346590 C CN100346590 C CN 100346590C CN B021086338 A CNB021086338 A CN B021086338A CN 02108633 A CN02108633 A CN 02108633A CN 100346590 C CN100346590 C CN 100346590C
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Abstract
The present invention discloses an error code pattern generating circuit and a decoding circuit using the circuit, which belongs to the field of digital communication, wherein the present invention can reduce the design area of an FEC correction encoding chip. An error code pattern (error_ptn) is calculated and generated according to the input pattern (error_add) of an error code position; the error code pattern (error_ptn) comprises an error value calculating module (55), a change-over switch (501) and a storage and output circuit, wherein the storage and output circuit comprises an upper symmetrical circuit, a lower symmetrical circuit and a switch (52); each of the symmetrical circuit comprises a memory group (54). The pattern (error_add) of the error code position is directly and orderly input to the error value calculating module (55) to be calculated; the calculated and output value is written in the memory group (54) in sequence by the change-over switch (501); data in the memory group (54) is output in sequence by the switch (52) to form the error code pattern (error_ptn).
Description
Technical field:
The present invention relates to the digital communication field, relate in particular to the design of integrated circuit of FEC (forward error correction) technology, specifically, relate to a kind of error-code pattern generative circuit of the FEC of reducing error correction coding chip design area and use the decoding circuit of this circuit.
Background technology:
The fast development of digital communication technology makes the world today enter the information age, and people are more and more higher to the requirement of communication apparatus, and application-specific integrated circuit (ASIC) can reduce equipment price, reduces volume, and weight reduction improves equipment dependability.
RS (255,239) is a specified standard FEC error correction coding mode G.975.Fig. 1 is RS (255, a 239) error correction coding chip design block diagram.As shown in the figure, the error correction coding chip comprise coding module 1, syndrome computing module 2, interative computation module 3, ask error code position module 4, error-code pattern generation module 5, FIFO (first-in first-out) buffer 6 and arithmetic unit 7; Input coding module 1 to be encoded, the output encoder module 1 of having encoded; Input fifo buffer 6 to be decoded, import syndrome computing module 2 simultaneously, the error_add (error code position pattern) of the character position of error code takes place in the output expression fec frame through syndrome computing module 2, interative computation module 3, after asking error code position module 4 sequential processes; Syndrome computing module 2, interative computation module 3, ask the error code position module 4 order common upstream circuitry that constitutes error-code pattern generation module 5 that links to each other; Symbol to_decode represents to be decoded via fifo buffer 6 time-delay output; Error code position pattern error_add input error-code pattern generation module 5, the error-code pattern error_ptn of output fec frame after error-code pattern generation module 5 is handled, the error-code pattern error_ptn of to_decode to be decoded and fec frame obtains to decipher through arithmetic unit 7 computings, finishes the decoding error correction of FEC.
Error-code pattern generation module 5 has two kinds of solutions commonly used in the prior art, is the design frame chart of the implementation one of error-code pattern generation module 5 as shown in Figure 2.This technical scheme comprises identical in structure two symmetric circuits up and down, and two symmetric circuits comprise the memory 53 of improper value computing module 55 and 255*8 respectively; This invention scheme utilizes switch 51 to select to go up branch road and following branch road in turn, error_add imports selected branch road with the error code position pattern, also utilize switch 52 with the error-code pattern error_ptn output that switch 51 selected branch roads produce, finish calculating, the output of error pattern.
This scheme is simple and reliable, designs easily and debugs, and its characteristics are in RS (255, the 239) decode procedure that the maximum of the upstream circuitry of error-code pattern generation module 5 is handled time-delay greater than 255 clock cycle, and is promptly long greater than a fec frame, and long less than two fec frames.Take turns to operate with two symmetric circuits and to have utilized this point well.Design in storage, output to improper value, this scheme adopts the memory of 255*8 to store the error pattern of a fec frame, and order output then with computing to be decoded, is finished error-correcting decoding.
Be the design frame chart of the implementation two of error-code pattern generation module 5 as shown in Figure 3.This technical scheme comprises identical in structure two symmetric circuits up and down equally, and two symmetric circuits comprise the memory 54 of improper value computing module 55 and 8*8 respectively, and address register 56, counter 57 and comparator 58; This invention scheme utilizes switch 51 to select to go up branch road and following branch road in turn, error_add imports selected branch road with the error code position pattern, also utilize switch 52 with the error-code pattern error_ptn output that switch 51 selected branch roads produce, finish calculating, the output of error pattern.
This technical scheme is an improvement to the aforementioned techniques scheme.Its improvement is that storage, the output of error code adopts the memory 54 of 8*8 to store 8 error codes of maximum of a FEC.Decoding circuit is a continuous productive process, and when not having error code, misaddress does not have, we define error code position is 1-255, if error code position is zero, then expression does not have error code, the error-code pattern of the data of this frame (255 bytes) can not calculate, and directly waits next frame just passable.When calculating error code, the error code values order is write 8 memory cell.The error code values of the byte that does not make a mistake is 0, is 255 error-code pattern error_ptn by several error codes (maximum is 8 bytes) and 0 formation length.When error code position pattern error_add passed to improper value computing module 55, address register 56 had also obtained misaddress.Address register 56 sum counters 57 link to each other with comparator 58 respectively simultaneously, when error_ptn exports, counter works, when the value of the value of counter and address register equates, pulse of comparator 58 output calls over the improper value of 54 li of the memories of 8*8, forms the error_ptn error-code pattern.
Area is the principle of design of integrated circuit as far as possible for a short time, though the implementation two of above-mentioned error-code pattern generation module has improved the implementation one of error-code pattern generation module effectively, make RS (255,239) the error correction coding area of chip reduces, but its chip area is still too big, and it is still too many to take resource, and if should design adopt FPGA to realize, also near the reducing of area adds 50%, and increases cost because the logic unit numbers purpose increases.
Summary of the invention:
The objective of the invention is to further reduce FEC error correction coding area of chip, reduce design and production cost, propose a kind of error-code pattern generative circuit and use the decoding circuit of this circuit.
For achieving the above object, the present invention proposes a kind of FEC error-code pattern generative circuit, is used for calculating and the generation error-code pattern according to the error code position pattern of input, and it comprises improper value computing module, first switch, storage and output circuit; Described storage and output circuit comprise up and down two symmetric circuits and can select to be connected in the second switch of branch road or time branch road of identical in structure; Described two symmetric circuits up and down comprise memory set respectively; It is characterized in that: error code position pattern directly order is imported described improper value computing module, the value that described improper value computing module calculates output is sequentially written into the described memory set that goes up in a symmetric circuit or the following symmetric circuit by described first switch, and the data in the described memory set are exported the formation error-code pattern in proper order by described second switch.
A kind of FEC decoding circuit that uses above-mentioned FEC error-code pattern generative circuit comprises syndrome computing module, interative computation module, asks the error code position module, error-code pattern generation module, fifo buffer and arithmetic unit; The described syndrome computing module of input to be decoded is through described syndrome computing module, described interative computation module, the described error code position pattern that the character position of error code takes place in the output expression forward error correction frames after the processing of error code position sequence of modules of asking; Described error-code pattern generation module is handled the back with described error code position pattern and is generated error-code pattern; To be decoded and described error-code pattern through described fifo buffer time-delay output obtains to decipher through described internalarithmetic; Described error-code pattern generation module comprises improper value computing module, first switch, storage and output circuit; Described storage and output circuit comprise up and down two symmetric circuits and can select to be connected in the second switch of branch road or time branch road of identical in structure; Described two symmetric circuits up and down comprise memory set respectively; It is characterized in that: described error code position pattern directly order is imported described improper value computing module, the value that described improper value computing module calculates output is sequentially written into the described memory set that goes up in a symmetric circuit or the following symmetric circuit by described first switch, data in the described memory set are exported the formation error-code pattern in proper order by described second switch, generate decode results for subsequent conditioning circuit.
The present invention directly imports same improper value computing module in proper order with the error code position pattern and calculates, rather than deliver to two improper value computing modules respectively by diverter switch, made full use of the disposal ability of improper value computing module, under the situation that upstream business is influenced not at all, saved resource to greatest extent.Because the processing speed of this module can practical requirement, so this module shared can not cause any negative influence.
Description of drawings:
Fig. 1 is RS (255, a 239) error correction coding chip design block diagram.
Fig. 2 is the design frame chart of the implementation one of error-code pattern generation module in the prior art.
Fig. 3 is the design frame chart of the implementation two of error-code pattern generation module in the prior art.
Fig. 4 is the design frame chart of error-code pattern generation module of the present invention.
Embodiment:
Also the present invention is described in further detail in conjunction with the accompanying drawings below by specific embodiment.
Present embodiment is an important improvement to original technical scheme two, the processing speed of noticing improper value computing module 55 is very fast, have more than is needed at all long time of a fec frame, can be owing to the shared data jamming that causes of this module, therefore present embodiment only uses an improper value computing module 55, again the storage in the scheme two, output are duplicated, form two circuit up and down.
As shown in Figure 4 be the design frame chart of present embodiment error-code pattern generation module 5, comprise improper value computing module 55, two-way switch 501 and switch 52, also comprise identical in structure two symmetric circuits up and down, two symmetric circuits comprise the memory 54 of 8*8 respectively, address register 56, counter 57 and comparator 58.
Suppose that two-way switch 501 is connected in branch road, error code position pattern error_add input error value computing module 55 calculates, through after calculating improper value, by two-way switch 501 wherein a road, the improper value order is write 8 memory cell of the memory 54 of 8*8.Error code position pattern error_add is through the direct input address register 56 in another road of two-way switch 501.The value input comparator 58 of address register 56 sum counters 57, comparator 58 outputs call over the memory 54 that 8*8 is given in pulse.When the output of improper value computing module 55 writes the memory 54 of 8*8 in proper order, counter 57 begins counting, when the value of the value of counter 57 and address register 56 equates, comparator 58 output calls over pulse the improper value of 54 li of the memories of 8*8 is called over by switch 52, forms error-code pattern error_ptn.One-way switch 52 is exported overturn later (from top to bottom) at error-code pattern.
If two-way switch 501 is connected in down branch road, the course of work is also identical.
The memory 54 of 8*8 also can be used the memory of other capacity instead in the present embodiment.
Present embodiment is imported same improper value computing module 55 with error code position pattern error_add and is calculated, make and have only an improper value computing module 55 in the error-code pattern generation module 5, make full use of the disposal ability of improper value computing module 55, saved resource to greatest extent.Simultaneously, present embodiment adopts the memory 54 of 8*8 in the upper and lower branch road to store 8 error codes of maximum of a FEC respectively, when the value of the value of counter and address register equates, the error-code pattern error_ptn of 54 li of the memories of 8*8 is called over by switch 52, made full use of the time-delay of the upstream circuitry of error-code pattern generation module 5.
Present embodiment is than the resource of one saving 200% of implementation in the prior art, and than the resource of two saving 60% of implementation in the prior art, chip area can reduce about 8 * (255-8)=1976 memory cell.The present invention adopts two-way switch to store this address when will giving the improper value computing module, is used for counting relatively, makes the structure of whole FEC chip circuit compact more.Present embodiment is reliably feasible through the analogue simulation proof.
An alternative embodiment of the invention is the improvement to scheme in the prior art one, promptly in scheme one, share improper value computing module 55, the direct order of error code position pattern error_add input error value computing module 55 is calculated, utilize diverter switch to select to go up branch road and following branch road in turn, last branch road and following branch road comprise the memory 53 of 255*8 respectively, the improper value of improper value computing module 55 outputs is write in the memory 53 of the 255*8 in the selected branch road in proper order, the improper value that the memory of 255*8 is 53 li calls over by switch 52, forms error-code pattern error_ptn.One-way switch 52 after error-code pattern output, overturn (from top to bottom or from down to up).Present embodiment is not shown in figures.
The present invention can pass through discrete component circuit, integrated circuit (IC) chip or software is realized, no matter which kind of implementation all belongs to protection scope of the present invention.
Claims (8)
1. a FEC error-code pattern generative circuit is used for calculating and generation error-code pattern (error_ptn) according to the error code position pattern (error_add) of input, and it comprises improper value computing module (55), first switch (501), storage and output circuit; Described storage and output circuit comprise up and down two symmetric circuits and can select to be connected in the second switch (52) of branch road or time branch road of identical in structure; Described two symmetric circuits up and down comprise memory set (54) respectively; It is characterized in that:
Error code position pattern (error_add) directly order is imported described improper value computing module (55), the value that described improper value computing module (55) calculates output is sequentially written into the described memory set (54) that goes up in a symmetric circuit or the following symmetric circuit by described first switch (501), and the data in the described memory set (54) constitute error-code pattern (error_ptn) by the output of described second switch (52) order.
2. error-code pattern generative circuit as claimed in claim 1 is characterized in that: described first switch (501) adopts two-way switch, and described two symmetric circuits up and down also comprise address register (56), counter (57) and comparator (58) respectively; Also by a described symmetric circuit or the described address register (56) in the symmetrical electric branch road down gone up of one tunnel input of described two-way switch (501), the memory set (54) in same the symmetric circuit at the output of improper value computing module (55) another road by described two-way switch (501) and described address register (56) place is connected in the time of the described improper value computing module of described error code position pattern (error_add) input (55); Output called over pulse and gives described memory set (54) when the value input comparator (58) of the value of described address register (56) and described counter (57), comparator (58) equated in the value of the value of described address register (56) and described counter (57).
3. error-code pattern generative circuit as claimed in claim 1, it is characterized in that: described first switch (501) adopts one-way switch (51), and the described described memory set (54) that goes up in a symmetric circuit or the following symmetric circuit is that capacity is the memory (53) of 255*8.
4. error-code pattern generative circuit as claimed in claim 2 is characterized in that: the described described memory set (54) that goes up in a symmetric circuit or the following symmetric circuit is that capacity is the memory (53) of 8*8.
5. FEC decoding circuit comprises syndrome computing module (2), interative computation module (3), asks error code position module (4), error-code pattern generation module (5), first-in first-out (FIFO) buffer (6) and arithmetic unit (7); The described syndrome computing module of input to be decoded (2) is through described syndrome computing module (2), described interative computation module (3), the described error code position pattern (error_add) that the character position of error code takes place in output expression forward error correction (FEC) frame after asking error code position module (4) sequential processes; Described error-code pattern generation module (5) is handled the back with described error code position pattern (error_add) and is generated error-code pattern (error_ptn); To be decoded and described error-code pattern (error_ptn) through described first-in first-out (FIFO) buffer (6) time-delay output obtains to decipher through described arithmetic unit (7) computing; , described error-code pattern generation module (5) comprises improper value computing module (55), first switch (501), storage and output circuit; Described storage and output circuit comprise up and down two symmetric circuits and can select to be connected in the second switch (52) of branch road or time branch road of identical in structure; Described two symmetric circuits up and down comprise memory set (54) respectively; It is characterized in that:
Described error code position pattern (error_add) directly order is imported described improper value computing module (55), the value that described improper value computing module (55) calculates output is sequentially written into the described memory set (54) that goes up in a symmetric circuit or the following symmetric circuit by described first switch (501), data in the described memory set (54) constitute error-code pattern (error_ptn) by the output of described second switch (52) order, generate decode results for subsequent conditioning circuit.
6. decoding circuit as claimed in claim 5 is characterized in that: described first switch (501) adopts two-way switch, and described two symmetric circuits up and down also comprise address register (56), counter (57) and comparator (58) respectively; Memory set (54) in same the symmetric circuit at the described described address register of going up in a symmetric circuit or the following symmetric circuit (56) of road input by described two-way switch (501) also in the time of the described improper value computing module of described error code position pattern (error_add) input (55), the output of improper value computing module (55) another road by described two-way switch (501) and described address register (56) place is connected; Output called over pulse and gives described memory set (54) when the value input comparator (58) of the value of described address register (56) and described counter (57), comparator (58) equated in the value of the value of described address register (56) and described counter (57).
7. decoding circuit as claimed in claim 5 is characterized in that: described first switch (501) adopts one-way switch (51), and the described described memory set (54) that goes up in a symmetric circuit or the following symmetric circuit is that capacity is the memory (53) of 255*8.
8. decoding circuit as claimed in claim 6 is characterized in that: the described described memory set (54) that goes up in a symmetric circuit or the following symmetric circuit is that capacity is the memory (53) of 8*8.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021086338A CN100346590C (en) | 2002-04-04 | 2002-04-04 | Error-code pattern generating circuit and decoding circuit using the same |
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| CNB021086338A CN100346590C (en) | 2002-04-04 | 2002-04-04 | Error-code pattern generating circuit and decoding circuit using the same |
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| CN1449151A CN1449151A (en) | 2003-10-15 |
| CN100346590C true CN100346590C (en) | 2007-10-31 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0065641A1 (en) * | 1981-05-19 | 1982-12-01 | International Business Machines Corporation | Synchronizer for medium speed multiplex data |
| JPH0832632A (en) * | 1994-07-15 | 1996-02-02 | Toshiba Corp | Transmission system and its device |
| CN1200212A (en) * | 1995-08-31 | 1998-11-25 | 艾利森电话股份有限公司 | Forward Error Correction Method Using Repeated Data Words |
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- 2002-04-04 CN CNB021086338A patent/CN100346590C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0065641A1 (en) * | 1981-05-19 | 1982-12-01 | International Business Machines Corporation | Synchronizer for medium speed multiplex data |
| JPH0832632A (en) * | 1994-07-15 | 1996-02-02 | Toshiba Corp | Transmission system and its device |
| CN1200212A (en) * | 1995-08-31 | 1998-11-25 | 艾利森电话股份有限公司 | Forward Error Correction Method Using Repeated Data Words |
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| CN1449151A (en) | 2003-10-15 |
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