JPH08321616A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device of which the off-current of a TFT is reduced and which is manufactured with high yield. CONSTITUTION: Within the peripheral driving circuit part of an active matrix type liquid crystal display, a gate electrode 110a of an NMOS.TFT and a source electrode 119a of PMOS.TFT 12 are connected by a relay electrode 103. Accordingly, the anode oxide films 111, 112A, 112B covering gate electrode 109a, 110a, 110b need not be etched away for connecting gate electrode to source electrode. Furthermore, this relay electrode 103 made of a light-shielding conductive film is pattern-formed simultaneously with a light-shielding film 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a thin film transistor provided on a transparent insulating substrate such as glass, and more particularly to a semiconductor device applicable to an active matrix type liquid crystal display device or the like.

[0002]

2. Description of the Related Art Generally, the above-mentioned active matrix type liquid crystal display device uses a thin film transistor (hereinafter referred to as a TFT) as a switching element of a matrix circuit section. This TFT is driven by an IC chip attached to the periphery of the matrix circuit section, and terminals for connecting the IC chip are usually formed by using gate wiring and source wiring. When the insulating film is etched using buffered hydrofluoric acid or the like when forming the terminals, cracks or the like are generated in the wiring, which causes a reduction in yield.

Therefore, a structure has been proposed in which the terminal portion is formed of a conductive film having resistance to buffered hydrofluoric acid, and the terminal portion is connected to the gate wiring and the source wiring (Japanese Patent Publication No. 7-1).
6012).

By the way, as an active matrix type liquid crystal display device, a driver monolithic active matrix type liquid crystal display device in which not only a matrix circuit portion but also its peripheral circuit portion are formed by using TFTs on the same substrate is known. . TF used in this liquid crystal display device
At T, since the channel length and the length of the gate electrode in the channel length direction are substantially the same, electric field concentration occurs at both ends of the channel to increase off current, which causes a problem that the display quality of the liquid crystal display device is deteriorated. there were. Therefore,
In order to solve this problem, a structure has been proposed in which an offset region is formed by anodizing the gate electrode to relax electric field concentration at both ends of the channel to reduce off current (Japanese Patent Laid-Open No. 5-267667). .

Further, since such a liquid crystal display device is often used as a transmissive type, off-current increases when external light is applied to the silicon layer which is an active body, which also deteriorates the display quality. There was a problem that it would occur. Regarding this problem, by providing a light shielding layer under the TFT,
A structure has been proposed in which light from the lower part of the substrate is shielded to suppress off current. A schematic diagram of a configuration example of the proposed semiconductor device is shown in FIGS. The semiconductor device in this illustrated example is a driver monolithic active matrix type liquid crystal display device.

FIG. 3A is a plan view of a TFT constituting the matrix circuit portion, FIG. 3C is a sectional view taken along the line CC ′ of FIG. 3A, and FIG. 3B is a peripheral circuit. TF which constitutes the section
FIG. 3D is a plan view of T, and FIG. 3D is a sectional view taken along line DD ′ of FIG. In this semiconductor device, a light-shielding film 302 is formed on a glass substrate 301 in a TFT portion forming a matrix circuit portion and a TFT portion forming a peripheral circuit portion. Further, the insulating film 30 is formed so as to cover each light shielding film 302.
3 are formed. Semiconductor layers 304, 305, 306 are formed on the respective TFT formation portions on the insulating film 303, and the respective semiconductor layers 304, 305, 306 are respectively channel regions 304a, 305a, 306a, source regions and drain regions 304b, 305b. , 306b. The semiconductor layers 304, 305, 306 are covered with S
A gate insulating film 307 made of iO ₂ or the like is formed.

In the TFT portion forming the matrix circuit portion, a gate electrode 308 having a surface covered with an anodic oxide film 310 is formed on the gate insulating film 307.
On the other hand, in the TFT portion that constitutes the peripheral circuit portion, a gate electrode 309 whose surface is covered with the anodic oxide film 311 is formed on the gate insulating film 307. An interlayer insulating film 312 is formed so as to cover the gate electrodes 308 and 309.

In the TFT portion forming the matrix circuit portion, the source electrode 314 is formed on the interlayer insulating film 312.
And a drain electrode 315 is formed. The source electrode 314 and the drain electrode 315 are the gate insulating film 3
07 and the source region and the drain region 30 through the contact hole 321 penetrating the interlayer insulating film 312.
4b is electrically connected. This drain electrode 31
5 is electrically connected to the transparent pixel electrode 313 formed on the interlayer insulating film 312.

On the other hand, in the TFT portion which constitutes the peripheral circuit portion, one (left) TF having the semiconductor layer 305 is provided.
A source electrode 316 and a drain electrode 317 are formed on the interlayer insulating film 312 in the T portion. The source electrode 316 and the drain electrode 317 are the gate insulating film 307.
And the contact hole 3 penetrating the interlayer insulating film 312
21 via the source and drain regions 305b
Is electrically connected to Further, the gate electrode 309 of this TFT portion is connected to the wiring 318A through a contact hole 322 penetrating the interlayer insulating film 312 and the anodic oxide film 311.

A source electrode, which is the end of the wiring 318A opposite to the gate electrode 309, is formed on the interlayer insulating film 312 of the other TFT portion (right side) having the semiconductor layer 306. The source electrode is electrically connected to the source region 305b through a contact hole 321 penetrating the gate insulating film 307 and the interlayer insulating film 312. In addition, the interlayer insulating film 3 of the same TFT portion
A drain electrode 319 is formed on the gate electrode 12 and is electrically connected to the drain region 305b through a contact hole 321 penetrating the gate insulating film 307 and the interlayer insulating film 312. Further, the gate electrode 309 of this TFT portion has a wiring 318B through a contact hole 322 penetrating the interlayer insulating film 312 and the anodic oxide film 311.
It is connected to the.

In the semiconductor device having such a structure, since the offset region is formed by the anodic oxide film on the surface of the gate electrode, the electric field concentration at both ends of the channel can be relaxed, and the light shielding film is provided below the semiconductor layer. Since it is provided, it is possible to block the light from the lower part of the substrate,
The off current of T can be suppressed.

[0012]

By the way, when the TFT is used in the peripheral circuit portion as described above, the gate electrode 3 is used.
In order to connect 09 and the wiring 318A (or 318B), a part of the anodic oxide film 311 needs to be removed by etching. For this etching, for example, when Al is used as the gate electrode, the anodic oxide film needs to be subjected to wet etching using phosphoric acid or hydrofluoric acid, dry etching using BCl ₃ gas, or the like.

However, in such etching, it is extremely difficult to etch only the anodic oxide film because the selection ratio between the anodic oxide film and the underlying Al film (gate electrode) is very small. Therefore, there is a problem that the yield at the time of semiconductor device production is low and the manufacturing cost is high.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a semiconductor device which can reduce the OFF current of the TFT and can be manufactured with a high yield.

[0015]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor layer formed on a substrate and having at least a channel region, a source region, and a drain region, a gate electrode formed on the semiconductor layer with a gate insulating film interposed therebetween, and a gate in each of the source region and the drain region. A plurality of thin film transistors including a source electrode and a drain electrode electrically connected through a contact hole penetrating the insulating film are provided, and the source electrode and the drain in one thin film transistor of the plurality of thin film transistors are provided. At least one of the electrodes,
The gate electrode of another thin film transistor is electrically connected to the relay electrode provided in an insulating state from the other thin film transistors, thereby achieving the above object.

In the semiconductor device of the present invention, the surface of the gate electrode is covered with an anodic oxide film, and at least one of a source electrode and a drain electrode in the one thin film transistor without breaking the anodic oxide film, A gate electrode of the other thin film transistor may be electrically connected to the relay electrode.

In the semiconductor device of the present invention, the channel length of the thin film transistor may be defined by the anodic oxide film.

In the semiconductor device of the present invention, the relay electrode may be made of a material having a light shielding property.

[0019]

In the present invention, one TF of a plurality of TFTs is used.
At least one of the source electrode and the drain electrode of T and the gate electrode of the other TFT are electrically connected to the relay electrode. Therefore, even if the surface of the gate electrode is covered with the anodic oxide film, it is not necessary to etch the anodic oxide film for connecting the gate electrode and at least one of the source electrode and the drain electrode, and the offset region is provided. The TFT can be formed with high yield. Further, the channel length can be defined by the thickness of this anodic oxide film.

Further, when the relay electrode is formed by using a material having a light shielding property, the patterning of the relay electrode and the light shielding film can be performed at the same time, so that the external light to the TFT can be increased without increasing the manufacturing process. Can be prevented.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

1 (a) to 1 (d) show the essential parts of a semiconductor device according to an embodiment of the present invention. This semiconductor device is a driver monolithic active matrix type liquid crystal display device. FIG. 1A shows a T which constitutes a matrix circuit section.
A plan view of the FT, (c) is a cross-sectional view taken along the line AA ′ of (a), (b) is a plan view of a TFT constituting a peripheral circuit portion,
(D) is the BB 'sectional view taken on the line of (b).

In this semiconductor device, an NMOS / TFT is provided as a matrix circuit TFT 1 and a CMOS / TFT is provided as a peripheral circuit TFT 2 at predetermined positions on the upper surface of a transparent insulating substrate 101 such as glass. There is. The peripheral circuit TFT 2 is composed of an NMOS / TFT 11 and a PMOS / TFT 12.

On the upper surface of the transparent insulating substrate 101, a light shielding film 102 and a relay electrode 103 are pattern-formed at predetermined positions, and the insulating film 10 is formed on the entire substrate so as to cover them.
4 are formed.

On the insulating film 104, semiconductor layers 105, 106 and 107 are patterned on the light shielding film 102 portion. The semiconductor layers 105, 106 and 107 have channel regions 105a, 106a and 107a at the center and source and drain regions 105b, 106b and 107b made of high concentration impurity regions at both sides thereof. A gate insulating film 108 is formed over the insulating film 104 so as to cover the semiconductor layers 105, 106 and 107. In the matrix circuit portion, a gate electrode 109 is patterned on the gate insulating film 108 so as to correspond to the channel region 105a.

On the other hand, in the peripheral circuit section,
A wiring 110A having a portion corresponding to the channel region 106a as a gate electrode 110a is patterned on the gate insulating film 108 in the TFT 11 portion. This wiring 1
10A has the other end opposite to the gate electrode 110a positioned on the relay electrode 103, and the other end electrically connected to the relay electrode 103 through a contact hole 121 penetrating the gate insulating film 108 and the insulating film 104. Connected to each other. Further, a wiring 110B having a portion corresponding to the channel region 107a as a gate electrode 110b is patterned on the gate insulating film 108 in the PMOS / TFT 12 portion. The wiring 110B is the gate electrode 110.
The other end on the side opposite to b is electrically connected to an electrode (not shown). These gate electrode 109 and wiring 110A,
The surface of 110B is anodized to form an anodized film 11 respectively.
1, 112A, 112B. The anodic oxide films 111, 112A, 112B and the gate electrodes 109, 11
Below the portion consisting of 0a and 110b is the channel region 10.
5a, 106a, 107a, and the gate electrode 1
The length of 09, 110a, 110b in the channel length direction is shorter than the length of the channel regions 105a, 106a, 107a in the channel length direction.

Further, the anodic oxide films 111, 112A, 1
Gate electrodes 109, 110a, 110b having 12B
To cover the entire surface of the gate insulating film 108 and the interlayer insulating film 1
13 is formed.

In the portion of the interlayer insulating film 113 and the gate insulating film 108 of the matrix circuit TFT 1, a contact hole 122 is formed at a position corresponding to the source region and the drain region 105b, and the contact hole 122 is partially filled. The source electrode 115 and the drain electrode 116 are patterned. As a result, the source electrode 115 and the drain electrode 116 are electrically connected to the source region and the drain region 105b, respectively. In this matrix circuit portion, a pixel electrode 114 made of a transparent conductive film such as ITO is patterned at a predetermined position on the upper surface of the interlayer insulating film 113 and electrically connected to the drain electrode 116.

In the portion of the interlayer insulating film 113 and the gate insulating film 108 of the NMOS TFT 11 in the peripheral circuit portion, a contact hole 122 is formed at a position corresponding to the source region and the drain region 106b, and a part of this contact hole 122 is formed. Source electrode 117 filled
And the drain electrode 118 is patterned.
Thereby, the source electrode 117 and the drain electrode 11
Reference numerals 8 are electrically connected to the source and drain regions 106b, respectively.

A contact hole 122 is formed at a position corresponding to the source region and the drain region 107b in a portion of the interlayer insulating film 113 and the gate insulating film 108 of the PMOS / TFT 12 in the peripheral circuit portion, and a part of this contact hole 122 is formed. Source electrode 119 filled
The a and drain electrodes 120 are patterned. As a result, the source electrode 119a and the drain electrode 120 are the source region and the drain region 107b, respectively.
Is electrically connected to. The source electrode 119a is one end of the wiring 119, and the other end is electrically connected to the relay electrode 103 through a contact hole 123 penetrating the interlayer insulating film 113, the gate insulating film 108, and the insulating film 104. There is. Therefore, the CMO of the peripheral circuit section
In the S · TFT2, the gate electrode 110a of the NMOS · TFT11 and the source electrode 11 of the PMOS · TFT12
9a is electrically connected to the relay electrode 103 or the like.

Such a semiconductor device is shown in FIGS.
(E) and (a ') to (e') can be manufactured by the manufacturing steps. 2 (a) to 2 (e) and 2 (a ') to 2 (e') show respective steps in process order, and (a) to 2 (e) on the left side of the drawing are shown in FIG. 1 (a). The cross section taken along the line AA ′ and (a ′) to (e ′) on the right side of the figure respectively show the cross section taken along the line BB ′ in FIG.

First, Ta, Nb is formed on a transparent substrate 101 having an insulating surface such as glass by a sputtering method or the like.
A high melting point metal film such as the above is deposited to a thickness of about 100 nm.
By etching this using a photolithography method, as shown in FIGS. 2 (a) and 2 (a ′),
The light-shielding film 102 and the relay electrode 103 are simultaneously patterned on a predetermined portion of the upper surface of the substrate 101.

Next, the light shielding film 102 and the relay electrode 103
An insulating film 1 of SiO ₂ or SiN _x, etc. is formed on the entire substrate so as to cover the substrate by sputtering or plasma CVD.
04 is deposited to a thickness of about 300 nm.

Subsequently, the amorphous silicon film is formed by CVD to a thickness of 10 nm to 200 nm, preferably 30 nm.
The amorphous silicon film is made to have crystallinity by being deposited in a thickness of m to 100 nm and baking the entire substrate at a temperature of about 600 ° C., or by irradiating the amorphous silicon film with high energy light such as an excimer laser. It is a polysilicon film. By etching this using a photolithography method, as shown in FIGS. 2B and 2B ′, the semiconductor layers 105, 106 and 107 are patterned on the light shielding film 102 portion of the insulating film 104.

After that, the semiconductor layers 105, 106 and 107
A gate insulating film 108 made of SiO ₂ or SiN _x is deposited to a thickness of about 100 nm on the entire substrate by using a sputtering method or a plasma CVD method so as to cover the film.

Next, as shown in FIGS. 2B and 2B ', a contact hole 121 is opened at a predetermined position on the relay electrode 103 in the gate insulating film 108 and the insulating film 104.

Subsequently, a low resistance metal film such as Al or Al-based alloy is formed on the gate insulating film 108 so as to fill the contact hole 121 by a sputtering method or the like 350.
Deposit to a thickness of about nm. By etching this using a photolithography method, the gate electrode 1
09 and the wiring 11 having the gate electrode 110a as an end portion
A wiring 110B having 0A and the gate electrode 110b as an end is patterned.

After that, the gate electrode 109 and the wiring 110
By anodizing A and 110B, as shown in FIGS. 2 (c) and 2 (c ′), the anodic oxide film 111,
112A and 112B are formed. In this anodic oxidation method, the substrate is immersed in an anodizing solution such as an aqueous tartaric acid solution, the positive side of a constant current source is connected to the gate electrode, the negative side is connected to the counter electrode, and a formation voltage of about 100 V is applied. By doing. As a result, an anodic oxide film having a thickness of about 140 nm is obtained. This anodic oxide film plays a role of forming an offset region and preventing hillocks of Al and an Al-based alloy in the subsequent thermal process.

Next, a photosensitive resin such as a resist is formed in a predetermined pattern (not shown), and the photosensitive resin and the gate electrodes 109 and 110a and the anodic oxide films 111 and 112A are formed.
Using as a mask, n-type impurities such as P ⁺ are implanted into the semiconductor layers 105 and 106 from the upper portion of the substrate by an ion doping method to remove the photosensitive resin. Further, by using the photosensitive resin formed in another predetermined pattern and the gate electrode 110b and the anodic oxide film 112B as a mask, B ⁺
Layer 1 for p-type impurities such as
07, and the photosensitive resin is removed. At this time, the patterning of the photosensitive resin and the implantation of impurities may be performed in either the p-type region or the n-type region first. Then 6
By activating the implanted impurities by baking the entire substrate at a temperature of about 00 ° C. or irradiating the impurity-implanted polysilicon film with high-energy light such as an excimer laser, the implanted impurities are activated as shown in FIG. Source and drain regions 105b, 106 as shown in (c ')
b, 107b are formed. At this time, the central portion of the semiconductor layer made of the polysilicon film below the anodic oxide films 111, 112A, 112B and the gate electrodes 109, 110a, 110b, into which impurities are not implanted, has a channel region 105a,
106a and 107a.

Subsequently, the anodic oxide films 111, 112A, 1
An interlayer insulating film 113 made of SiO ₂ or SiN _x or the like is deposited to a thickness of about 400 nm on the entire gate insulating film 108 so as to cover 12B by using a sputtering method or a plasma CVD method.

Then, a transparent conductive film such as ITO is deposited to a thickness of about 100 nm by a sputtering method or the like, and is etched by using photolithography or the like, as shown in FIGS. 2 (d) and 2 (d '). Pixel electrodes 114 are pattern-formed at predetermined locations on the upper surface of the interlayer insulating film 113 in the matrix circuit portion.

Next, as shown in FIGS. 2E and 2E ', in the interlayer insulating film 113 and the gate insulating film 108, the source and drain regions 105b and 106 are formed.
b, 107b at the portion corresponding to the contact hole 122
To open. At the same time, the interlayer insulating film 113 and the gate insulating film 1
08 and the insulating film 104, a contact hole 123 is opened in a portion different from the contact hole 121 corresponding to the relay electrode 103.

Subsequently, these contact holes 12
The interlayer insulating film 113 is partially filled with 2, 123.
A low resistance metal film such as Al or an Al-based alloy is deposited to a thickness of about 500 nm on the top by using a sputtering method or the like. By etching this using a photolithography method, as shown in FIGS. 2E and 2E ′, the wiring 119 having the source electrodes 115 and 117 and the source electrode 119a as end portions and the drain electrode 116, 11
8 and 120 are patterned. Through the above steps, the semiconductor device shown in FIG. 1 is completed.

As described above, in the semiconductor device of this embodiment, the TFT 12 is formed by the relay electrode 103 formed in the peripheral circuit portion.
Source electrode 119a and the gate electrode 11 of the TFT 11
0a can be electrically connected. Therefore, the step of etching the anodic oxide film, which is indispensable in the conventional semiconductor device using the anodic oxide film, is unnecessary, and a TFT with a small off current can be manufactured with high yield. Further, since the relay electrode 103 is patterned simultaneously with the light-shielding film using a material having a light-shielding property, a TFT with a small off-current can be manufactured without increasing the number of manufacturing steps.

In the above embodiment, the source electrode and the gate electrode are connected by the relay electrode, but the present invention is also applicable when at least one of the source electrode and the drain electrode and the gate electrode are connected by the relay electrode. Applicable.

In the above embodiment, the TFT is provided in the drive circuit section.
, And the source electrode of another TFT were connected by a relay electrode.
The present invention can be applied to a case where at least one of the source electrode and the drain electrode of T and the gate electrode of another TFT are connected by a relay electrode.

[0047]

As is apparent from the above description, according to the present invention, at least one of the source electrode and the drain electrode of one of the plurality of TFTs and the gate electrode of the other TFT are provided. It is electrically connected via the relay electrode. Therefore, even when a TFT in which an offset region is formed using an anodic oxide film is manufactured, a step of etching the anodic oxide film is unnecessary, and therefore a TFT with a small off current can be manufactured with high yield. The cost can be reduced. Further, the channel length can be defined by the thickness of the anodic oxide film.

When the relay electrode is formed of a material having a light-shielding property, it is possible to form a pattern simultaneously with the light-shielding film, so that it is possible to prevent the external light from illuminating the TFT and reduce the off-current without increasing the manufacturing process. be able to.

Therefore, by using the semiconductor device of the present invention for an active matrix type liquid crystal display device or the like, a liquid crystal display device having excellent display quality can be manufactured with high yield and at low cost without increasing the number of manufacturing steps. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of a semiconductor device according to an embodiment of the present invention, in which (a) is a TF forming a matrix circuit part.
A plan view of T, (b) is a plan view of a TFT constituting a peripheral circuit portion, (c) is a sectional view taken along the line AA ′ of (a), and (d) is a sectional view taken along the line BB ′ of (b). It is a figure.

2 (a) to (e) and (a ′) to (e ′) are
FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG. 1.

3A and 3B are schematic views of a conventional semiconductor device, FIG. 3A is a plan view of a TFT forming a matrix circuit section, FIG. 3B is a plan view of a TFT forming a peripheral circuit section, and FIG. ) Is a cross-sectional view taken along the line CC ', and (d) is a cross-sectional view taken along the line DD' of (b).

[Explanation of symbols]

 1 TFT for Matrix Circuit Section 2 TFT for Peripheral Circuit Section 11 NMOS / TFT 12 PMOS / TFT 101 Transparent Substrate 102 Light Shielding Film 103 Relay Electrode 104 Insulating Film 105, 106, 107 Semiconductor Layer 108 Gate Insulating Film 109, 110a, 110b Gate Electrode 110A, 110B, 119 Wirings 111, 112A, 112B Anodized film 113 Interlayer insulating film 114 Pixel electrodes 115, 117, 119a Source electrodes 116, 118, 120 Drain electrodes 121, 122, 123 Contact holes

Claims (4)

[Claims] 1. A semiconductor layer formed on a substrate and having at least a channel region, a source region, and a drain region, a gate electrode formed on the semiconductor layer with a gate insulating film interposed therebetween, the source region, and A plurality of thin film transistors each including a source electrode and a drain electrode electrically connected to each other through a contact hole provided through the gate insulating film in the drain region are provided, and one thin film transistor among the plurality of thin film transistors is provided. A semiconductor device in which at least one of the source electrode and the drain electrode and the gate electrode of another thin film transistor are electrically connected to a relay electrode provided in an insulating state from the other. 2. The surface of the gate electrode is covered with an anodic oxide film, and at least one of the source electrode and the drain electrode in the one thin film transistor and the other thin film transistor are formed without breaking the anodic oxide film. The semiconductor device according to claim 1, wherein a gate electrode is electrically connected to the relay electrode. 3. The semiconductor device according to claim 2, wherein a channel length of the thin film transistor is defined by the anodic oxide film. 4. The semiconductor device according to claim 1, wherein the relay electrode is made of a light-shielding material.