JPH0831933A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To set an interconnection in an intermediate layer to good continuity by a method wherein, when a contact hole is formed, a difference in level is formed in a part in which the contact hole is formed before the interconnection in the intermediate layer is deposited and the interconnection in the intermediate layer is made thick. CONSTITUTION:An-aluminum electrode interconnection 17 is set to continuity to an aluminum electrode interconnection 14, and it is set to continuity to a silicon substrate 11. At this time, before the aluminum electrode interconnection 14 is deposited, a difference in level 14a is formed. Then, a hole is made in a part 17a in which a contact hole is to be formed, and the electrode interconnection 17 is formed. Thereby, the film of the electrode interconnection 14 is made locally thick, and the contact are of the electrode interconnection 14 with the electrode interconnection 17 is made large. Consequently, when a contact hole is made collectively in respective layers for a semiconductor device having a multilayer interconnection, an interconnection in an intermediate layer can be set to good continuity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a multilayer wiring and a method of forming a contact of the multilayer wiring.

[0002]

2. Description of the Related Art In recent years, with the progress of semiconductor technology, in large-scale semiconductor integrated circuits such as memories and processors, miniaturization and densification have been advanced, and the operation speed has been increased. In order to increase the density, it goes without saying that miniaturization is required, but for example, aluminum wiring is multilayered. In order to form multi-layer wiring and obtain high density, contact for connecting the intermediate layer electrode wiring and upper layer electrode wiring on top of the contact for connecting the lower layer electrode wiring and the intermediate layer electrode wiring. Must be formed, and how to form a highly reliable contact is a very important issue.

A conventional method of manufacturing a semiconductor device having a multi-layer wiring will be described below with reference to FIGS.

First, as shown in FIG. 2A, a silicon oxide film 22 is formed on a silicon substrate 21 by a CVD method to form 100
After forming about 00Å, aluminum 23 which will be the first layer wiring is accumulated by the sputtering method and patterned by using a photoresist.

Next, as shown in FIG. 2B, a silicon oxide film 24 is formed as an interlayer insulating film to a thickness of about 10,000 Å, and then contact holes are opened to both the silicon substrate 21 and the first-layer aluminum wiring 23. After forming a photoresist pattern for this as shown in FIG. 2C, the silicon oxide film 24, the first-layer aluminum wiring 23, and the silicon oxide film 22 are etched by anisotropic etching.

Next, as shown in FIG. 2D, after removing the photoresist, aluminum 26 to be the second layer wiring is formed and patterned. At that time, as shown in FIG. 2D, the aluminum wiring 23 is penetrated to form a contact with the silicon substrate 21.

As described above, the semiconductor device having the multilayer wiring is manufactured.

[0008]

However, in the case of forming a contact, which is indispensable for promoting high density and miniaturization, so as to be electrically connected from the upper layer wiring to the wiring of the intermediate layer and also to the lower layer wiring. The conduction with the wiring of the intermediate layer becomes a problem. That is, there is a problem that the contact resistance becomes excessive. For example, in a conventional multi-layer wiring type semiconductor device, the contact surface between the aluminum wiring 23 and the aluminum wiring 26 in FIG. 2D is small, the possibility of conduction failure is high, and the reliability is low.

Further, in the conventional method for manufacturing a semiconductor device of a multi-layer wiring type, the wiring of the upper layer is penetrated through the wiring of the intermediate layer,
In the case where the lower layer wiring is collectively formed by the contact having the holes, there is a problem that it is difficult to improve the electrical connection with the intermediate layer wiring.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to form an intermediate layer wiring when forming a collective contact hole in each layer of a semiconductor device having a multilayer wiring. Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof which can obtain good conduction and have high reliability against variations in the manufacturing process.

[0011]

To achieve the above object, the first feature of the first invention is that a first insulating film is formed on a semiconductor substrate on which a desired element region is formed, or on a lower electrode wiring. A first insulating film forming step, a step forming step of selectively etching the first insulating film to form a step in a region where a contact is to be opened later, and a step of forming a step on the first insulating film. A first electrode wiring forming step of forming one electrode wiring, a second insulating film forming step of forming a second insulating film on the first electrode wiring, the second insulating film and the first A contact forming step of selectively etching the electrode wiring and the first insulating film to form a contact hole, and a second connecting to the first electrode wiring and the lower electrode wiring or the semiconductor substrate through the contact hole. Second electrode wiring type that forms the electrode wiring of It is to include a step.

A second feature of the first invention is that in the step of forming the first electrode wiring, the first electrode wiring is reflowed to embed the step portion.

A second aspect of the present invention is that the semiconductor substrate or the lower electrode wiring, the first insulating film formed on the semiconductor substrate or the lower electrode wiring, and the first insulating film on the first insulating film. The formed first electrode wiring, the second insulating film formed on the first electrode wiring, the first and second insulating films, the first electrode wiring, and the semiconductor substrate or the lower layer. In a semiconductor device having a second electrode wiring formed in contact with the electrode wiring, a cross-sectional area of the first electrode wiring at a contact portion between the second electrode wiring and the first electrode wiring is The contact area is larger than the cross-sectional area of the first electrode wiring.

The above etching is preferably anisotropic etching, for example, RIE is preferable since etching can be performed in the same manner as a resist pattern.

Here, in the contact forming step, each layer may be etched once or a plurality of times may be etched for each layer.

[0016]

According to the first feature of the first invention, in forming the contact hole for connecting the upper layer wiring to the intermediate layer and the lower layer wiring, before depositing the intermediate layer wiring,
By forming a step at the place where the contact hole is formed and increasing the wiring thickness of the intermediate layer, the contact cross-sectional area of the wiring of the intermediate layer at the time of contact formation is increased, and the conduction surface is increased. .

According to the second feature of the first invention,
In the step of forming the first electrode wiring, the first electrode wiring is reflowed (flattened) to fill in the gap formed in the step forming step, thereby adjusting the resist patterning occurring in the manufacturing process. A sufficient contact cross-sectional area can be obtained even with respect to the deviation, and the manufacturing margin is widened.

According to the second aspect of the invention, the contact cross-sectional area of the wiring of the intermediate layer at the time of contact formation is increased,
The conductive surface is enlarged to reduce the contact resistance.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In this method, the aluminum electrode wiring 17 is electrically connected to the aluminum electrode wiring 14 and the silicon substrate 11 is used, as shown in the manufacturing process of FIGS.
When the aluminum electrode wiring 14 is electrically connected to the aluminum electrode wiring 14, the aluminum electrode wiring 14 and the aluminum electrode wiring 17 can be electrically connected with high reliability by forming the step 14a before depositing the aluminum electrode wiring 14. It is characterized by that.

First, as shown in FIG. 1A, the silicon oxide film 12 is formed on the silicon substrate 11 as in the conventional method.
After forming about 10000Å by CVD method (600
0Å to 15000Å), photoresist 13
After patterning a portion 14a which may be a contact hole by using, the anisotropic etching is applied to 3000-4.
Approximately 000Å (2000Å to 8000Å may be used) Etching to form contact holes 14
A step is formed on a. It should be noted that this step is formed in a range where the silicon substrate 11 is not exposed.

Next, after removing the photoresist 13, as shown in FIG. 1 (b), aluminum is sputtered to about 6000Å (2000Å to 15000Å).
(Although it may be) deposited and patterned to form the aluminum electrode wiring 14, and further, a silicon oxide film 15 as an interlayer insulating film is formed by the CVD method at about 10,000 Å (4
000 Å to 15,000 Å may be used).

Next, as shown in FIG. 1C, the photoresist 16 is patterned to open a contact hole forming portion 17a, and the silicon oxide film 15, the aluminum electrode wiring 14, and the silicon oxide film 12 are changed. Etching is performed by isotropic etching to open a hole up to the silicon substrate 11 (FIG. 1D).

Finally, as shown in FIG. 1 (e), aluminum is deposited by a sputtering method and a photoresist is used.
By patterning, the electrode wiring 17 is formed.

In the contact structure thus formed, the film thickness of the electrode wiring is locally thickened, so that when the wiring is formed penetrating that portion, the electrode wiring 14 and the electrode wiring 17 are formed. The contact area becomes large and good conduction can be obtained.

In this embodiment, the step is formed at the penetrating portion and the wiring is simply deposited, but it may be embedded in the step portion. That is, the aluminum electrode wiring 14 may be reflowed (flattened) and embedded in the step portion by a heating process to make the upper surface portion flat. This is because by increasing the thick portion of the electrode wiring in the step portion, a sufficient contact cross-sectional area can be obtained even with respect to misalignment that occurs during resist patterning in FIG. 1C.
The allowable range of misalignment can be widened.

After passing through the contact and opening the contact,
By embedding tungsten or the like, it is effective for an elongated contact hole as in this embodiment.

Further, the anisotropic etching is used in the present embodiment because it is preferable in that etching can be performed in the same pattern as the resist, as compared with isotropic etching (eg wet etching or CDE). Among these, RIE and the like are preferable.

In addition, various modifications can be made without departing from the scope of the present invention.

[0030]

As described above, according to the first feature of the first aspect of the present invention, it is possible to achieve reliable conduction by increasing the film thickness at the place where the electrode wiring is penetrated.

According to the second feature of the first invention,
It is possible to widen the allowable range of misalignment at the time of resist patterning that occurs in the manufacturing process.

Further, according to the second invention, by increasing the contact cross-sectional area of the wiring of the intermediate layer at the time of forming the contact, it is possible to increase the conductive surface and reduce the contact resistance.

[Brief description of drawings]

1A to 1E are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.

2A to 2D are manufacturing process diagrams of a conventional semiconductor device.

[Explanation of symbols]

 11 Silicon Substrate 12 Silicon Oxide Film 13 Photoresist 14 Aluminum Wiring 14a Contact Hole 15 Silicon Oxide Film 16 Photoresist 17 Aluminum Wiring 17a Contact Hole 21 Silicon Substrate 22 Silicon Oxide Film 23 Aluminum Wiring 24 Silicon Oxide Film 25 Photoresist 26 Aluminum Wiring

Claims (3)

[Claims] 1. A first insulating film forming step of forming a first insulating film on a semiconductor substrate on which a desired element region is formed or on a lower electrode wiring, and the first insulating film is selectively formed. A step of forming a step in a region where a contact is to be opened later by etching, a step of forming a first electrode wiring on the first insulating film, and a step of forming a first electrode wiring, A second insulating film forming step of forming a second insulating film thereon; a contact forming step of selectively etching the second insulating film, the first electrode wiring and the first insulating film to form a contact hole And a second electrode wiring forming step of forming the first electrode wiring and the lower electrode wiring or the second electrode wiring connected to the semiconductor substrate through the contact hole. Manufacturing method. 2. The step of forming the first electrode wiring comprises:
The method of manufacturing a semiconductor device according to claim 1, wherein the first electrode wiring is reflowed to fill the step portion. 3. A semiconductor substrate or a lower layer electrode wiring, a first insulating film formed on the semiconductor substrate or a lower layer electrode wiring, and a first electrode wiring formed on the first insulating film. And a second insulating film formed on the first electrode wiring, and formed in contact with the first and second insulating films, the first electrode wiring, and the semiconductor substrate or the lower electrode wiring. In a semiconductor device having a second electrode wiring, a cross-sectional area of the first electrode wiring in a contact portion between the second electrode wiring and the first electrode wiring is a non-contact portion of the first electrode. A semiconductor device characterized by being larger than a cross-sectional area of wiring.