JPH09306992A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the contact resistance between an upper and lower layer wirings to provide stable characteristics by forming a first wring layer having tapered part extending into first vias and a second insulation film having second vias piercing the second film to the interior of the first film. SOLUTION: After removing a first conductive film entirely on the surface of a first insulation film 2, etching is continued to form tapered part 12 extending from the first insulation film 2 into first vias 3. A second insulation film 5 is formed on the all top faces of them by the CVD method, etc. The photomechanical process is combined with etching to form second vias 16 through the second insulation film 5 on the first vias 3. The 2nd vias 16 piercing the second film 5 are formed by etching a part of the first insulation film 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having via holes for connecting wiring layers.

[0002]

2. Description of the Related Art With the high integration of semiconductor devices, the demand for wiring intervals has become more and more strict. Improving the alignment accuracy of photoengraving technology is indispensable for obtaining a multi-layer wiring structure with a high degree of integration, but the amount of misalignment cannot be eliminated at all. Forming a wiring pattern with allowance for this misalignment amount hinders high integration.

For example, when a via hole is formed on a wiring layer, the width of the wiring should be at least on the via hole so that the via hole is formed on the wiring layer even if misalignment occurs. It is necessary to set as wide as this alignment precision amount. However, there is a strong demand for high integration, and as miniaturization progresses, it is impossible to design with a sufficient margin.

FIG. 6 is a sectional view showing a conventional semiconductor device. In FIG. 6, 1 is a semiconductor substrate, 2 is a first insulating film formed on the semiconductor substrate 1, and 3 is a first insulating film 2. The formed first via holes 4 are formed on the first insulating film 2, the lower layer wiring filling the first via holes 3 is a second insulating film formed on the lower layer wiring 4, and 6 is The second via hole 7 formed in the second insulating film 5 is an upper layer wiring formed in the second insulating film 5 and filling the second via hole 6. Second via hole 6 as shown
Is displaced from the lower layer wiring 4, not only the upper surface portion of the lower layer wiring 4 but also a part of the side wall portion 8 is exposed in the second via hole 6. Then, the upper layer wiring is embedded in the second via hole 6, and the upper surface portion of the lower layer wiring 4 and the side wall portion 8 are in contact with each other.

FIG. 7 is a sectional view showing a conventional semiconductor device disclosed in Japanese Patent Application Laid-Open No. 7-283319, etc., and a side wall of a lower layer wiring 4 is provided with a tapered portion 9 having an inclination angle. FIG. 8 is a plan view showing another conventional semiconductor device, the cross section of which is equivalent to those shown in FIGS. 6 and 7,
The lower layer wiring 4 does not extend in the depth direction of these figures.
That is, the lower layer wiring 4 is a plug having a head protruding above the first insulating film 2, and the upper layer wiring 7 is simply connected to the semiconductor substrate 1 (or wiring provided under the plug). Since it is used for connection, the head has a minimum required pattern, and is shaped like a nail.

[0006]

The conventional semiconductor device as shown in FIG. 6 has a problem that the contact resistance between the upper and lower wirings 7 and 4 becomes high. That is, when forming the upper layer wiring 7, the natural oxide film on the surface of the lower layer wiring 4 is removed by argon (Ar) sputter etching, but the amount of Ar incident on the side wall portion is extremely small. It is difficult to remove the film, the natural oxide film remains, and the contact resistance at the side wall portion 8 becomes extremely high.

In order to deal with this problem, it has been proposed to provide a taper portion 9 having an inclination angle on the side wall of the lower layer wiring 4 as shown in FIG. The amount of Ar incident on the tapered portion 9 during the sputter etching is larger than that on the side wall portion 8 in FIG. However, even in this case, a sufficiently low contact resistance may not be obtained. For example, when the lower layer wiring 4 is a nail-shaped plug as shown in FIG. This has an effect in both the vertical and horizontal directions, and in the worst case, the contact area is further reduced and the contact resistance is increased.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device having stable characteristics by reducing the contact resistance between upper and lower wirings.

[0009]

In a semiconductor device according to the present invention, the first wiring layer has a taper portion extending inside the first via hole, and the second via hole has a second insulating film. Is formed so as to penetrate into the first insulating film and reach the inside of the first insulating film.

Further, a third insulating film made of a material different from that of the second insulating film is formed between the first insulating film and the second insulating film. Furthermore, the first wiring layer has a structure that is a plug having a head.

Further, in the method of manufacturing a semiconductor device according to the present invention, the step of forming the first wiring layer having the tapered portion extending inside the first via hole and the step of penetrating the second insulating film are performed. And a step of forming a second via hole reaching the inside of the first insulating film.

Further, a step of forming a third insulating film made of a material different from that of the second insulating film on the first insulating film, and a first step having a tapered portion extending inside the first via hole The method includes a step of forming a wiring layer and a step of penetrating the second insulating film and forming a second via hole reaching the first insulating film by using the third insulating film as an etching mask.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. 1 and 2 show a manufacturing process of a semiconductor device according to a first embodiment of the present invention. The process shown in FIG. 2 is carried out subsequent to FIG. In these figures, 1 is a semiconductor substrate, 2 is a first insulating film formed on the semiconductor substrate 1, 11 is a first wiring layer formed on the first insulating film 2, and 12 is a first insulating film. The taper portion 5 formed on the wiring layer 11 is a second insulating film formed on the first wiring layer 11, and 13 is a second wiring layer formed on the second insulating film 5.

First, as shown in FIG. 1A, a first insulating film 2 is formed on a semiconductor substrate 1 by a CVD method or the like to a thickness of 1 μm, for example, a silicon oxide film, and then a first plate is formed by photolithography and dry etching. A first via hole 3 is formed in the first insulating film 2. Next, as shown in (b), the first via hole 3 is filled with the aluminum (Al) alloy or the like by the sputtering method or the CVD method and the first insulating film 2 is formed.
A first conductive film 14 having a thickness of 500 nm, for example, is formed thereon. Then, a resist mask 15 is formed thereon by photolithography. At this time, misalignment occurs between the via hole 3 and the resist mask 15.

Next, FIGS. 1C, 1D and 2A.
As shown in FIG. 5, the first conductive film 14 is patterned using the resist mask 15 to form the first wiring layer 11. The taper portion 12 is formed in the first wiring layer 11 by appropriately selecting the etching conditions at this time.
That is, when etching with a certain selection ratio between the resist mask 15 and the first conductive film 14 is performed, FIG.
From (d) to (d), the surface of the first conductive film 14 is removed, and at the same time, the resist mask 15 also becomes thinner. Therefore, the resist mask 15 of the first conductive film 14 is reduced.
A slanted portion is formed from the portion in contact with the end surface.

The first conductive film 1 on the surface of the first insulating film 2
Etching is continued even after all 4 are removed, as shown in FIG.
As shown in FIG. 5, a part of the Al alloy in the first via hole 3 is etched. When the etching is completed, the resist mask 15 is removed. As described above, the tapered portion 12 extending from above the first insulating film 2 into the inside of the first via hole 3 is formed.
Is formed. Tapered portion 1 from the surface of the first insulating film 2
The depth d of 2 is 200 nm, for example. Tapered part 12
The inclination angle of the resist mask 15 and the first conductive film 1 is
It can be adjusted by changing the etching selection ratio with respect to 4. Further, Japanese Patent Laid-Open No. 7-283319 also discloses a method of forming a tapered portion on a wiring.

Next, a second insulating film 5 is formed on the entire surface of these by a CVD method or the like with a thickness of 1 μm, for example, a silicon oxide film. Then, a second via hole 16 is formed in the second insulating film 5 on the first via hole 3 by a combination of photolithography and etching, as shown in FIG. . The second via hole 16 is formed by penetrating the second insulating film 5 and further etching a part of the first insulating film 2. The depth from the surface of the first insulating film 2 is, for example, 200 nm, which is the same as d shown in FIG. As a result, the tapered portion 12 of the first wiring layer 11 formed so as to extend into the first via hole 3 is exposed.

Next, by CVD or sputtering, A
a second conductive film having a thickness of, for example, 500 nm is formed on the second insulating film 5 by burying the second via hole 16 with an alloy of 1 or the like, and patterned by photolithography and etching. A second wiring layer 13 is formed as shown in 2 (c).

Since the first wiring layer 11 is etched up to the inside of the first via hole 3 as described above, the taper portion 1 is formed.
2 is large, and in this embodiment, the depth d of the tapered portion 12 from the first insulating film 2 is 200 nm with respect to the film thickness of the first wiring layer 11 of 500 nm.
The area of the taper portion 12 is 40% compared to when d is zero.
Increase. By controlling the etching amount when forming the tapered portion 12, the area of the tapered portion 12 can be controlled and the contact resistance can be adjusted.

In the above embodiment, the resist mask 1 is used.
The tapered portion 12 was formed while etching 5
When the resist mask 15 is formed by photolithography, the focus may be shifted so that the resist itself has a tapered shape and etching is performed. Also, as shown in FIG.
There may be another lower layer wiring 17 under the first wiring layer 11. Another insulating film 18 is formed on the semiconductor substrate 1, and the lower layer wiring 17 is formed thereon by a usual method.

Embodiment 2 FIG. In the first embodiment, part of the first insulating film 2 is etched when the second via hole 16 is formed. At this time, for example, when the etching amount of the first insulating film 2 is large and there is another lower layer wiring 17 further below the first wiring layer 11 and the wiring interval is narrow, the wirings are unnecessarily short-circuited. It may happen. A method for solving this problem will be shown below with reference to FIG.

First, a first insulating film 2 is formed on the semiconductor substrate 1 by a CVD method or the like to have a thickness of 1 μm, for example, of a silicon oxide film, and a third insulating film 19 is formed thereon by a CVD method or the like to be described later. The insulating film 5 is made of a different material, for example, a silicon nitride film having a thickness of 50 to 100 nm. Next, as shown in FIG. 5A, the first via hole 3 penetrating the third insulating film 19 and the first insulating film 2 is formed by a combination of photolithography and dry etching. Then, FIG. 1 (b)-
In the same manner as in (d) and FIG. 2 (a), the first wiring layer 11
To form The tapered portion 12 is formed in the first wiring layer 11, and the depth from the surface of the third insulating film 19 is, eg, 200 nm.

Next, a second insulating film 5 of, eg, a silicon oxide film having a thickness of 1 μm is formed on the entire surface by CVD or the like. At this time, the first in the first via hole 3
After the wiring layer 11 is etched, the gap is filled with the second insulating film 5. Then, as shown in FIG. 2C, a second via hole 16 is formed in the second insulating film 5 on the first via hole 3 by a combination of photolithography and etching. At this time, misalignment occurs. .

First, the second insulating film 5 is etched until the surface of the third insulating film 19 is exposed, and then the third insulating film 19 is used as a mask to selectively further etch the film by 200 nm. First wiring layer 1 in first via hole 3
It is a silicon oxide film that fills the area after etching 1 and the third insulating film 19 is a silicon nitride film. In contrast, since the materials are different from each other, one silicon oxide film is selected. Can be selectively etched. In this way, the tapered portion 12 is exposed up to the portion inside the first via hole 3.

Next, as in the case of the first embodiment, as shown in FIG. 2D, the second wiring layer 13 is formed.
As described above, since the portions directly below the second via hole 16 and inside the first via hole 3 are not etched, the problem as shown in FIG. 4 does not occur.

In the first and second embodiments, the first wiring layer 11 has been described as a general one, but the first wiring layer 11 projects onto the first insulating film 2. In the case of a plug having a curved head, that is, in the case where the plug does not extend in any direction in a plane like the lower layer wiring 4 in FIG. .

[0027]

According to the semiconductor device and the method of manufacturing the same of the present invention, since the first wiring layer has the tapered portion extending inside the first via hole, the area of the tapered portion increases, Therefore, the contact resistance can be reduced, and a semiconductor device having stable characteristics can be obtained.

The third insulating film made of a material different from that of the second insulating film is used.
Since the insulating film of 1 is formed, it is possible to prevent a short circuit between wiring layers lower than the first wiring layer. Also, the first
If the wiring layer is a plug having a head portion, the misalignment in the two directions is improved, so that the contact resistance can be lowered.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process for a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram of a semiconductor device according to a first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a manufacturing process that follows.

FIG. 3 is a sectional view showing another semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view of the semiconductor device showing a case where a problem occurs in the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a sectional view showing a conventional semiconductor device.

FIG. 7 is a cross-sectional view showing another conventional semiconductor device.

FIG. 8 is a plan view showing another conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 semiconductor substrate, 2 1st insulating film, 3 1st via hole, 5 2nd insulating film, 11 1st wiring layer, 12
Tapered portion, 13 second wiring layer, 14 first conductive film, 16 second via hole, 19 third insulating film.

Claims (5)

[Claims] 1. A first insulating film formed on a substrate, and a first wiring formed on the first insulating film and filling a first via hole formed in the first insulating film. Layers and
A second insulating film formed on the first wiring layer and a second insulating film formed on the second insulating film and formed on the second insulating film on the first via hole. In a semiconductor device having a second wiring layer for filling a via hole,
The first wiring layer has a taper portion extending from above the first insulating film into the inside of the first via hole, and the second via hole penetrates through the second insulating film. A semiconductor device, wherein the second wiring layer is formed so as to reach the inside of the first insulating film, and the second wiring layer is electrically connected to the first wiring layer at the tapered portion. 2. A third insulating film made of a material different from that of the second insulating film is formed between the first insulating film and the second insulating film. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the first wiring layer is a plug having a head portion projecting above the first insulating film. 4. A step of forming a first insulating film on a semiconductor substrate, a step of forming a first via hole in the first insulating film, and a step of forming the first insulating film on the first insulating film. A step of forming a first conductive film filling the via hole; and a step of patterning the first conductive film to extend from above the first insulating film into the inside of the first via hole. A step of forming a first wiring layer, a step of forming a second insulating film on the first wiring layer, and a step of penetrating the second insulating film on the first via hole and Forming a second via hole reaching the inside of the first insulating film; forming a second conductive film on the second insulating film to fill the second via hole; A step of patterning a conductive film to form a second wiring layer Manufacturing method. 5. A step of forming a first insulating film on a semiconductor substrate, a step of forming a third insulating film on the first insulating film, and the first insulating film and the third insulating film. Forming a first via hole in the film, forming a first conductive film on the third insulating film to fill the first via hole, and patterning the first conductive film And forming a first wiring layer having a tapered portion extending from the first insulating film to the inside of the first via hole; and the third conductive layer on the first wiring layer. A step of forming a second insulating film made of a material different from that of the film, and a step of penetrating the second insulating film on the first via hole and using the third insulating film as an etching mask. Forming a second via hole reaching the inside of the insulating film; Forming a second conductive film on the edge film to fill the second via hole;
And a step of forming a second wiring layer by patterning the conductive film of 1.