JPH08316806A - Signal contention circuit - Google Patents

Abstract

PURPOSE: To avoid a duplicated valid level of plural signals. CONSTITUTION: With signals DREQ, RESET received at an H level, a flip-flop 11 latches the H level of the signal DREQ synchronously with a clock signal CK. A flip-flop 12 latches the H level of the signal RESET synchronously with a clock signal CKN inverted to the clock signal CK. Succeedingly a flip-flop 13 latches the H level latched by the flip-flop 11 synchronously with the clock signal CKP to provide an output of the signal BREQ of the H level. In this case, a level of an inverted output terminal NQ of the flip-flop 13 is at L and a flip-flop 14 is reset. As a result, an output signal rst of the flip-flop 14 is guarded to be L.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal competing circuit provided in a data transmitting / receiving circuit of a circuit switch and a packet switch.

[0002]

2. Description of the Related Art FIG. 2 is a configuration block diagram showing a conventional data transmitting / receiving circuit. This data transmission / reception circuit includes a central processing unit (hereinafter, CPU) 1 and, for example, two integrated circuits (hereinafter, LSI) 2 and 3 having a direct memory access (hereinafter, DMA) function. I have it. CPU1 and LSI2
A bus request / select circuit 4 is provided between 3 and 3. When it is desired to perform a DMA operation on a memory (not shown), the LSIs 2 and 3 enable the bus request select circuit 4 by validating the level of the DMA request signal DREQ to occupy the bus. When the bus request / select circuit 4 detects that the signal DREQ is valid, the bus request / select circuit 4 validates the level of the hold request signal HREQ and supplies it to the CPU 1 to request the suspension of the function of the CPU 1. The CPU 1 detects the signal HREQ indicating validity, validates the hold acknowledge signal HACK, and outputs it to the bus request select circuit 4. This releases the bus. After that, the bus request / select circuit 4 validates and returns the DMA acknowledge signal DACK to the one having the highest priority among the LSIs 2 and 3, and the DM
A LSI2 or LSI3 that received A acknowledge signal DACK
Performs DMA operation.

[0003]

However, the conventional information processing system has the following problems. CP
From U1, the activated individual reset signal is sent to each LSI2.
When resetting the LSIs 2 and 3, respectively, and resetting the LSIs 2 and 3, the valid periods of the signal DREQ and the individual reset signal may overlap. If they overlap,
In LSIs 2 and 3, before the signal DACK becomes valid, the signal DR
Clear the EQ. In this case, the CPU 1 that has input the valid signal HREQ validates the signal HACK, so
1 and LSIs 2 and 3 are locked without operating together.

[0004]

According to a first aspect of the invention, in order to solve the above-mentioned problems, a signal competing circuit has the following configuration. That is, the signal competing circuit of the first invention is
A first flip-flop that latches the level of a first input signal that takes a binary value of a valid level or an invalid level in synchronization with a first clock signal, and a second input that takes a binary value of the valid level or an invalid level A second flip-flop for latching a signal level in synchronization with a second clock signal having a phase opposite to that of the first clock signal; and a latched level of the first flip-flop for the first clock signal A third output which outputs a first output signal by latching in synchronization with
And a fourth flip-flop that outputs the second output signal by latching the latched level of the second flip-flop in synchronization with the second clock signal. The third flip-flop is configured to be reset to set the first output signal to the invalid level when the second output signal is at the valid level, and the fourth flip-flop is configured to be the first flip-flop. Is reset when the output signal of
The output signal of is set to an invalid level.

A second invention has a frequency divider for dividing one reference clock signal, and a plurality of dividers having the same cycle and different phases based on the reference clock signal and the divided clock signal. Generating a control clock signal, and a plurality of first flip-flops for respectively latching the levels of a plurality of input signals, each of which takes a binary value of a valid level or an invalid level, in synchronization with the control clock signal. And a plurality of second flip-flops for latching the latched level of each of the first flip-flops in synchronization with each of the control clock signals and transmitting the output signals, respectively. Each of the second flip-flops is reset to set the output signal to an invalid level when there is one of the other second flip-flops that outputs an effective level.

[0006]

According to the first aspect of the invention, since the signal competing circuit is configured as described above, when only the first input signal becomes the effective level, the first clock signal is synchronized with the first clock signal. The valid level of the input signal is latched in the first flip-flop. The latched level of the first flip-flop is latched by the third flip-flop in synchronization with the first clock signal, and the effective level is output from the third flip-flop. In this state, the fourth flip-flop is reset and outputs an invalid level regardless of the level of the second input signal. Similarly, when only the second input signal becomes the valid level, the fourth flip-flop outputs the valid level and the third flip-flop outputs the invalid level. The latches in the first and third flip-flops are synchronized with the first clock signal, and the latches in the second and fourth flip-flops are synchronized with the second clock signal. Therefore, even if the first and second input signals simultaneously become effective levels,
The timings at which the effective levels of the first and second input signals are latched are different. Therefore, only one of the third and fourth flip-flops outputs the effective level.

According to the second invention, one reference clock signal is divided by the divider in the clock generation circuit. Then, the clock generation circuit generates a plurality of control clock signals having the same cycle and different phases based on the reference clock signal and the divided clock signal. The plurality of first flip-flops latch the level of each input signal in synchronization with each control clock signal. The level latched by each of the first flip-flops is latched by the plurality of second flip-flops in synchronization with each control clock signal.
For example, when one input signal is at the effective level, the second flip-flop latching the level of the input signal outputs the effective level. The other second flip-flop is reset and outputs an invalid level. 2 at the same time
Even when one or more input signals reach the effective level, each of the first and second flip-flops latches them at different timing according to each control clock signal. Therefore, only the second flip-flop that latches the valid level first outputs the valid level, and the other second flip-flops output the invalid level. Therefore, the above problem can be solved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a signal competing circuit showing a first embodiment of the present invention. This signal competing circuit 10 corresponds to each LSI of FIG.
It is provided corresponding to each of 2 and 3, and the first
First flip-flop (F / F) for inputting the DMA request signal DREQ, which is an input signal of, to the data input terminal D
11 and a second flip-flop 12 for inputting the individual reset signal RESET of the second input signal to the data input terminal D
It has and. The first clock signal CKP is input to the clock terminal of the flip-flop 11, and the data output terminal Q of the flip-flop 11 is connected to the data input terminal D of the third flip-flop 13. The clock signal CKP is applied to the clock terminal of the flip-flop 12.
The second clock signal CKN having a phase opposite to that of is input, and the data output terminal Q of the flip-flop 12 is connected to the data input terminal D of the fourth flip-flop 14.
The clock signal CKN can be generated with respect to the clock signal CKP by using, for example, an inverter (not shown).

The clock signal CKP is input to the clock terminal of the flip-flop l3, and the clock signal CKN is input to the clock terminal of the flip-flop l4. The bus request signal BREQ of the first output signal is output from the positive-phase output terminal Q of the flip-flop 13, and the negative-phase output terminal NQ of the flip-flop 13 is output.
The output from the flip-flop 1 is inverted in level.
4 is input to the reset terminal R. The reset signal rst of the second output signal to each of the LSIs 2 and 3 is output from the positive-phase output terminal Q of the flip-flop 14, and the negative-phase output terminal N of the flip-flop 14 is output.
The output from Q is inverted in level and input to the reset terminal R of the flip-flop 13. That is,
In this signal competing circuit 10, the level of the signal DREQ is latched by the flip-flop 11 in synchronization with the clock signal CK, and the output of the flip-flop 11 is the clock signal.
It is latched by the flip-flop 13 in synchronization with CKP. On the other hand, the signal RESET is latched in the flip-flop 12 in synchronization with the clock signal CKN, and the output of the flip-flop 12 is latched in the flip-flop 14 in synchronization with the clock signal CKN. Each flip-flop 1
The levels of the latched signals 3 and 14 are the signal BREQ and the signal
The configuration is such that each is output as rst.

FIG. 3 is a diagram showing the data transmitting / receiving circuit of FIG. 2 in which the signal competing circuit of FIG. 1 is incorporated. The data transmission / reception circuit includes a CPU 1, two LSIs 2 and 3 having a DMA function, and a bus request / select circuit 4 connected between the CPU 1 and the LSIs 2 and 3. CPU1, each LSI2, 3 and bus request
Two signal competing circuits 10-2 and 10-3 respectively corresponding to the LSIs 2 and 3 are provided between the select circuit 4 and the selection circuit 4.
A reset circuit 20 for generating individual reset signals RESET2 and RESET3 for resetting the LSIs 2 and 3 based on an instruction from the PU 1 is provided. The DMA request signal DREQ2 output from the LSI 2 and the individual reset signal RESET2 output from the reset circuit 20 are
-2, the signal competing circuit 10-2 supplies the bus request signal BREQ2,
And the reset signal rst2 is supplied to the LSI2. DMA request signal DREQ output from LSI3
3 and the individual reset signal RESE output from the reset circuit 20
T3 is input to the signal contention circuit 10-3, and the signal contention circuit 10-3 inputs the bus request signal BREQ3 to the bus request / select circuit 4 and the reset signal rs to the LSI 3.
It is connected to supply t3. The bus request / select circuit 4 gives a hold request signal HREQ to the CPU 1, and the CPU 1 returns a hold acknowledge signal HACK to the bus request / select circuit 4. Also, bus request select circuit 4
However, DMA acknowledge signal DACK for each LSI2, 3
2 and DACK3 are returned respectively.

FIGS. 4 and 5 are time charts (Nos. 1 and 2) for explaining the competition in FIG. 1. With reference to FIGS. 4 and 5, the operation of the signal competition circuit of FIG. 1 and FIG.
The operation of the data transmission / reception circuit will be described. When performing a DMA operation for each memory (not shown), each LSI
Since 2 and 3 occupy the bus, the respective DMA request signals DREQ2 and DREQ3 are set to the effective level "H" and are given to the signal competing circuits 10-2 and 10-3. On the other hand, CP
When U1 resets the LSIs 2 and 3, the reset circuit 20 resets the individual reset signals RESET2 and RESE.
The signal competing circuit 10-
2 and 10-3 respectively. Each signal competing circuit 10-
In 2 and 10-3, the signals BREQ2 and BREQ3 corresponding to the levels of the signals DREQ2 and DREQ3 and the signals rst2 and rst3 corresponding to the levels of the signals RESET2 and RESET3 are transmitted, respectively. The operations of the signal contention circuits 10-2 and 10-3 are the same, and the operation of the signal contention circuit 10-2 will be described here.

For example, when the signal DREQ2 is at the effective level "H" and the signal RESET2 is at the ineffective level "L",
The flip-flop 11 latches "H" of the signal DREQ2, and the flip-flop 13 latches the level of the signal latched by the flip-flop 11. That is, the signal BREQ becomes the effective level "H". In this state, even if the signal RESET2 changes to the effective level of "H", the flip-flop 1
Since 4 is reset by the flip-flop 13, the signal rst2 output from the flip-flop 14 is guarded at the invalid level "L". Conversely, the signal DREQ
When 2 is the invalid level “L” and the signal RESET2 is the valid level “H”, the flip-flop 12 outputs the signal RESET2.
, "H", and the flip-flop 14 latches the level latched by the flip-flop 12. That is,
The signal rst2 becomes the effective level "H". In this state, even if the signal DREQ2 changes to the effective level "H", the flip-flop 13 is reset by the flip-flop 14, so the signal output from the flip-flop 13
BREQ2 is a signal that is guarded with the invalid level "L"
The levels of DREQ2 and signal RESET2 become H "at the same time and Fig. 4
Is given at the timing of. Signal competition circuit 10-
When the "H" signal DREQ2 is input to 2, the flip-flop 11 latches the level "H" of the signal DREQ2 in synchronization with the clock signal CKP. Flip-flop 12
Latches "H" of the signal RESET2 in synchronism with the clock signal CKN with a delay of a half cycle with respect to the flip-flop 11. Then, the flip-flop 13 outputs the clock signal CK.
In synchronization with P, the output level "H" of the flip-flop 11 is latched. At this point, flip-flop 1
The level of the output signal BREQ2 of 3 becomes "H", and the flip-flop 14 is reset. That is, the signal DREQ2 wins the signal RESET2 in competition, and the level of the signal rst2 output from the flip-flop 14 is guarded at the invalid level "L".

Next, the case where the signal RESET2 wins the signal DREQ2 by competition will be described. It is assumed that the levels of the signal DREQ2 and the signal RESET2 become H ”at the same time and are given at the timing of FIG. 5. When the signal RESET2 of“ H ”is input to the signal competing circuit 10-2, the flip-flop 12 operates as Signal CK
The level “H” of the signal RESET2 is latched in synchronization with N. The flip-flop 11 is delayed by a half cycle from the flip-flop 12 and is synchronized with the clock signal CKP to generate the signal DREQ2.
L level of "H" is latched. Then the clock signal
The flip-flop 14 latches the output level “H” of the flip-flop 12 in synchronization with CKN. At this time, the level of the output signal rst2 of the flip-flop 14 becomes "H", and the flip-flop 13 is reset. That is, the signal RESET2 wins the signal DREQ2 in competition, and the level of the signal BREQ2 output from the flip-flop 13 is guarded at the invalid level "L".

DMA request signal DREQ2 or DREQ3
However, when the circuit of FIG. 1 wins the competition, a valid level “H” is given to the bus request / select circuit 4, and the bus request / select circuit 4 prompts the CPU 1 to stop the temporary operation. Then, a valid level hold request signal HREQ is given. The CPU 1 releases the bus and returns a hold acknowledge signal HACK to the bus request / select circuit 4, and the bus request / select circuit 4 returns a DMA acknowledge signal DACK2 or DACK3 to each LSI 2 or 3. This allows the LSI
2 or LSI3 DMAs to a memory (not shown)
Take action. On the other hand, in the circuit of FIG. 1, the signal RESET2,
If RESET3 wins the signal DREQ2 or DREQ3 in competition,
High level signals rst2 and rst3 of effective level for each LSI 2 and 3
Is entered. Here, the signal level lost by competition is
If the CPU 1 or the LSIs 2 and 3 are kept valid, the signal of the losing party is processed after the sequence of the signals that won the competition is completed.

As described above, in the first embodiment, the flip-flop 1 for latching the level of the input signal DREQ in the signal competing circuit 10 in synchronization with the clock signal CKP.
1, a flip-flop 12 that latches the level of the signal RESET in synchronization with the clock signal CKN, and a flip-flop 13 that latches the level of the signal latched by the flip-flop 11 in synchronization with the clock signal CKP and sends out the signal BREQ. , And the flip-flop 14 which latches the level of the signal latched by the flip-flop 12 in synchronization with the clock signal CKN and sends out the signal RST. And
The flip-flop 13 is reset when the flip-flop 14 outputs a valid level, and the flip-flop 14 is reset when the flip-flop 13 outputs a valid level. Therefore, the signal DREQ and the signal RESET do not overlap as in the conventional case, and the lock failure in the CPU 1 and the LSIs 2 and 3 can be avoided.

Second Embodiment FIG. 6 is a circuit diagram of a signal competing circuit showing a second embodiment of the present invention. The signal competing circuit of this embodiment has four first flip-flops 31, 3 for inputting four input signals S1, S2, S3, S4 to respective data input terminals D.
2, 33, 34 are provided. Each flip-flop 31
The output terminals Q of -34 are connected to the data input terminals D of the four second flip-flops 41-44, respectively. The signal competing circuit has a function of generating output signals S41 to S44 which respectively correspond to the input signals S1 to S4 and do not simultaneously take an effective level and are positive phase signals of the flip-flops 41 to 44. Output terminal Q
From these four output signals S41, S42, S43,
S44 is the configuration to be output respectively. Further, the reset terminals R of the respective flip-flops 41 to 44 are connected so that the levels of the negative-phase output terminals NQ of the other flip-flops 41 to 44 are inverted and input. That is, to the reset terminal R of the flip-flop 41, the output signal of the 3-input AND gate 45, which receives the levels of the negative-phase output terminals NQ of the other flip-flops 42 to 44, is inverted and input. The reset terminal R of the flip-flop 42 is a 3-input AND in which the levels of the negative-phase output terminals NQ of the other flip-flops 41, 43, 44 are input.
The connection is such that the output signal of the gate 46 is inverted and input. The reset terminal of the flip-flop 43 is connected to the negative-phase output terminals NQ of the other flip-flops 41, 42 and 44.
The connection is such that the output signal of the 3-input AND gate 47 which receives the level of is input is inverted and input. The reset terminal R of the flip-flop 44 is connected to another flip-flop 4
Input the level of each negative-phase output terminal NQ 1 to 43 3
The connection is such that the output signal of the input AND gate 48 is inverted and input. On the other hand, the four control clocks CK1 to CK4 generated by the clock generation circuit 50 are input to the clock terminals of the respective flip-flops 31 to 34, and the control terminals CK1 to CK4 are also input to the clock terminals of the respective flip-flops 41 to 44. CK4 is input respectively.

FIG. 7 is a circuit diagram showing the clock generation circuit in FIG. The clock generation circuit 50 has a function of generating four control clock signals CK1, CK2, CK3, CK4 having the same cycle and different phases, and divides one reference clock signal CK by two. Frequency divider 51 and four 2-input AND gates 52 to 5 for sending out control clock signals CK1, CK2, CK3, and CK4, respectively.
5 is provided. The frequency divider 51 is a flip-flop 51a
It is formed with. The reference clock signal CK is input to the clock terminal of the flip-flop 51a, and the negative phase output terminal NQ of the flip-flop 51a is connected to the data input terminal D of the flip-flop 51a. AND
The input terminal of the gate 52 is a connection to which the level of the positive phase output terminal Q of the flip-flop 51a and the clock signal CK are input. The input terminal of the AND gate 53 is a connection to which the level of the positive phase output terminal Q of the flip-flop 51a and the clock signal CK inverted by the inverter 56 are input. An inverter 57 is connected to the input terminal of the AND gate 54.
Positive-phase output terminal Q of the flip-flop 51a inverted by
And the clock signal CK are input.
The input terminal of the AND gate 55 is connected so that the level of the positive phase output terminal Q of the flip-flop 51a inverted by the inverter 58 and the clock signal CK inverted by the inverter 59 are input.

FIG. 8 is a time chart showing the control clock signal generated by the clock generating circuit of FIG. 7. The operation of the signal competing circuit of FIG. 6 will be described with reference to FIG. In the clock generation circuit 50, the reference clock signal CK is divided by 2 by the flip-flop 51a as shown in FIG. The AND gates 52 to 55 output control clock signals CK1 to CK4, which have the same period and are out of phase with each other, and the respective control clock signals CK1 to CK4 output the flip-flops 31 to 34 and the flip-flops in FIG. Is supplied to each of the groups 41 to 44. For example, of the input signals S1 to S4 that were at the invalid level, the input signal S1
Is changed to an effective level of "H", the flip-flop 31 synchronizes with the control clock signal CK1 and receives the input signal S1.
Latch "H". Then, the flip-flop 41
Latches "H" latched by the flip-flop 31. Therefore, the positive-phase output terminal Q of the flip-flop 41 outputs the output signal S41 of "H". In this state, since "L" is output from the negative-phase output terminal NQ of the flip-flop 41, the flip-flop 42
To 44 are reset, and even if the other input signals S2 to S4 become the effective level "H", the output signals S42 to S4 are output.
The 4th level is guarded and maintains the invalid level "L". Similarly, when the input signal S2, S3 or S4 first becomes "H", one output signal S42, S4
3, or only S44 becomes the valid level "H", and the others become invalid level "L".

Further, for example, when the input signals S1 to S4 are simultaneously set to the effective level "H", the control clock signals CK1 to CK4 are out of phase with each other, so that the flip-flops 31 to 34 and the flip-flops 31 to 34 are not in phase with each other. Flip-flops 41 to
The latch timing at 44 is different. Therefore, of the flip-flops 41 to 44, the first “H”
Only those that have latched are output valid level "H", and others are guarded and output invalid level "L".
That is, two or more signals do not reach the effective level. As described above, in the second embodiment, the clock generation circuit 5
0 is equipped with a frequency divider 51 to divide the reference clock signal CK,
The control clock signals CK1 to CK4 having the same cycle and different phases are generated. Then, the levels of the respective input signals S1 to S4 are set to those control clock signals CK1 to CK.
Flip-flop 31 that latches in synchronization with 4
To 34 and flip-flops 41 to 44 for latching the levels of the signals latched by the flip-flops 31 to 34 in synchronization with the control clock signals CK1 to CK4, respectively. When there is one of the two flip-flops that outputs the valid level, the flip-flop is reset to set the output signal to the invalid level. Therefore, the four input signals S1 to S4 can compete with each other with a simple configuration.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the first embodiment, the competition between the bus request signal BREQ and the reset signal rst has been described, but the invention can be applied to the competition for the access right to the common memory and the competition between other arbitrary signals. it can. (2) In the second embodiment, four input signals S1 to S4
However, if the frequency division in the frequency divider 51 is not divided by 2 but divided by 3, divided by 4, etc., the number of competing input signals is increased to 6, 8. Is possible. (3) In the second embodiment, in the clock generation circuit 50,
Generates the control clock signals CK1 to CK4 and inputs the input signal S1.
Although the configuration is such that the competition of S4 to S4 is performed, it is not necessary to use all the control clock signals. For example, three input signals S
When competing for 1 to S3, control clocks CK1 to CK
You can use 3.

[0021]

As described in detail above, according to the first invention, the first flip-flop for latching the level of the first input signal in synchronization with the first clock signal, and the second flip-flop are provided. A second flip-flop that latches the level of the input signal in synchronization with a second clock signal having a phase opposite to that of the first clock signal, and the latched level of the first flip-flop is synchronized with the first clock signal And then latch third
And a fourth flip-flop that latches the latched level of the second flip-flop in synchronization with the second clock signal, and the third flip-flop outputs the second output signal. The fourth flip-flop is configured to be reset when it is at the valid level, and the fourth flip-flop is reset when the first output signal is at the valid level. Therefore, even if the levels of the first and second input signals are both valid levels, only one of the first and second output signals becomes the valid level.

According to the second invention, a clock generating circuit having a frequency divider for dividing one reference clock signal and generating a plurality of control clock signals having the same cycle and different phases from each other, A plurality of first flip-flops that respectively latch the levels of a plurality of input signals in synchronization with the respective control clock signals, and a latched level of each first flip-flop in synchronization with the respective control clock signals. A plurality of second flip-flops, each second flip-flop being reset when there is one of the other second flip-flops outputting a valid level and invalidating the output signal. It is configured to be a level. Therefore, even if two or more input signals become effective levels, only one output signal becomes effective level.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a signal competing circuit showing a first embodiment of the present invention.

FIG. 2 is a configuration block diagram showing a conventional data transmission / reception circuit.

3 is a diagram showing the data transmitting / receiving circuit of FIG. 2 in which the signal competing circuit of FIG. 1 is incorporated.

FIG. 4 is a time chart (No. 1) for explaining the competition in FIG.

5 is a time chart (No. 2) for explaining the competition in FIG. 1. FIG.

FIG. 6 is a circuit diagram of a signal competing circuit showing a second embodiment of the present invention.

7 is a circuit diagram showing a clock generation circuit in FIG.

FIG. 8 is a time chart showing a control clock signal generated by the clock generation circuit of FIG.

[Explanation of symbols]

10, 10-2, 10-3 signal competing circuit 11 first flip-flop 12 second flip-flop 13 third flip-flop 14 fourth flip-flop 31 to 34 first flip-flop 41 to 44 second Flip-flop 50 Clock generation circuit 51 Frequency divider CKP, CKN First and second clock signals CK Reference clock signal CK1 to CK4 Control clock signal DREQ, RESET S1 to S4 Input signal BREQ, rst, S41 to S44 Output signal

Claims (2)

[Claims] 1. A first flip-flop that latches the level of a first input signal that takes a binary value of a valid level or an invalid level in synchronization with a first clock signal, and a binary value of a valid level or an invalid level. The level of the second input signal is set to the phase of the second clock having a phase opposite to that of the first clock signal.
A second flip-flop that latches in synchronization with the first clock signal, and a third flip-flop that latches the latched level of the first flip-flop in synchronization with the first clock signal and outputs a first output signal. A third flip-flop; a flip-flop, and a fourth flip-flop that latches the latched level of the second flip-flop in synchronization with the second clock signal and sends out a second output signal. Is configured to reset the first output signal to an invalid level when the second output signal is at a valid level, and the fourth flip-flop is configured to set when the first output signal is at a valid level. Is reset to set the second output signal to an invalid level, the signal competing circuit. 2. A plurality of control clock signals having a frequency divider for dividing one reference clock signal, having the same period based on the reference clock signal and the divided clock signal, and having different phases from each other. And a plurality of first flip-flops for respectively latching the levels of a plurality of input signals, each of which takes a binary value of a valid level or an invalid level, in synchronization with each of the control clock signals, and A plurality of second flip-flops for latching the latched level of the first flip-flops in synchronization with the respective control clock signals and sending output signals, respectively. If any of the second flip-flops outputs an effective level, it is reset to set the output signal to an invalid level. A signal competing circuit characterized by the above.