JPH01233849A - Timing system - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution by providing two or more latch circuits on a bit synchronizing circuit and a means inverting the phase of a latch clock signal when a coincidence detection circuit detects the discordance of an input signal. CONSTITUTION:A coincidence detection circuit decides the coincidence of outputs of two latch circuits 103, 104 at all times and if discordance is detected even once, the leading edge of the output of an EX-OR gate 108 is judged to be in the vicinity of a change point of a data input 1011 to invert automatically the phase of the output of the EX-OR gate 108 and the inverted clock signal is used afterward to identify the data input 1011. Since the leading edge of the inverted clock appears at a time when the data input 1011 is made stable to be a prescribed state, the clock signal is used to attain retiming of the data signal without any error. Thus, a data signal having two kinds of phases of 0 and pi phase is supplied to a latch circuit 114 inputting the output of bit aligners 1101-110n.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a timing system % type % used in digital transmission systems such as backbone transmission systems, public networks, subscriber systems, etc. [Prior Art] FIG. 1 is a circuit diagram showing a configuration example of a conventional timing method used in a digital transmission system.

In the figure, 4011 to 401° are data input lines, and 40
2 is a clock input line, 403 is a circuit, 404 is a selector circuit, 405 is a control signal input line, 4061 to 40
63 is a gate, 4071 to 407o are data output lines, 4
08 is a clock output line. ζClock input 44 here
Clock signal input from 02 and data input line 401
The data signals input from the data input lines 401! to 401n have the same repeat synchronization (To=1/f o), but generally the data signals input from the data input lines 401! Between the data signals input from 401. to 401n, the data input line 401. The phase synchronization between the data signal input from ~401° and the clock signal input from the clock input 6402 is not necessarily achieved.For this reason, the n data signals are immediately input using this clock signal 402. Cannot be retimed. Therefore, this input clock signal 402 is converted into clock signal 406 . 4063 to produce a four-phase clock signal. The selector circuit 404 which receives the generated four-phase clock signals as input selects one phase clock signal from the four-phase clock signals based on the control signal input from the control signal input line 405. Using this selected clock signal, the latch circuit 403 connects the n data input lines 4011 to 40
The data signal input from 10 is identified and retimed. In this way, in the circuit shown in FIG. 4, it is possible to select one phase from the Fi four-phase clock signals as the clock signal used for retiming, so even if the clock signal input from the clock input line 402 and n Even if the data signals input from the book data inputs m401t to 401n are not phase synchronized, these data signals can be retimed without error.

[Problem to be solved by the invention]

In the timing scheme shown in FIG. 4, 406. Since a four-phase clock signal is generated by a non-logical operation using ~406fl, and one phase is selected from these four-phase clock signals to perform the timing of n data signals, the gates 4061~406
The gate delay amount of n is an important factor in determining the data signal timing, and the gate delay amount had to be adjusted depending on the repetition frequency (fo) of the input data. Data signals input from the n data input lines 4011 to 401a include skew (phase distortion) between data and delay variations between signals. For this purpose, the clock number 100 selected by the selector circuit 404 is applied to all n data input lines 40.
11 to 4010 could not always be identified under optimal phase conditions.

In addition, after selecting the optimal phase clock for the information of each data input line and identifying the information for each signal line,
N data input! A method of retiming information between 401 and 401fi using a common clock signal to ensure parallel bit synchronization may also be considered. However, in this method, phase control of the common lock for achieving parallel bit synchronization is complicated.

An object of the present invention is to provide a simple circuit configuration that solves these problems, does not generate a clock signal for data timing by non-logical operations, does not depend on the repetition frequency of input data, All data input lines 401
An object of the present invention is to provide a timing method in which information of 3 to 401n is identified at optimal timing and parallel bit synchronization is easily ensured.

m(mFi
m
an m frequency divider circuit that divides the frequency; n viad aligner circuits to which the output signal of the m frequency divider circuit and each of the n digital signals are supplied; and a delay circuit that delays the output signal of the m frequency divider circuit. and means for retiming the signals of the n signal lines, which are the outputs of the synchronization circuits, using the output signals of the delay circuits and achieving parallel bit synchronization, and each of the bit synchronization circuits: two or more latch circuits that use the output signal of the m frequency divider circuit as a latch clock signal, and use the latch clock signal to load or check the digital signal;
It is characterized by comprising a coincidence detection circuit that receives an output signal of the latch circuit and detects coincidence of the input signals, and means for inverting the phase of the latch clock signal when the coincidence detection circuit detects a coincidence. A timing scheme is obtained.

〔Example〕

FIG. 1 shows a timing scheme that is an embodiment of the invention.

In the figure, 101. S-101tln data input lines, 102Fi clock input d, 103°104t
105 is an exclusive OR gate (nx-o
agegu), 101jD-F/F'.

107 is 'I'-b'/F% 108FiEX-0 which inverts the internal state every time a clock signal is input.
1 (gate, 109 is an inverter circuit, 110t to 11
0° is n bit aligners, 111 is TF/F.

112 is an inverter circuit, and 113 FiD-F/F.

114 is a child circuit, 115s to 115a are n data output lines, and 116 is a clock output line.

Here, the clock signal input from the clock input a102 is the data input fm 101 t~l 01. It has a repetition frequency (2fo) twice that of the repetition frequency component of the data signal input from the input data signal.

TF/Fill constitutes a divide-by-2 circuit) and divides the frequency of the clock signal input from the clock input line 102 by two. Each and door liner circuit 11O! ~110.
Data input, 1!1ull to 101. , and the clock signal output from T-F/Fill will have the same repetition frequency component (fo), but in general, data input lines 1011-101. Between data signals input from, and even data input! 101t~1
01. Data signal input from T-F/F 111
The phase synchronization between the clock signals provided by the clock signal is not ensured, and each input data signal cannot be immediately retimed using this clock signal. Each of the bit aligner circuits 110t to 110° automatically selects a clock signal that is in phase or in phase with the clock signal supplied from the T-F/Fltl in order to retiming each input signal without error. The two latch circuits 103 and 104 use the clock signal supplied from the T-F/F' t 11 to identify the data signal.
1 Retiming the data signal input from t,
The X-OR gate 105, D-F/F l 06, and T-1111/F107 constitute a coincidence detection circuit that detects coincidence of the data signals supplied from the latch circuits 103 and 104. A selector circuit is configured to select the output phase of 0 phase or π phase based on the output signal of the 10BH coincidence detection circuit which receives the output signal as input.Furthermore, an inverter circuit 112, D-
The F/Fl13 constitutes a delay circuit that delays the 2fo clock signal inputted from the clock signal fa102 by π phase, and uses the output signal of this delay circuit to control the latch circuit 11.
4 retiming each data signal transmitted from the bit aligners 1101 to 110n to ensure parallel bit synchronization.0 Below, using FIG.
A process in which the child circuit 114 identifies the data signal inputted from i without any error and retimes each data signal transmitted from each bit aligner 1101 to 110n will be described.

Figure 2 shows the operation waveforms of each part in Figure 1.
A is the start time of this timing chart.

First, the operation of bit aligner circuit 110z will be explained. h
The output signal of mX-OR gate 108 includes T-P/F1
When the output of 07 is 111, an inverted clock of the positive phase output signal of TF/Fl11 is output, and when the output is 101, an in-phase clock signal is output. Two child circuits 103.10
4 is g x-.

Data input 1 at the rising edge of the output signal of 108
011 is identified. Generally gx-o rugut 108
If there is a change point of data input 1ull near the rise of the output signal of
3,104 outputs are insufficient, resulting in identification errors. Therefore, the outputs of latch circuits 103 and 104 are monitored, and both
If a configuration is adopted in which when a mismatch between the child circuits 103 and 104 is detected, a clock signal having an opposite phase to the clock signal supplied to the latch circuits 103 and 104 is automatically supplied as a punching signal of the data signal, the data input 1011 It becomes possible to retiming without error. In Figure 2,
It is assumed that at time B, the latch circuit 103ij mistakenly identifies the input data signal, and the latch circuit 104 correctly identifies it.

The EX-OR gate 1o5 constantly monitors the outputs of the latch circuits 103 and 104, and the output is 0'' in the matching state and M in the mismatching state.
In the F3X-0 gate 105, an undesirable narrow pulse is generated in the straight line a, but this appears when the input signals of the J4X-0 gate 105 change at the same time. . D-F/ni' 101
By punching the output signal of the jg Remove 0 times, 1 g 103゜1
When the outputs of 04 are equal, D-i;'/11' 10
101 appears in the output of 6, but when they are not equal, this output signal is supplied as a control signal for IDX-0R game) 108. As a result, once a mismatch is detected, gx
The phase of the clock output signal 105 is inverted, and this inverted clock signal is used to input the data input 101. Identification is performed. The match detection circuit always judges the match between the outputs of the two slave circuits 103 and 104, and when a match is detected even once, the output of the EX-OR gate 108 rises. It is determined that the clock signal is near the changing point of the data input 1011, the phase of the output of the aX-OR gate lO8 is automatically inverted, and the data input 1011 is subsequently identified using this inverted clock signal. Since the rising edge of this inverted clock appears at the time when the data input 1011 is determined to be in a constant state, by using this clock signal, it is possible to retiming the data signal without error. and each bit aligner circuit 110z to 11
0fl transmits a data signal synchronized with the output signal of T-F/Fill to the child circuit 114, but the latch circuit 114, which receives the outputs of the bit aligners 1101 to 110fi, has two signals, O phase or π phase. Data signals having different phases will be provided. Therefore, the sub circuit 114 uses a clock signal delayed by the π phase of the 2fo clock from the output signal of the T-F/Fill.
Using the output signal of F113, pit aligner 1101~
After performing the output signal timing of 110 and ensuring synchronization between the parallel signal lines, the data output lines 115t~
115fi.

Further, FIG. 3 is a circuit diagram of a second embodiment of the present invention.
This figure shows the configuration of a timing system in which a clock signal having a frequency four times as high as the repetition frequency component of the input data signal is supplied as an input clock signal. In the figure, 3011 to 301fi indicate n data inputs. line, 302 is a clock input line, 3101 to 310nFi
n pit aligners, 311riT-F'/P,
313 and 313sFiT-F/F% 314 is a latch circuit, 3151 to 3151S are n data output lines, 31
6 is the output line 'i'. Here clock input 5
The clock signal input from 3oz is the data input line 3.
4 times the repetition frequency (4fo) for the mb return frequency component of the data signal input from 011 to 30111
have. The T-F/y 311 constitutes a frequency divider circuit, and divides the frequency of the clock signal input from the clock input line 302 by two. Furthermore T-F/F 3131 *
313sFiT-F/P The output signal of 311 is divided by two to obtain a clock signal.

Pit aligner circuit 310. ~310° ensures synchronization between the data signal input from each data input line 3011~301fl and the fo clock signal supplied from T-F/F' 313t. Each pit aligner ai
Ot~310. The output signal is O-phase or π-phase 2! A data signal having M classes of phases is output, and the latch circuit 31
4. On the other hand, 1p-F/F 313a is
π/2 or 3 compared to the output signal of T-t'/F3131
Latch the f0 clock signal with a phase difference of f/2 7 times
1314. The child circuit 314 uses this clock signal to control each door liner 310 . ~310. Retimes the data signals sent from the source to ensure parallel bit synchronization.

Although the present invention has been described above using the embodiments shown in FIGS. 1 and 3, the present invention is not limited to these combinations. For example, in a pit aligner, three
In some configurations, the bit aligner is equipped with a protection counter and the protection counter is used to latch the input data signal. Various configurations are conceivable, such as a configuration in which the number of mismatches in the child circuit outputs is counted, the input data signal is input only after the protection counter has counted up, and the phase inversion control of the clock signal that is input is performed. Furthermore,
As a method of generating a clock signal input from a clock input line, for example, after self-extracting a timing signal of f from an input data signal, a method of having a clock signal of 2fo using frequency duplication, a method of having a clock signal of 2f@, a method of generating a clock signal of 2f@ Various methods can be considered, such as an external supply method.

〔Effect of the invention〕

As described above, the present invention provides a timing method that ensures parallelism and synchronization of data signals input in parallel by using simple logical operations without depending on the repetition frequency of input data. can.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG. 2 is a circuit diagram of the first embodiment of the present invention.
FIG. 3 is a timing chart showing the operation of the second embodiment of the present invention, and FIG. 4 is a 10-step diagram of the conventional example. 101, ~101.・・・・・・n data input lines,
102... Clock input line, 103, 104...
・Dan - Consists of D-Furi, Pufuro, and Pu (D-F/F). Child circuit, 105...EX-OR gate, 106
..., D-F/F1107...T-F/F
1108-...BX-OR gate, 109...
...Inverter circuit, 1101-110fi...
...n bit aligners, ill...T-1
'/F% 112...self...inverter circuit, 113...
...D-F/F%114 Old... U, child circuit, 1
15t~115n...n data output lines,
116...Clock output line %3011~301
fi...n data input lines, 302...
・Clock input line, 310+~310n...
n bit aligners, 311...T-F
/ i=1.313 and 3131...T-F/F
, 314...group latch circuit, 3151-315n...
...N data output lines, 316...Clock output line %4011-401Q...Data input line, 402...Clock input line, 40:(
·····cormorant. Child circuit, 404/old...Selector circuit, 4o5...
...Control signal input line %4061-4o63...
Gate, 4071-407n...Data output line, 408...Clock output line. Agent Patent Attorney Uchihara Back FF/F/Normal phase output EX-IR Gen2t/θ evening output data input 107? I.T.
2 3 4 6Ln-f)/
3-Goka Dormitory 2121 p3 Kaya 4 times

Claims (1)

[Claims] n (n is 2 or more) digital signals and a clock signal having a repetition frequency m (m is 2 or more) times the repetition frequency component of the digital signal is divided by m.
a frequency divider circuit; n bit aligner circuits to which the output signal of the m frequency divider circuit and each of the n digital signals are supplied; a delay circuit that delays the output signal of the m frequency divider circuit; It consists of means for retiming the signals of the n signal lines output from the bit synchronization circuit using the output signal of the delay circuit to achieve parallel bit synchronization, and each of the bit synchronization circuits two or more latch circuits that use an output signal as a latch clock signal and use the latch clock signal to latch the digital signal; a coincidence detection circuit that receives the output signal of the latch circuit as an input and detects coincidence of the input signals; A timing system characterized by comprising means for inverting the phase of the latch clock signal when the coincidence detection circuit detects a mismatch.