JPH08306931A - Formation of array with multichannel structure having continuously doped region in channel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the reverse gate bias leakage current in an array having TFTs by implanting dopant grains so as to form adequate continuous distribution of the grains in in-channel regions of serial channels. SOLUTION: The array 10 is formed by executing many functions: function A forming an m-th scanning line and other scanning lines, function B forming an n-th data line 32 and other data line intersecting the scanning lines at such a cross pint 34, and other part of function C4 doping (Q-1) in-channel regions 54 so that each in-channel region in the set has a continuous distribution of the dopant grains and involves no inner boundary of regions having different dopant concns. Thus implanting of the dopant grains controls the reverse gate bias leakage current flowing in Q channels, and the distribution of the dopant grains in the in-channel regions is obtained.

Description

Detailed Description of the Invention

[0001]

U.S. Pat. No. 4,907,041 to Huang discloses an intra-gat that is immune to misalignment.
e offset) High voltage TFT is disclosed.

The present invention addresses the problems that arise when using TFTs to control connections to cell circuits within an array, such as a display, sensor, or memory array. The reverse gate bias leakage current differs depending on the gate bias and also for each TFT in the array.

In a two-dimensional (2D) array, the TFT of the cell
During the turn-off of the, its gate is held at a stable low voltage, but its channel lead voltage fluctuates. Some leads may fluctuate with the voltage on the data line, while others may fluctuate if the charge level accumulated by the components of the cell fluctuates. Therefore, even if the reverse gate bias is continuously applied to the TFT, the magnitude of the reverse gate bias voltage may change over a wide range. If the minimum leakage current occurs at different reverse gate bias voltages for each TFT in an array, the leakage current will be non-uniform across the array.

The problem that the reverse gate bias voltage changes is
It is particularly serious for polysilicon (poly-Si) TFTs. In conventional polysilicon TFTs, the leakage current increases exponentially with increasing magnitude of the reverse gate bias voltage. Therefore, small differences between the TFTs in an array can produce large differences in leakage current in response to similar reverse gate bias signals. Since each scan line is typically connected to the gates of many TFTs, it is difficult to adjust the bias to get the minimum leakage current.

[0005]

The present invention is based on the discovery of a new technique for controlling reverse gate bias leakage current in arrays having TFTs. This new technology uses a simple multi-channel structure that is easy to manufacture. This new technique implants dopant particles such that each intra-channel region in the series of channels has a suitable continuous distribution of dopant particles. Surprisingly, this technology does not significantly reduce the on-current of the TFT,
It provides excellent control over reverse gate bias leakage current even in polysilicon TFTs.

[0006]

This technique is applied to, for example, an LD.
It is advantageous because it is cheaper and simpler to implement than other solutions for reducing leakage current, such as D-structures and more channels. Although LDD structures lead to masking and uniformity issues and reduce on-current, the techniques of the present invention can be implemented with simple masks in a manner that produces uniform results without reducing on-current. . The uncertain processing steps, such as the precise lithography required to fabricate the LDD structure, are not required by the technique of the present invention. Covers the entire channel area,
Accurate alignment is not required because a mask that slightly overlaps adjacent surfaces can be used to prevent excessive doping of the in-channel regions. Providing more channels leads to the problem of increased capacitance, which is difficult to implement without increasing the size of the device, but the technique of the present invention is nonetheless effective.

This technique is also advantageous because it reduces non-uniformities that prevent adjustment of the gate bias to obtain minimum leakage current. Conventional polysilicon TFTs differ within an array or between multiple arrays to vary the gate bias with minimal leakage. In other words, the optimum gate bias varies from TFT to TFT and from array to array. However, the technique of the present invention is able to identify the worst case reverse gate bias operating conditions for a polysilicon TFT and keeps leakage current under that worst case operating condition below a known maximum value. If retained, the gate bias that minimizes leakage will not change due to such non-uniformities.

The internal channel region has a "continuous distribution" of dopant particles when the in-channel region does not include any internal boundaries between regions having different concentrations of dopant particles.

One channel or series of channels or one
"Reverse gate bias voltage" of One of the TFT is the potential difference V _GS between the gate and the source, in the V _GS 1 single channel or series of channels or TFT is turned off.

The "operating limit" in reverse gate bias leakage current is the limit set by the way the circuit is used.

Assuming that all other parameters are constant, the maximum reverse gate bias leakage current that occurs in the range does not exceed 10 times the minimum reverse gate bias leakage current that occurs in the range. In fact, the reverse gate bias leakage current "does not increase significantly over the range of reverse gate bias voltage."

It is a set of in-channel regions that the reverse gate bias leakage current does not increase significantly over the range of the reverse gate bias voltage that occurs during operation and does not exceed the operational limit on the reverse gate bias leakage current at all. The distribution "controls the reverse gate bias leakage current through the series of channels or TFTs" if it ensures the distribution of dopant concentration in.

Assuming that all other parameters are constant, the on-current flowing through the series of channels or TFTs will be at least as doped as the conductivity of the channel leads. At half size, the distribution of dopant particles in a set of in-channel regions "does not significantly reduce the on-current" through a series of channels or TFTs.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The array 10 of FIG. 1 has M scan lines from a first scan line 20 to an Mth scan line 22 and N scan lines from a first data line 24 to an Nth data line 26. And the data line of the book. The cell circuit connected to the mth scan line 30 and the nth data line 32 will be described in more detail.

As shown in FIG. 1, array 10 can be manufactured by performing a number of functions. One function, designated A, forms the mth scan line 30 with the other scan line. Another function, labeled B, forms another data line with the nth data line 32, which intersects the scan line at an intersection, such as intersection 34.

Another function is to fabricate cell circuits. This function is a component 40
Generates the nth data line 3
2 has data leads for receiving signals and transmitting signals. Further, a portion of this function, designated C1, forms a channel portion 42 connected between the nth data line 32 and the data lead of component 40.

The other part of this function, designated C2-C3, forms Q gate regions 44-46,
Here, Q is 2 or more. Each of gate regions 44-46 extends across channel portion 42 in one of channels 50-52; gate region 44 intersects channel portion 42 in channel 50 as shown, and gate region 46. Intersects channel portion 42 at channel 52. As a result, the channel portions 42 also each have a (Q-
1) It has an in-channel region.

Another part of this function, designated C4, is that each intrachannel region in the set has a continuous distribution of dopant particles and does not include any internal boundaries between regions having different dopant concentrations. , (Q-1) in-channel regions indicated by in-channel regions 54 in FIG. The part indicated as C4 is
Intra-channel region that implants dopant particles in (Q-1) intra-channel regions to control reverse gate bias leakage current through the Q channels and does not significantly reduce on-current through the Q channels. To obtain the distribution of the dopant particles at.

Another function is to make electrical connections at the appropriate connection points. One portion of this function, designated D1, forms an electrical connection between the nth data line 32 and the channel portion 42. The second part of this function, designated D2, forms an electrical connection between the channel portion 42 and the data leads of the component 40. Since many parts of this function, designated D3-D4, form one or more electrical connections, the mth scan line 30 is gate region 44.
To 46 are electrically connected. For such a connection,
The signals on the mth scan line 30 are the channels 50-5.
Control the conductivity of 2.

FIG. 2 shows a general sequence of operations that can carry out the functions in FIG.

The act in box 60 deposits a semiconductor layer and lithographically patterns it to produce channel portion 42 of FIG. Therefore, the operation of box 60 is
1. Perform the function designated C1 in FIG. The act in box 60 can also generate data leads and other portions of component 40, such as capacitor electrodes.

The act in box 62 deposits a first insulating layer on the pattern from box 60. Then box 6
Operation 4 deposits a gate layer and lithographically patterns it to produce gate regions 44-46 of FIG. Thus, the act in box 62 performs the functions labeled C2-C3 in FIG.

The act in box 66 then implants a low concentration of dopant without a mask. Gate region 44-
Since 46 covers channels 50-52, channels 50-52 are not exposed to dopants, but other portions of channel portion 42 are lightly doped, including in-channel region 54. The dopant is implanted such that the resulting distribution of dopant particles in the in-channel region controls the reverse gate bias leakage current of channels 50-52 without significantly reducing the on-current. Therefore, the act in box 66 performs the function designated C4 in FIG.

The act in box 68 then deposits a photosensitive layer and lithographically patterns it to form a mask over the in-channel regions 54 and other regions that are to be avoided from being heavily doped. The act in box 68 then implants a high concentration of dopants and
2 forms a channel lead between the point at which 2 electrically connects to the nth data line 32 and the channel 50, and also forms a channel lead between the channel 52 and the data lead of the component 40. The actuation of box 68 thus forms an electrical connection between channel portion 42 and the data lead of component 40, which is a function shown at D2 in FIG. The act in box 68 can also make gate regions 44-46 conductive if the gate layer is a semiconductor material.

The act in box 70 is to deposit a scan line layer and lithographically pattern the M scan lines 2
0 to 22, which accomplishes the function designated A in FIG. Therefore, the operation of box 70 is
An electrical connection is formed between each of the gate regions 44 to 46 and the mth scan line 30. If the gate regions 44-46 are formed of a semiconductor material and the mth scan line 30 is a metal, an electrical connection is made by forming a metal / semiconductor interface. Thus, the act in box 70 also performs the functions labeled D3-D4 in FIG.

The act in box 72 deposits a second insulating layer. The act in box 74 then exposes the connection point where the channel portion 42 connects to the nth data line 32 by lithographically forming openings in the first and second insulating layers. The act in box 76 then deposits a data line layer and lithographically patterns it to produce N data lines 24, thereby performing the function labeled B in FIG. Thus, the act in box 76 creates an electrical connection between the channel portion 42 and the nth data line 32; if the data line layer is metal, the metal in the opening formed in box 74 is metal / Form a semiconductor interface. Thus, the act in box 76 also performs the function designated D1 in FIG.

FIG. 3 illustrates another schematic operating sequence that can be used to perform the functions of FIG. The sequence of FIG. 3 produces a structure with a gate region under each channel and an ITO layer on top.

The act in box 100 deposits a scan line layer and lithographically patterns it to generate scan lines, thereby performing the function designated A in FIG. The act in box 100 also deposits a gate layer and lithographically patterns the gate region 4
4 to 46, thereby performing the functions designated C2 to C3 in FIG. The gate layer can be the same as the scan line layer, in this case Box 1
00 also performs the functions labeled D3-D4 in FIG. 1; or the gate layer can be a separate layer. If the scan line is a metal and the gate layer is a semiconductor material, depositing the gate layer on the scan line forms a metal / semiconductor interface and makes an electrical connection. Thus, the act in box 100 also performs at least some of the functions labeled D3-D4 in FIG.

The operation of box 102 is similar to that of box 100.
Depositing a first insulating layer on the pattern from The act in box 104 then deposits a semiconductor layer. Box 106
Operation deposits a second insulating layer on the semiconductor layer from box 104.

Next, the operation of box 110 is such that self-aligned backside exposure is performed, and then etching is performed to pattern the second insulating layer by lithography.
Island will be included on 52. Box 1
The operation of 12 implants a low concentration of dopant without a mask, but the islands from box 110 do not expose each of the channels 50-52 to the dopant.
Channel portion 42 that subsequently forms an in-channel region 54
Other parts of the semiconductor layer, including, are lightly doped, so that the operation of box 112 is shown in FIG.
Start executing the function labeled 4. Similar to box 66 in FIG. 2, the dopants are implanted such that the continuous distribution of dopant particles in the in-channel region controls the reverse gate bias leakage current in channels 50-52 without significantly reducing the on-current.

The act in box 114 then deposits a photosensitive layer and lithographically patterns it to form a mask that covers the in-channel regions 54 and other regions that should not be heavily doped. The act in box 114 then implants a high concentration dopant. When the data leads of channel portion 42 and component 40 are subsequently formed, they are electrically connected due to the high concentration of dopants, so that the operation of box 114 begins to perform the function labeled D2 in FIG. Continue executing the indicated function. The act in box 114 may then remove the mask and also anneal to activate and deactivate the channel.

The act in box 116 then lithographically patterns the semiconductor layer to produce channel portion 42 of FIG. 1, thereby causing C1, C4, and D2 in FIG.
Complete the function indicated by. Box 116
2 can also generate data leads and other portions of component 40, such as capacitor electrodes, similar to box 60 of FIG.

The act in box 120 then deposits a third insulating layer and lithographically patterns it so that it has an opening to the semiconductor layer at the connection point. The act in box 122 then deposits a data line layer and lithographically patterns it to produce data lines, thereby performing the function designated B in FIG. Therefore, the operation of box 122 forms an electrical connection between channel portion 42 and the nth data line 32 because the metal in the opening formed in box 120 forms the metal / semiconductor interface; Thus, the act in box 122 performs the function designated D1 in FIG.

The graph of FIG. 4 shows that the ON current I _ON through the channel portion 42 and the reverse gate bias leakage current I
FIG. 4 shows how _OFF changes during the operation of array circuit 10 as a function of dopant concentration ρ in the in-channel region. The magnitudes of I _ON and I _OFF are plotted against the log coordinate axis and include the upper range for currents in the drive current range and the lower range for currents in the leakage current range.

For polysilicon TFTs, for example, the useful drive current range may be in the microampere to milliampere range, while the useful leakage current range may be in the sub-picoampere to nanoampere range. The range depends on the W / L ratio and other parameters. In general,
The drive current range and leakage current range should be separated by more than 5 orders of magnitude for a proper signal to noise ratio.

As shown, I _ON increases sharply as ρ increases from 0, and soon reaches the upper range,
Finally, when ρ = ρ _{S / D} , the value of I _MAX is reached, and
= Ρ _{S / D,} the conductivity of the in-channel region is as great as the conductivity of the channel lead connecting to the nth data line 32 and the data lead of the component 40, which is sometimes the source. Also referred to as / drain lead. For most applications, I
_It is satisfactory if the value of _ON is greater than (0.5) I _MAX , and therefore the dopant concentration ρ _LOW with I _ON = (0.5) I _MAX does not appear to significantly reduce I _ON .

I _OFF also increases from 0, but remains in the lower leakage current range. However, to obtain satisfactory operation with a given drive technique, I
_OFF must not exceed _{IOFF (WDC)} , which is the maximum leakage current that can occur under worst case drive conditions (WDC) for that drive technology.

Component 40 typically includes a capacitive element that stores a charge level within one of two or more different voltage bands for at least a minimum storage period.

The WDC of a given drive technology is the condition under which the capacitive element is most difficult to maintain a given charge level during the minimum storage period, due to the combined effect of all relevant factors. Reverse gate bias leakage current is I
_{Beyond OFF (WDC)} , the capacitive element is unable to hold the charge level within its band during the minimum storage period when WDC occurs, which results in a lack of information.

FIG. 4 shows that I _OFF = I _{OFF (WDC)} , I _{OFF at} a dopant concentration below ρ _HIGH.
Is below I _{OFF (WDC)} . Therefore, for ρ _LOW <ρ <ρ _HIGH ,
I _OFF is controlled because it is less than I _{OFF (WDC)} , but I _ON is greater than (0.5) I _MAX , so I _OFF
Not significantly reduced from _MAX .

FIG. 5 shows how I _OFF varies as a function of gate-source voltage V _GS when the distribution of dopant particles in the in-channel region controls leakage current. The value of I _OFF shown in FIG. 5 occurs at the drain-source voltage V _{DS (WDC)} of _WDC . The dashed line on the left side of the vertical axis shows that I _OFF is I as V _GS increases to a larger negative value if leakage current is not controlled.
It shows that the current exponentially rises to a current larger than _{OFF (WDC)} . This is, for example, the channel part 4
2. All in-channel regions in 2 are shown in FIG.
It occurs when the _{S / D} level is uniformly doped.

However, the distribution of the dopant particles in the in-channel region can control the reverse gate bias leakage current. FIG. 5 shows the range of reverse bias gate voltage from V _{GS (A)} where I _OFF has its minimum level I _OFFMIN to V _{GS ( B)} which is the WDC gate-source voltage. Over the range from V _{GS (A)} to V _{GS (B)} , I _OFF is at its minimum level of 1
It does not increase above 0 times 10 (I _OFFMIN ).
As long as I _OFF is in the shaded area above the A to B line, the reverse gate bias leakage current is controlled and within a predetermined magnitude. Line between points A and _{B, I OFFMIN} throughout its range _{I OFF}
It shows that it is possible to be almost constant.

FIG. 6 shows the mechanism by which the distribution of dopant particles in the in-channel region appears to control the reverse gate bias leakage current. In the graph of FIG. 6, the horizontal axis measures the position in the x direction from the source to the drain of the portion 130, which portion 130 is the portion of the semiconductor layer shown to include the heavily doped channel lead region. . The vertical axis measures the voltage varying from the source voltage V _SS to the drain voltage V _DD .

Portion 130 includes two undoped channels, channel 132 and channel 134, each of which is "intrinsic".
Is marked as "i". Channel lead 1
36 is connected to the source voltage V _SS and is marked ρ ⁺ to indicate having a high concentration of dopant particles. Channel lead 138 is also connected to drain voltage V _DD and is marked ρ ⁺ to indicate a high dopant concentration. On the other hand, the channel inner area 1
40 is marked ρ ⁻ to indicate that it has a low concentration of dopant particles, where 0 <ρ ⁻ <ρ ⁺ .

The portion 130 has two junction depletion regions in which the voltage difference is maintained because the tunneling of holes is suppressed, and the source-drain current I _DS is determined by the conductivity of the two smaller ones. : Depletion region 142 occurs at the junction of channel lead 138 and channel 134. Depletion region 144 occurs at the junction between in-channel region 140 and channel 132. Since they are in series, the current through the depletion regions 142 and 144 should be approximately equal, assuming other leakage mechanisms are controlled. However, the distribution of voltage between the depletion regions 142 and 144 varies with different values of the gate-source voltage _VGS .

As shown in FIG. 5, when the gate-source voltage is V _{GS (A)} or more, the channel 132 is used.
Due to its high conductivity, the voltage drop across the depletion region 144 is just large enough to allow current to flow. For a typical polysilicon TFT implementation,
This occurs when V _GS > -2V, for which Sturm, J. et al. C. (Sturm, JC), Wu, I. W. (Wu, I.W), and Hack, M (Ha
ck, M) "Leakage Current Modeling of Series Thin Film Transistors.
ng of Series-Connected Th
in Film Transistors "(IEE
E Transactions on Electro
n Devices, Vol. 42, No. 8, Aug
ust 1995, pp1561-1563). In this state, since the tunneling of holes is limited in the depletion region 142, the depletion region 142 is less conductive than the depletion region 144, and the actual source-drain current is limited. Therefore, the on and leakage currents in this state are determined by the voltage drop across the depletion region 142, which is very high for high positive values of V _GS , but the two depletion regions 142 and 14 are depleted.
4 will reach its minimum at V _{GS (A)} with a voltage drop such that their conductivities are equal.

WDC represented by V _{GS (B) in} FIG.
The gate-source voltage is significantly more negative than V _{GS (A)} . Assuming drain voltage V _DD and source voltage V _SS are held constant, channels 132 and 134 are for V _{GS (B) and} for other values of V _GS <V _{GS (A)} . Passes only leakage current. In this state, the drain end of the channel 132 becomes less conductive than the depletion region 142. Hole tunneling is the depletion region 1
As it increases at 42, the voltage drop across depletion region 142 decreases and therefore the voltage drop across depletion region 144 increases. If the negative value of V _GS is sufficiently large, a large voltage drop will occur across the depletion region 144 and a high field effect, which is a major cause of leakage current, will occur.

If the in-channel region 140 has a high dopant concentration, such as ρ ⁺ , then the magnitude of the drain-source current I _DS through the portion 130 will be a single channel T.
It has the same slope in the reverse gate bias region as in the case of FT. Furthermore, as shown by the uncontrolled I _OFF dashed line in FIG. 5, increasing the number of channels in the structure has the same reverse gate bias leakage current slope as a single gate device, because it has the highest channel field. Point always moves to the drain side of the channel closest to the source, and the resulting junction in the depletion region has the same dopant concentration difference as all other junctions.

However, the in-channel region 140 is ρ _HIGH.
4 with a smaller dopant concentration ρ ⁻ .
I _DS is less than I _{OFF (WDC)} as shown by, and for appropriate values of ρ ⁻ , I _DS as shown in FIG.
Is controlled over a range of reverse gate bias voltages.
The relatively small difference in dopant concentration across the junction between the channel 132 and the in-channel region 140 is more than spread over the depletion region 142, as shown by the relative size of the depletion regions 142 and 144 in FIG. It widens the voltage drop in the depletion region 144 over a long distance. Therefore, the electric field in the depletion region 144 is also widened,
Hole tunneling in depletion region 144 is limited, which limits the actual source-drain current, which is a major factor in reverse gate bias leakage current for V _GS . For example, assuming that the depletion region 142 is 0.2 μm long and the depletion region 144 is 1 μm long,
For example, the peak electric field is reduced by a factor of 5, and hole tunneling, which varies exponentially as a function of the peak electric field, is greatly reduced.

The array 150 of FIG. 7 has a first scan line 160.
To M-th scan line 162, and N data lines from the first data line 166 to the N-th data line 168. The cell circuit connected to the mth scan line 170 and the nth data line 172 is shown in detail.

As shown in FIG. 7, the polysilicon portion 180 and the conductive line 182, which can be a heavily doped polysilicon line, are line 18
2 form an intersecting L-shape that intersects polysilicon portion 180 in channels 184 and 186. Line 1
82 is an end portion 18 electrically connected to the m-th scanning line 170.
8 which provides the gating signal. Thus, the region of line 182 extending across channels 184 and 186 acts as a gate region.

Polysilicon portion 180 is connected between data line connection points 190, which may include through metal connections, and data leads of component 192. In the embodiment shown, line 182 is electrically conductive,
The gate signal on the m-th scanning line 170 is the connection point 19
Controls the conductivity of the portion 180 between the 0 and the data lead of the component 192. When the voltage at the mth scan line 170 is high, the channels 184 and 186 are both highly conductive, but when the voltage at the mth scan line 170 is low, the channels 184 and 186 only conduct leakage current. .

Polysilicon portion 180 also includes an in-channel region 194 between channels 184 and 186.
The channel region 194, as described in more detail below.
The distribution of the dopant particles in controls the reverse gate bias leakage current but does not significantly reduce the on-current.

FIG. 8 shows the m-th scanning line 2 indicated by a broken line.
00, the (m + 1) th scanning line 202, the nth data line 204, and the (n + 1) th data line 2
06 and a portion of array 150 with. FIG. 8 also shows the mth scan line 200 and the nth data line 20.
4 shows the part of the cell circuit for the cell connected to 4.

The circuit of the cell is the first polysilicon pattern 2
10, the pattern 210 includes a first connection point 212.
To a second connection point 214, and a line extending from the second connection point 214 to the capacitor electrode 216.

The cell circuitry also includes channels 222 and 2
At 24, a second polysilicon pattern 220 having a line that intersects the first polysilicon pattern 210 is included. The second polysilicon pattern 220 extends from the end 226, and the pattern 220 is electrically connected to the mth scan line 200 at the end 226.

FIG. 8 also shows a lightly doped region 230, which is the region masked during heavy doping.
As a result, the portion of the polysilicon pattern 210 extending between the channels 222 and 224 can remain lightly doped. The second polysilicon pattern 220 also acts as a shield during heavy doping so that the channels 222 and 224 can remain undoped. For ease of fabrication, the mask on the lightly doped region 230 is patterned with the second polysilicon pattern 2 as shown in FIG.
It can overlap slightly with 20.

FIG. 9 is a cross-sectional view showing a substrate (base) 240 which can be quartz or glass, and its surface 2
A circuit 244 is formed at 42. Circuit 244 is surface 24
2 includes an insulating layer 250 on which a polysilicon portion 252 which is a portion of the first polysilicon pattern 210 shown in FIG. 8 is connected to the m-th scanning line 200 and the n-th data line 204, respectively. Is formed for the cell circuit to be formed.

The circuit 244 also includes an insulating layer 256 between the polysilicon portion 252 and the second polysilicon pattern 220 shown in FIG. Second polysilicon pattern 2
20 also includes heavily n-doped polysilicon and is electrically connected to the mth scan line 200.

The circuit 244 then includes an insulating layer 260 that separates the second polysilicon pattern 220 from the nth data line 204. On the nth data line 204 is a polyimide passivation layer 262.

In FIG. 9, polysilicon portion 252 includes channel lead region 272, channel 224, and in-channel region 274. The channel lead region 272 is
It comprises heavily n-doped polysilicon as indicated by n ⁺ . The channel 224 is underneath the second polysilicon pattern 220 and is therefore undoped intrinsic polysilicon as indicated by "i". In-channel region 274 comprises lightly n-doped polysilicon as indicated by n ⁻ . The second polysilicon pattern 220 provides a signal from the mth scan line 200 to the channel region 270, and the signal controls the conductivity of the channel 224.

FIG. 10 is another cross-sectional view of FIG. 9 taken along line bb and therefore has the same layers as described above. In addition, dark matrix lines 280 and 2
82 is formed on the passivation layer 262 over the edge of the nth data line 204, and the indium tin oxide (ITO) pixel electrodes 290 and 292 slightly overlap the dark matrix lines 280 and 282.

In FIG. 10, the polysilicon portion 252 is
It includes a channel lead region 276, a channel 222, and an in-channel region 274. Channel lead area 276
Includes heavily n-doped polysilicon as indicated by n ⁺ . Channel 222 underlies second polysilicon pattern 220 and is therefore undoped intrinsic polysilicon as indicated by i. The in-channel region 274 is the same as that shown in FIG. The second polysilicon pattern 220 also includes the m-th scan line 20.
A signal is provided from 0 to the channel region 278 which controls the conductivity of the channel 222.

The operation of box 330 begins by manufacturing the surface of a quartz or glass substrate. The act in box 330 may include any necessary cleaning.

The act in box 332 then deposits a first layer of low temperature oxide (LTO), which can be SiO ₂ deposited by plasma enhanced chemical vapor deposition.
The first LTO layer can be deposited to a thickness of 0.7 μm and then annealed.

The act in box 334 deposits a layer of a-Si to a thickness of 0.1 μm and performs silicon self-ion implantation to enhance performance. The act in box 334 is also 6
Crystallize and anneal at 00 ° C. as a result,
a-Si becomes polysilicon. The act in box 334 is to lithographically perform the first polysilicon pattern 2
A pattern of mask material is created that covers the portion of polysilicon forming 10. The act in box 334 then etches to remove areas not covered by the pattern of mask material, leaving the first polysilicon pattern 210.

The act in box 336 deposits a second layer of LTO to a thickness of 0.085 μm. The act in box 336 also performs oxidation at 950 ° C. under 150 atmospheres to anneal the second LTO layer.

The act in box 340 deposits a layer of polysilicon to a thickness of 0.35 μm. The act in box 340 performs lithography to perform masking material to cover the polysilicon portions that form the second polysilicon pattern 220, or another similar pattern that intersects the first polysilicon pattern 210 in two or more channels. Generate a pattern. The act in box 340 then performs an etch to remove areas not covered by the pattern of mask material, leaving the second polysilicon pattern 220. Then work

The act in box 342 implants a low concentration n-type dopant without a mask. As a result, all exposed portions of the first polysilicon pattern 210 that are not covered by the second polysilicon pattern 220 are lightly n-doped so that the dopant concentration is substantially equal at all positions. . Compared to the LDD technique, the operation of box 342 does not require a mask because the second polysilicon line 220 covers the channels 222 and 224 so that the lightly n-doped in-channel region 274 is the channel. This is because it is self-aligned with 222 and 224. Therefore, the channel area 27
4 has a continuous distribution of dopant particles with no internal boundaries between regions of different dopant concentration. Intrachannel region 274 because the local concentration of dopant particles is approximately equal to the average dopant concentration for all suitable amounts therein.
Will also be uniformly doped, even though the dopant concentration in the region may vary slightly.

The implant concentration of dopants is selected such that the resulting implant distribution in the in-channel region 274 controls the reverse gate bias leakage current without significantly reducing the on-current as described above. For example, from experiments with multi-channel polysilicon structures, if the channel leads have an average dopant concentration of 2 × 10 ²⁰ cm ⁻³ , the average dopant concentration produced in box 342 is 5 × 10 ¹⁵ cm ^−3. From 2 × 10 ¹⁹ c
It can range up to m ⁻³ , 1 × 10 ¹⁷ cm
^-3 greater than the average concentration is the most effective in maintaining the on-state current, the average concentration of less than 2 × 10 ¹⁸ cm ^-3 was found to be effective in controlling the reverse gate bias leakage current. For example, _{I ON} in an average concentration of 1 × ¹⁰ 18 ^{cm -3} is about _{0.7I MAX,} 1 × ^{10 17} c
_{I ON} is the average concentration of m ^-3 is about _{0.5I MAX.} The device-specific dopant concentration should be selected based on experimental results for that device,
It is because various other parameters, such as channel lead dopant concentration, channel length and width, number of gates, spacing between gates, etc., can determine what distribution of dopant particles is effective. Because you can. The distribution of the dopant particles can be very uniform throughout each intra-channel region so that the local dopant concentration at any location within each intra-channel region will be approximately equal to the average dopant concentration.

The act in box 344 lithographically produces a mask material pattern that does not cover the cell circuitry, but in the lightly doped region 230 of FIG.
Since the land that covers the
Will be covered. Since the land slightly overlaps with the second polysilicon pattern 220, the lightly doped region 230 includes a portion of the second polysilicon pattern 220, thereby causing the edge of the land to overlap the second polysilicon pattern 220. The difficulty of aligning with the edges is avoided. The pattern of mask material is also
It is also possible to cover the area where the peripheral circuit is formed on the substrate. The act in box 344 then implants a high concentration of n-type dopant to render the second polysilicon pattern 220 conductive and the first polysilicon pattern 2
Channel leads 272 and 276 are formed in 10. The act in box 344 then removes the mask material by a suitable plasma resist etch.

The act in box 346 is to lithographically produce a mask material pattern that covers the cell circuitry but not the peripheral circuitry. The act in box 346 then implants a high concentration of p-type dopant into the peripheral circuitry to form a conductive region. The act in box 346 then removes the mask material. The act in box 346 is also 60
Crystallization annealing is performed at 0 ° C.

The act in box 348 is to move the metal layer to 0.1.
Produce a scanline layer with a thickness of ~ 0.2 μm. The scan line layers are, for example, three or four 0.01 μm TiW
It is possible that the layers are hybrid TiW / AlCu multi-layers separated by two or three 0.05 μm AlCu layers.

The act in box 348 then performs lithography to produce a mask material pattern that covers the portions of the scan line layer that form the scan lines. Then box 34
The operation of 8 etches to remove areas not covered by the pattern of mask material, leaving scan lines. The act in box 348 then removes the mask material.

The act in box 350 deposits a third LTO layer to a thickness of 0.7 μm. The act in box 350 also performs a hydrogen treatment to remove the first polysilicon pattern 21.
The channel at 0 is passivated and an appropriate wet oxygen etch is performed to remove the layer damaged as a result of the hydrogen treatment. This hydrogen treatment is performed on the first polysilicon pattern 2 because the scan line formed in box 346 is not on the channel in the first polysilicon pattern 210.
It does not degrade the channel properties at 10.

The act in box 352 performs lithography to cover the first and second connection points 212 and 214 and any other areas where the metal of the data line layer contacts the layer formed in box 334. Although not, a mask material pattern that covers all other areas is generated. The act in box 352 then etches, in the uncovered areas, box 336 and box 350.
Forming openings in the second and third LTO layers from The act in box 352 then removes the mask material.

The act in box 354 deposits a data metal layer to a thickness of 0.5 μm. The data metal layer is, for example,
It can be a hybrid TiW / AlCu multi-stack as described above. The act in box 354 then performs lithography to produce a mask material pattern that covers the data line layers that form the data lines and covers the openings to the second connection points 214. The act in box 354 then etches to remove areas not covered by the mask material pattern, leaving the data lines. The act in box 354 then removes the mask material.

The act in box 356 deposits a passivation layer of polyimide to a thickness of 1.5 μm. Box 35
The operation of 6 performs lithography and the second connection point 214
And a mask material pattern that does not cover the metal of the data line layer for contacting and any other areas. The act in box 356 then etches to form openings in the passivation layer in the uncovered areas. The act in box 356 then removes the mask material.

The act in box 360 deposits a dark matrix layer of TiW to a thickness of 0.1 μm. The act in box 360 is to perform lithography to generate a mask material pattern that covers the dark matrix layer only in areas that need to be shaded, such as areas along the edges of each data line or areas around the second connection points 214. To do. The act in box 360 then etches to remove the uncovered areas. Then Box 3
The act of 60 removes the mask material.

The operation of the box 362 is 0.05% ITO.
Deposit to a thickness of 5 μm. The act in box 362 is to lithographically create a mask material pattern that covers the ITO layer in the light transmissive cell regions. Box 3
The act of 62 then etches to remove the uncovered areas. The act in box 362 removes the mask material and anneals the ITO layer at 280 ° C.

The array described above can be operated in a liquid crystal display by providing a signal in any of several driving ways.

For dot or pixel inversion drive technology,
WDC occurs when V _GS = -7V and V _DS = + 5V. For other driving techniques such as frame inversion, gate line inversion, and column inversion, WDC is V _GS = -2.
It occurs when V and V _DS = + 10V.

The graph of FIG. 12 shows the drain-source current concentration J _DS as a function of the gate-source voltage V _GS for two simulated devices. Curve 400 shows simulation results for a multi-channel polysilicon TFT with an average dopant concentration of 5 × 10 ¹⁷ cm ⁻³ in each in-channel region. Curve 402 shows simulation results for a multi-channel polysilicon TFT with an average dopant concentration of 2 × 10 ¹⁹ cm ⁻³ in each in-channel region. In both cases, the TFT channel leads were assumed to have an average dopant concentration of 2 × 10 ¹⁹ cm ⁻³ .

Curve 402 shows how the concentration of the reverse gate bias leakage current rises exponentially from its minimum when the region in the channel is heavily doped, while the curve 400 shows a low concentration. It is shown that the distribution of dopant particles in the doped in-channel region controls the leakage current concentration over the range of reverse gate bias voltage. As a result, for large reverse gate bias voltages, the magnitude of the leakage current is greater when the channel region is heavily doped than when it is lightly doped. Curves 400 and 402
In addition, it is shown that the lightly doped on-channel region does not significantly reduce the obtained on-current as compared with the lightly doped region.

The techniques described above have been implemented in test chips. The number of channels per structure was changed from 1 to 8.
The doping structure is; a structure in which a channel lead having no LDD region is highly doped, and an in-channel region is highly doped; and a channel lead having an LDD region is heavily doped, and an in-channel region is highly doped. A structure in which the channel lead is doped at a high concentration and a region in the channel is doped at a low concentration; Channel lead 2 × 10 ²⁰ cm
^-3 to 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ³ in a channel region which is lightly doped.
Doping was performed at a concentration in the range of ¹⁹ cm ⁻³ . The width of the channel was changed in the range of 1 to 50 μm. The length of the channel was changed in the range of 1 to 50 μm. We used several different processes.

FIGS. 13 and 14 show examples of test results for a two-channel structure having a width and length of 50 μm and a channel layer and oxide layer thickness of 1000 Å. The area in the channel in FIG. 13 is 1 × 10 ¹⁸ cm ^−3.
14 had an average dopant concentration of .beta., But the in-channel region of FIG. 14 was doped to the same level as the channel leads.
In each figure, the upper curve shows the results with V _DS = 10V, the middle curve shows the results with V _DS = 5V, and the lower curve shows the results with V _DS = 0.1V.

As can be seen, the distribution of dopant particles in the in-channel region of FIG. 13 controlled the reverse gate bias leakage current without significantly reducing the on-current.
On the other hand, in FIG. 14, the leakage current is high in the middle and high drains.
It increased exponentially with increasing reverse gate bias voltage relative to source bias, but was controlled for low drain-source bias where there should not be high field effect between channel leads.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an array in which each cell includes a multi-channel structure in which an in-channel region has a continuous distribution of dopant particles, showing the functions performed in producing the array.

FIG. 2 is a flow chart showing a schematic sequence of operations for producing the same array as in FIG.

3 is a flow chart showing another general sequence of operations for producing the same array as in FIG.

4 is a graph showing maximum on-current and maximum reverse gate bias leakage current as a function of dopant concentration in the in-channel region of FIG.

5 is a graph showing an example of drain-source current as a function of gate-source voltage for the same structure as FIG.

FIG. 6 is a diagram showing how leakage current can be controlled by reverse gate bias with different distributions of dopant particles in the channel region in the same structure as in FIG. 1, and is shown in combination with a schematic diagram and a graph. .

FIG. 7 is a two-channel polysilicon (poly-S) having an in-channel region having a continuous distribution of dopant particles.
i) A schematic diagram of an embodiment of an array in which each cell comprises a TFT.

8 is a first and second circuit of the one-cell circuit of FIG.
It is a figure which shows the schematic layout of a polysilicon layer.

9 is a cross-sectional view of a cell circuit taken along line aa in FIG.

10 is a cross-sectional view of the cell circuit taken along line bb in FIG.

11 is a flow chart showing the operation in producing the array of FIG.

FIG. 12 is a graph showing simulated drain-source current as a function of gate-source voltage for two dopant particle distributions in the in-channel region.

FIG. 13: Gate-drain-as a function of source voltage for a conventionally doped in-channel region.
It is a graph which shows the measured value of source current.

FIG. 14 is a graph showing drain-source current measurements as a function of gate-source voltage for regions in the channel having a distribution of dopant particles that control reverse gate bias leakage current.

 ─────────────────────────────────────────────────── ————————————————————————————————— Inventor Ewayou California, USA 94024 Los Altos Miguel Avenue 1201

Claims (1)

[Claims] 1. A method of forming an array circuit on a surface of a substrate, the array circuit including: a scan line; a data line; and a cell circuit for each scan line and each data line, The cell circuit is connected to the scan line and the data line,
The cell circuit includes a component including a data lead for receiving a signal from the data line and transmitting a signal to the data line, and between the data line and the data lead under the control of the scan line. A polysilicon thin film transistor for providing an electrical connection of the polysilicon thin film transistor, the polysilicon thin film transistor having a first connection point for electrical connection to the data line and a second connection for electrical connection to the data lead. A series of channels between the points and an intra-channel region, one of the intra-channel regions being between adjacent pairs of channels in the series of channels, each of the intra-channel regions being a dopant particle. To control the reverse gate bias leakage current through the channel and The distribution of the greatly reduced without dopant particles flip the On current to have said channel region, a method of forming array circuitry on the surface of the substrate, which comprises implanting dopant particles to each of said channel region.