JPH08306130A - Digital signal processor - Google Patents

Abstract

PURPOSE: To exactly conduct the signal processing of digital information signals by conducting the processing of the digital information signals, which are synchronized to sampling clock signals, in synchronization with system clock signals. CONSTITUTION: A rate converting means 1 receives digital information signals, which are synchronized to sampling clock signals fs, from a bus 30 of a signal processing means 5. The digital information signals are synchronized to gate clock signals GK through an AND circuit 3 and a gate circuit 4 and are transmitted to the bus 30. On the other hand, the signals GK are synchronized to system clock signals SK read from an instruction memory 17 of a coefficient setting means 8 and outputted. Moroever, the frequency of the signals fs is varied by a sampling clock varying means. Since the signals fs are synchronized to the signals SK and outputted, an exact signal processing is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus, and more particularly to a digital signal processing apparatus which is supplied with digital information signals standardized at a plurality of types of sampling frequencies and performs signal processing of the digital information signals. .

[0002]

2. Description of the Related Art Today, it is provided in a computer, an image signal processing apparatus, an audio signal processing apparatus, etc., and performs predetermined signal processing of supplied digital information signals such as data, command signals, image signals and audio signals. Digital signal processing devices such as a digital signal processor (hereinafter, referred to as DSP) are in widespread use.

The sampling frequency of the digital information signal supplied to the digital signal processing device differs depending on the standard of the system in which the digital signal processing device is provided. Therefore, in the digital signal processing device, the operation clock is variably set according to the sampling frequency signal to perform signal processing.

In addition, in order to perform signal processing between digital information signals having different sampling frequencies, the time axes are expanded / reduced so that the time axes of the sampling points of the digital information signals are aligned with each other, and the digital information signals of the two are mutually digitalized. Signal processing is performed by synchronizing signals.

[0005]

By the way, in the digital signal processing apparatus, it is difficult to completely synchronize the phases of the digital information signals with each other, and when the synchronization is deviated, the signal processing is accurately performed. There is a problem that there is no.

In view of the above problems, it is an object of the present invention to provide a digital signal processing device that performs accurate signal processing with a simple structure.

[0007]

A digital signal processing apparatus according to the present invention, which has achieved this object, latches a supplied digital information signal in synchronization with a sampling clock signal, and the latched digital information signal is transferred to a system. A rate conversion means for transmitting in synchronization with a clock signal, a signal processing means for performing signal processing in synchronization with the system clock signal for the digital information signal supplied from the rate conversion means, and a sampling frequency for the digital information signal. And a sampling clock variable means for variably setting the frequency of the sampling clock signal.

[0008]

According to the digital signal processing apparatus of the present invention having the above configuration, the digital information signal supplied in synchronization with the sampling clock signal by the rate conversion means is supplied to the signal processing means in synchronization with the system clock signal. Send out,
The signal processing means processes the digital information signal in synchronization with the system clock.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a digital signal processing device according to the present invention will be described below with reference to the drawings.
The digital signal processing device is a digital audio tape recorder (hereinafter referred to as DA).
Called T. ) Is shown in FIG.

The above-mentioned DAT is formed on the main surface of the magnetic tape 40 which is run by the running means and the running means which allows the running direction and running speed of the magnetic tape 40 mounted as shown in FIG. A drum-type rotary head 41 that records and reproduces an information signal for one track each time it makes one revolution in the scanning direction, and PCM demodulates the audio signal reproduced by the rotary head 41 to output a sound, or the supplied audio. Recording / reproducing means 42 for PCM modulating the signal and recording
And a digital signal processing device 10 for processing the information signal demodulated by PCM by the recording / reproducing means 42 and supplying it to the recording / reproducing means 42, the recording / reproducing means 42 and the digital signal processing device 10. And a mode setting means 46 for setting control conditions in the microcomputer 45 according to the operation mode of the DAT.

The microcomputer 45 records the data according to the control condition set by the mode setting means 46.
A sampling frequency is set in the reproducing means 42, the recording / reproducing means 42 is operated in synchronization with the sampling clock signal fs, and the digital signal processing device 10 has a system clock having a frequency which is an integral multiple of the sampling clock signal fs. The digital signal processing device 10 is operated in synchronization with the signal SK to cause the digital signal processing device 10 to perform signal processing according to the command signal. In this way, the microcomputer 4
5 functions as a sampling clock setting means.

The DAT standard has four recording / reproducing modes and two reproducing-only modes as shown in FIG.

In the recording / reproducing mode, the sampling frequency is 48 KHz and the quantization bit number is 16 bits.
8k mode, each sampling frequency is 32KHz
, 32k mode with 16 bits of quantization bit, 32 bits with 12 bits of quantization bit and 2 channels of 2CH
It has a k-LP mode and a 32k-4CH mode in which the number of quantization bits is 12 bits and the number of channels is 4CH, and the 48k mode is required to be standard equipment.
Other modes are optionally equipped.

In the reproduction-only mode, the sampling frequency is 44.1 KHz and the number of quantization bits is 1.
It has a 6-bit magnetic tape running speed and track pitch of standard 44k mode and a magnetic tape running speed and track pitch of 1.5 times standard 44k-WT mode. The mode also requires standard equipment.

In this DAT, the information signal of two tracks is set as one frame and the rotary head 1 drives the magnetic tape 40.
The digital information signal for each track is recorded in the main data area. The tracks of the one frame are interleaved with each other, and the interleaving is performed to disperse error information due to the positional deviation of the track position of the magnetic tape 40 and the rotary head 1 and the like. The lack of is suppressed.

As shown in FIG. 3A, the main data area is composed of 128 blocks, and a synchronization signal (SYNC), a main ID signal W1, and a main ID signal W are arranged in order from the beginning.
2. Main ID parity signal and main data MD1,
It is composed of MD2.

The above-mentioned main data MD1 and main data M
D2 is an audio signal and is interleaved with each other. The interleaving disperses error information due to floating of the magnetic tape 40 from the rotary head 1 and the like, resulting in a missing information signal. And the parity codes C1 and C2 based on the doubled (32.28) Reed-Solomon code are applied to enable error correction.

Further, the main data MD1 in the specifications of the respective recording / reproducing modes such as the rotational speed of the rotary head 41 shown in FIG. 2, the sampling frequency, the number of quantization bits, etc.
When MD2 is recorded, an empty area is created in the main data MD1 and MD2 in any mode. In this empty area, as shown in FIGS. 3B and 3C, sub-data SD1 and SD2 each consisting of 8 blocks are recorded. The main data MD1 and MD2 are each divided into eight areas, and the divided main data MD1 and MD are divided into eight areas.
2 sub-data SD1 and SD2 in each area
Are assigned and recorded in order.

As shown in FIG. 4A, the format of one block of the main data MD1 and MD2 is such that the synchronization signal (SYN) is sequentially provided for each symbol (= 8 bits) from the beginning.
C), a main ID signal W1, a main ID signal W2, a main ID parity signal, and main data of 8 × 32 symbols.

The main ID signal W1 is composed of formats ID0 to ID7 in which specifications required for recording and reproduction are set as shown in FIG. 4B, and a frame address assigned to each track in the running direction of the magnetic tape. To be done. For example, in the format ID2, the sampling frequency of the digital information signal is set as shown in FIG. 4C. The number of channels of main data in one track is set in the format ID3. A quantization rule such as the number of quantization bits is set in the format ID4. A track pitch is set in the format ID5.

In the main ID signal W2, as shown in FIG. 4B, the block address for every 8 blocks from the beginning of each track is recorded.

As shown in FIG. 5A, the format of one block in the sub-data area is such that a synchronization signal (SYNC), a sub-ID signal SW1, a sub-ID signal SW2 and a sub-ID parity signal are arranged in order from the beginning for each symbol. 8x3
It is composed of sub-data of 2 symbols.

As shown in FIG. 5B, the sub ID signals SW1 and SW2 include a control ID, a data ID, a pack ID, programs ID1 to ID3, etc. in which data required for high speed search is set. The control ID
Is a table of contents that functions as a list of the beginning position of the song, the arrangement position of each movement, and the capacity.
Information (hereinafter referred to as TOC information) is set. The purpose of use of the sub ID signals SW1 and SW2 is set in the data ID. The configuration of the sub ID signals SW1 and SW2 and the arrangement of each data are set in the pack ID.
A program for editing or the like is set in each of the programs ID1 to ID3.

The digital signal processing apparatus 10 according to the present invention provided in the DAT includes a rate converting means 1 for converting the sampling rate of the supplied digital information signal as shown in FIG. 6, and the rate converting means 1. And a signal processing means 5 for processing the converted digital information signal.

The rate conversion means 1 is supplied with main data MD1 and MD2 of digital information signals from the bus 30 of the signal processing means 5 in synchronization with the sampling clock signal fs based on the sampling frequency, and the main data MD1 is supplied. , MD2, an AND circuit 3 for outputting a logical product of the main data MD1, MD2 supplied from the register 2 and the sample flag signal FS-FLG, and an output signal of the AND circuit 3 for a gate clock signal. And a gate circuit 4 for transmitting to the bus 30 in synchronization with GK.

The sample flag signal FS-FLG is
It is formed based on the exclusive OR of the sampling clock signal fs and the digital information signal.

The gate clock signal GK is formed by sending the system clock signal SK in accordance with a predetermined instruction read from the instruction memory 17 provided in the coefficient setting means 8.

In the rate conversion means 1, for example, as shown in FIG.
When the frequency of the sample flag signal FS-FLG shown in is half the frequency of the sampling clock signal fs of the main data MD1 and MD2 shown in FIG. 7B, the main data supplied from the register 2 for each sampling clock signal fs MD1 and MD2 are transmitted, and the AND flag 3 outputs the sample flag signal FS-F as shown in FIG. 7C.
Main data MD1 and MD2 when LG is in High state
Is transmitted, and the Low signal is transmitted when the sample flag signal FS-FLG is in the Low state. The output signal of the AND circuit 3 is supplied from the gate 4 to the signal processing means 5 for each system clock signal SK.

As described above, the rate conversion means 1 is
Main data MD for each sampling clock signal fs
1, MD2 is taken in, and the sample flag signal FS-FL
Data is sent for each G. As a result, according to the sampling clock signal fs, in synchronization with the system clock signal SK which is the operation clock of the signal processing means 5,
It becomes possible to send data for signal processing to the signal processing means 5.

The signal processing means 5 comprises an interface 7 for inputting and outputting a digital information signal, a coefficient setting means 8 for associating a predetermined coefficient with the digital information signal supplied from the interface 7, and the coefficient setting means 8. It has a computing means 9 for computing the associated digital information signal and coefficient, and a bus 30 for connecting the interface 7, the coefficient setting means 8 and the computing means 9 to each other.

The interface 7 includes an input port 11 to which a digital information signal is supplied, and the input port 11
Input register 12 for sequentially sending the digital information signal supplied to the bus 30 to the bus 30 in synchronization with the sampling clock signal fs, and an output register to which the digital information signal is supplied from the bus 30 in synchronization with the sampling clock signal fs. 13 and an output port 14 for transmitting the digital information signal supplied from the output register 13.

The coefficient setting means 8 includes an instruction address generator 16 for generating an instruction address, and an instruction memory 1 for reading an instruction for each instruction address.
7, a coefficient address generator 18 for generating a coefficient address and a data address on the basis of the read instruction, a data address generator 19, and a coefficient memory 20 for writing a coefficient in a readable manner for each coefficient address. A data memory 21 in which data is readably written for each data address, a coefficient selector 22 for selecting and transmitting a coefficient supplied from the coefficient memory 20 or the bus 30, the data memory 21 or the bus Thirty
The data selector 23 selects and sends the data supplied from the.

Instruction address generator 1
6, the address is reset when the command signal supplied from the microcomputer 45 or the power supply voltage of the DAT is turned on, and the address is incremented by 1 every one instruction cycle of the microcomputer 45.

Instructions are written in advance for each address in the instruction memory 17, and the instructions are read out for each address generated by the instruction address generator 16.

In the coefficient address generator 18, a coefficient address is written in advance for each instruction,
The coefficient address is read for each instruction read from the instruction memory 17.

In the data address generator 19, a data address is written in advance for each instruction, and the data address is read for each instruction read from the instruction memory 17.

The coefficient memory 20 stores the data address generated by the coefficient address generator 18 in the bus 3
The coefficients of the sub data SD1 and SD2 supplied via 0 are written in a readable manner.

The data memory 21 has main data MD1, MD2 supplied to the data address generated by the data address generator 19 via the bus 30.
Is written readable.

The coefficient selector 22 is responsive to a command signal supplied from the microcomputer 45 to supply the sub data SD1 and SD2 supplied via the bus 30.
Or the coefficient read from the coefficient memory 20 is selected and transmitted.

The data selector 23 is responsive to a command signal supplied from the microcomputer 45 to supply the main data MD1, MD supplied via the bus 30.
2 or main data MD1 and MD2 read from the data memory 21 are selected and transmitted.

The calculating means 9 multiplies the coefficient supplied from the coefficient selector 22 of the coefficient setting means 8 by the main data MD1 and MD2 supplied from the data selector 23, and the output of the multiplier 24. A shifter 25 for sequentially shifting and holding signals, and an adder 26 for supplying an output signal from the shifter 25 to one input terminal and adding the output signal and a signal supplied to another input terminal
An accumulator 27 that stores the output signal of the adder 26, a selector 28 that selects the signal stored in the accumulator 27 or 0 and supplies it to the other input terminal of the adder 26, and the output of the accumulator 27 Signal the above bus 3
Clipper 2 rounded to a word length of 0 and supplied to the bus 30
9 and.

In the calculating means 9, for example, 8-bit unit main data MD1 and M for each sampling frequency fs are used.
The impulse signal of the audio signal forming D2 is supplied from the selector 23, the coefficient b of each impulse signal is supplied from the selector 22, and the multiplier 24 multiplies the impulse signal by the coefficient b from the first impulse signal to N. The impulse signal delayed to the output is sequentially performed, and the N + 1 multiplication results are sequentially added by the adder 26, and the accumulator 27
Then, by sequentially convolving the addition result, the impulse response H (Z) of the actual frequency characteristic shown in the following equation (1) is output.

[0043]

[Equation 1] In this way, the computing means 9 uses the finite-length impulse response (fini
te impulse response: hereinafter referred to as FIR. ) Type non-recursive digital filter, and by performing a calculation that causes a predetermined time difference between Rch and Lch of the audio signal, it is possible to improve the sense of difference in the sound field due to the audio signal. .

Digital signal processing apparatus 1 having the above configuration
According to 0, the digital information signal supplied by the rate conversion means 1 in synchronization with the sampling clock signal fs is sent to the signal processing means 5 in synchronization with the sample flag signal FS-FLG, and the signal processing means 5 Sample flag FS-
Signal processing of a digital information signal is performed in synchronization with FLG.
With such a simple configuration, the signal processing of the digital information signal is accurately performed according to the sampling frequency.

[0045]

As described in detail above, according to the digital signal processing device of the present invention, the digital information signal supplied in synchronization with the sampling clock signal by the rate conversion means is synchronized with the system clock signal. To the signal processing means, and the signal processing means performs signal processing of the digital information signal in synchronization with the system clock. For this reason,
It is possible to provide a digital signal processing device that has a simple configuration and accurately performs signal processing of a digital information signal according to a sampling frequency.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a DAT provided with a digital signal processing device according to the present invention.

FIG. 2 is a diagram showing a standard of a main part of a recording / playback mode and a playback only mode of the DAT.

FIG. 3 shows a schematic configuration diagram of a format of a digital information signal of one track of the DAT, FIG. 3A is a configuration diagram of a main data area, and FIGS. 3 is a configuration diagram of a sub data area provided in the empty area of FIG.

4A and 4B are schematic configuration diagrams of a format of one block of the main data of DAT, FIG. 4A is an overall diagram, FIG. 4B is a configuration diagram of main ID, and FIG. ) Is a figure which shows the function of each main ID.

5A and 5B are schematic configuration diagrams of a format of one block of DAT sub data, FIG. 5A is an overall diagram, and FIG. 5B is a configuration diagram of sub IDs.

FIG. 6 is a configuration diagram of a main part of a digital signal processing device according to the present invention.

FIG. 7 is a conceptual diagram of signals in a main part of the rate conversion means of the digital signal processing device when the sampling frequency is higher than the frequency of the system clock signal, and FIG. 7A is a diagram showing the system clock signal. Yes, FIG. 7B is a diagram in which the digital information signal supplied at the sampling frequency is displayed in analog, and FIG. 7C is a diagram in which the digital information signal to be output is displayed in analog.

[Explanation of symbols]

 1 rate conversion means 5 signal processing means 45 microcomputer

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[Procedure amendment]

[Submission date] December 18, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

Instruction address generator 1
6, the address is reset by the rising edge of the sampling clock, and
The address is incremented by 1 every instruction cycle.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Delete

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction content]

The coefficient selector 22 responds to the command signal supplied from the instruction memory 17 in accordance with
Main data MD1 supplied via the bus 30,
The coefficient of MD2 or the coefficient read from the coefficient memory 20 is selected and transmitted.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction content]

The data selector 23 is responsive to the command signal supplied from the instruction memory 17 to receive the main data MD supplied via the bus 30.
1, MD2 or the main data MD1 and MD2 read from the data memory 21 are selected and transmitted.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

The calculating means 9 multiplies the coefficient supplied from the coefficient selector 22 of the coefficient setting means 8 by the main data MD1 and MD2 supplied from the data selector 23, and the output of the multiplier 24. A shifter 25 that shifts a signal or holds it without shifting, and an adder 2 that supplies an output signal from the shifter 25 to one input terminal and adds the output signal and a signal supplied to another input terminal
6, an accumulator 27 for storing the output signal of the adder 26, and a signal stored in the accumulator 27 or 0.
A selector 28 for selecting and supplying to the other input terminal of the adder 26, and a clipper 29 for rounding the output signal of the accumulator 27 into the word length of the bus 30 and supplying it to the bus 30.

Claims (1)

[Claims] 1. A rate conversion means for latching the supplied digital information signal in synchronization with a sampling clock signal and transmitting the latched digital information signal in synchronization with a system clock signal, and the rate conversion means. Signal processing means for performing signal processing by synchronizing the digital information signal thus obtained with the system clock signal, and sampling clock varying means for variably setting the frequency of the sampling clock signal in accordance with the sampling frequency of the digital information signal. Digital signal processing device.