JPH08305630A - Digital signal processor - Google Patents

Abstract

PURPOSE: To provide a digital signal processor which can fast operate at low cost. CONSTITUTION: The digital signal processor consists of an address generation means 17 which transmits the addresses after increment of them, the 1st and 2nd latch circuits 31 and 32 which latch the addresses supplied from the means 17 with the timings alternate to each other, the 1st and 2nd memories 33 and 34 where the information signals are readably written in the addresses latched by both circuits 31 and 32, and an arithmetic means which applies the arithmetic operations to the information signals that are read out of both memories 33 and 34 with the timings alternate to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device, and more particularly to a digital signal processing device provided with a storage device for storing information signals.

[0002]

2. Description of the Related Art Today, it is provided in a computer, an image signal processing apparatus, an audio signal processing apparatus, etc., and performs predetermined signal processing of supplied digital information signals such as data, command signals, image signals and audio signals. Digital signal processing devices such as a digital signal processor (hereinafter, referred to as DSP) are in widespread use. The digital signal processing device includes a data memory that stores a digital information signal so that the digital information signal can be read out, and a computing unit that computes the digital information signal read from the data memory. It is composed of semiconductor elements.

In recent years, the amount of information signals has increased with the sophistication and quality of information, and the digital signal processing device is required to have a high operating speed and a large capacity of the data memory. To be done. On the other hand, in the digital signal processing device, the operation speed has been increased and the capacity of the data memory has been increased due to the progress of the semiconductor process technology in recent years.

[0004]

By the way, when the data memory is manufactured by using the semiconductor process technology for increasing the operation speed of the semiconductor element, the manufacturing cost becomes high and the digital signal processing device becomes expensive. Was causing problems. In addition, when the data memory is manufactured by a semiconductor process technology which is low in manufacturing cost, it is difficult to increase the operating speed of the digital signal processing device.

In view of the above problems, it is an object of the present invention to provide an inexpensive digital signal processing device which operates at high speed.

[0006]

The digital signal processing apparatus according to the present invention, which has achieved this object, has an address generating means for incrementing and transmitting an address and an address supplied from the address generating means at mutually alternating timings. First and second latch circuits for latching the first and second latch circuits, first and second memories in which an information signal is readably written at the address latched by the first and second latch circuits, and the first and second latch circuits. And an arithmetic unit for arithmetically operating the information signals read from the two memories at alternate timings.

[0007]

According to the digital signal processing device of the present invention having the above-described structure, the first and second memories have the first and second memories.
Information signals are written to and read from the mutually alternating addresses latched by the second latch circuit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a digital signal processing device according to the present invention will be described below with reference to the drawings.
The digital signal processing device is a digital audio tape recorder (hereinafter referred to as DA).
Called T. ) Is shown in FIG.

The DAT has a traveling means for traveling the magnetic tape 40 mounted thereon as shown in FIG. 1 so that the traveling direction and traveling speed of the magnetic tape 40 can be switched and set, and the magnetic tape traveling by the traveling means. A drum type rotary head 1 which records and reproduces an information signal for one track each time the main surface of 40 is rotated in the scanning direction, and PCM demodulation of the audio signal reproduced by the rotary head 1 to output a sound. Recording that records the supplied audio signal by PCM modulation
The reproducing means 2, a digital signal processing device 10 for signal-processing the information signal PCM demodulated by the recording / reproducing means 2 and supplying the signal signal to the recording / reproducing means 2, and the recording / reproducing means 2
And a microcomputer 3 for controlling the digital signal processing device 10, and a mode setting means 4 for setting control conditions in the microcomputer 3 according to the operation mode of the DAT.

The microcomputer 3 sets a sampling frequency in the recording / reproducing means 2 in accordance with the control condition set by the mode setting means 4 so that the recording / reproducing means 2 and the digital signal processing device 10 can be operated. It operates in synchronization with the sampling clock signal fs to cause the digital signal processing device 10 to perform signal processing according to the command signal.

The DAT standard has four recording / reproducing modes and two reproducing-only modes as shown in FIG. The recording / playback modes include a 48k mode with a sampling frequency of 48 KHz and a quantization bit number of 16 bits, a 32k mode with a sampling frequency of 32 KHz and a quantization bit number of 16 bits, and a quantization bit number of 12 bits. 32k-LP with 2 channels
It has a 32k-4CH mode in which the mode and the number of quantization bits are 12 bits and the number of channels is 4CH.
8k mode is mandatory as standard equipment, other modes are optional equipment.

In the reproduction-only mode, the sampling frequency is 44.1 KHz and the number of quantization bits is 1.
It has a 6-bit magnetic tape running speed and track pitch of standard 44k mode and a magnetic tape running speed and track pitch of 1.5 times standard 44k-WT mode. The mode also requires standard equipment.

In this DAT, the information signal of two tracks is set as one frame and the rotary head 1 drives the magnetic tape 40.
The digital information signal for each track is recorded in the main data area. The tracks of the one frame are interleaved with each other, and the interleaving is performed to disperse error information due to the positional deviation of the track position of the magnetic tape 40 and the rotary head 1 and the like. The lack of is suppressed.

As shown in FIG. 3A, the main data area is composed of 128 blocks, and a synchronization signal (SYNC), a main ID signal W1, and a main ID signal W are sequentially arranged from the beginning.
2. Main ID parity signal and main data MD1,
It is composed of MD2. The main data MD1 and the main data MD2 are composed of audio signals and are interleaved with each other. The interleaving gives the magnetic tape 40 from the rotary head 1.
The error information is suppressed by dispersing error information due to floating and the like, and the parity codes C1 and C2 by the dual (32.28) Reed-Solomon code are applied to enable error correction. Has become.

Further, the main data MD1 and M in the specifications of the respective recording / reproducing modes, such as the rotational speed of the rotary head 1 shown in FIG.
When D2 is recorded, an empty area is created in the main data MD1 and MD2 in any mode. In this empty area, as shown in FIGS. 3B and 3C, sub-data SD1 and SD2 each consisting of 8 blocks are recorded. Also,
Each of the main data MD1 and MD2 is divided into eight areas, and each block of sub-data SD1 and SD2 is sequentially allocated and recorded in each area of the divided main data MD1 and MD2. .

As shown in FIG. 4A, the format of one block of the main data MD1 and MD2 has a sync signal (SYN) in order from the beginning for each symbol (= 8 bits).
C), a main ID signal W1, a main ID signal W2, a main ID parity signal, and main data of 8 × 32 symbols.

As shown in FIG. 4B, the main ID signal W1 is composed of formats ID0 to ID7 in which specifications required for recording and reproduction are set, and a frame address assigned to each track in the running direction of the magnetic tape. To be done. For example, in the format ID2, the sampling frequency of the digital information signal is set as shown in FIG. 4C. The number of channels of main data in one track is set in the format ID3. A quantization rule such as the number of quantization bits is set in the format ID4. A track pitch is set in the format ID5.

In the main ID signal W2, as shown in FIG. 4B, block addresses for every 8 blocks from the beginning of each track are recorded. As shown in FIG. 5A, the format of one block in the sub-data area is 8 × 32, including a synchronization signal (SYNC), a sub-ID signal SW1, a sub-ID signal SW2 and a sub-ID parity signal in order from the beginning for each symbol. It is composed of symbol sub-data.

As shown in FIG. 5B, the sub ID signals SW1 and SW2 include a control ID, a data ID, a pack ID, programs ID1 to ID3, etc. in which data required for high speed search is set. The control ID
Is a table of contents that functions as a list of the beginning position of the song, the arrangement position of each movement, and the capacity.
Information (hereinafter referred to as TOC information) is set. The purpose of use of the sub ID signals SW1 and SW2 is set in the data ID. The configuration of the sub ID signals SW1 and SW2 and the arrangement of each data are set in the pack ID.
A program for editing or the like is set in each of the programs ID1 to ID3.

The digital signal processing apparatus 10 according to the present invention provided in the DAT has an interface 7 for inputting / outputting a digital information signal as shown in FIG. 6, and a predetermined digital information signal supplied from the interface 7. Coefficient setting means 8 for associating the coefficient of
Calculating means 9 for calculating the digital information signal and coefficient associated with each other, the interface 7, and coefficient setting means 8
And a bus 30 that connects the computing means 9 to each other.

The interface 7 has an input port 11 to which a digital information signal is supplied, and the input port 11
Input register 12 for sequentially sending the digital information signal supplied to the bus 30 to the bus 30 in synchronization with the sampling clock signal fs, and an output register to which the digital information signal is supplied from the bus 30 in synchronization with the sampling clock signal fs. 13 and an output port 14 for transmitting the digital information signal supplied from the output register 13.

The coefficient setting means 8 includes an instruction address generator 15 for generating an instruction address, an instruction memory 16 for reading out an instruction signal for each instruction address, and data for generating a data address according to the instruction signal. An address generator 17, a data memory 18 for writing a digital information signal for each data address supplied from the data address generator 17, and a digital information signal supplied from the data memory 18 or the bus 30 A data selector 19 for selecting and transmitting, and a coefficient address generator 20 for generating a coefficient address according to the instruction signal,
A coefficient memory 21 in which a coefficient is readably written for each coefficient address, and a coefficient selector 22 for selecting and transmitting the coefficient supplied from the coefficient memory 21 or the bus 30.
Have and.

The instruction address generator 1
An address reset signal 5 is reset by an address clear signal supplied from the DAT or an address clear signal supplied from the microcomputer 3 when the power supply of the DAT is turned on, and is counted in synchronization with the system clock signal SK of the DAT. The value is incremented by 1 to form the instruction address.

In the instruction memory 16, the instruction stored at the instruction address supplied from the instruction address generator 15 is read and sent to the data address generator 17 and the coefficient address generator 21.

As shown in FIG. 7, the data memory 18 includes first and second latch circuits 31 and 32 for latching the data addresses generated by the data address generator 17 at alternate timings. It has first and second memories that readably write the information signal supplied via the bus 30 at the data address latched by the first and second latch circuits 31 and 32.

The coefficient selector 22 selects the coefficient of the sub-data SD1 or SD2 supplied via the bus 30 or the coefficient read from the coefficient memory 21 according to the command signal supplied from the microcomputer 3. Select and send. The data selector 19 selects and sends the information signal supplied via the bus 30 or the information signal read from the data memory 18 in response to the command signal supplied from the microcomputer 3.

The calculation means 9 has a multiplier 23 for multiplying the coefficient supplied from the coefficient selector 22 of the coefficient setting means 8 by the information signal supplied from the data selector 19.
A shifter 24 that holds the output signal of the multiplier 23 while sequentially shifting it, and an addition that adds an output signal from the shifter 24 to one input terminal and adds the output signal and a signal supplied to another input terminal. 25, a second accumulator 27 for storing the output signal of the adder 25, and a second accumulator 27
Selector 28 for selecting the signal stored in the accumulator 27 or 0 and supplying it to the other input terminal of the adder 25,
The output signal of the second accumulator 27 is transferred to the bus 30.
Clipper 29 that is rounded to the word length and supplied to the bus 30
Have and.

As shown in FIG. 8, the coefficient setting means 8 and the arithmetic means 9 having the above-mentioned configuration have a system clock signal SK having a frequency which is an integral multiple of the sampling clock signal.
Is supplied, the instruction address generator 15 resets the address by the clear signal I-ADD CLR from DAT, and generates the address signal I-ADDGEN. Instruction memory 1 specified by the address signal I-ADDGEN
An instruction is generated from the address of 6. The data address generator 17 generates a data address according to the supplied instruction.

Next, in the data memory 18, the first latch circuit 31 latches the data address in synchronization with the rising edge of the switching signal 0/1 which is 1/2 the frequency of the system clock signal SK. . In addition, the second latch circuit 32 latches the data address in synchronization with the fall of the switching signal 0/1.

At the address latched by the first latch circuit 31 in the first memory 33, the information signal is stored in synchronization with the fall of the switching signal 0/1. Further, at the address latched by the second latch circuit 32 in the second memory 34, the information signal is stored in synchronization with the rising edge of the switching signal 0/1.

Next, the address is incremented in synchronization with the rising edge of the system clock signal SK, and the information signal is transferred from the first and second memories 33 and 34 in synchronization with mutually alternating addresses. Send to. This information signal passes through the adder 23, the shifter 24, and the adder 25, and the first and second accumulators 26,
27.

The first and second accumulators 26, 2
7, the first and second memories 3 of the data memory 18
When the information signal is read out in the reverse order stored in 3, 34, the information signal previously supplied to the first accumulator 26 is returned to the adder 25 via the selector 27 and again returned to the first accumulator 25. It is supplied to the accumulator 26. In addition, the information signal supplied to the first accumulator 26 later becomes the second signal.
By waiting until the previous information signal is supplied to the first accumulator 26 again by the accumulator 27 of
It is possible to correct in a normal order.

In the arithmetic means 9, for example, an impulse signal of an audio signal forming an 8-bit unit information signal for each sampling frequency fs is supplied from the selector 19, and a coefficient b of each impulse signal is supplied from the selector 22. The multiplier 23 sequentially multiplies the impulse signal by the coefficient b from the first impulse signal to the Nth delayed impulse signal, and adds the N + 1 multiplication results to the adder 2
5, and the second accumulator 27 sequentially convolves the addition result to output the impulse response H (Z) of the actual frequency characteristic shown in the following equation (1).

[0034]

[Equation 1]

As described above, the calculating means 9 functions as a finite impulse response (hereinafter referred to as FIR) type non-recursive digital filter,
By performing a calculation that causes a predetermined time difference between the Rch and the Lch of the audio signal, it is possible to improve the sense of difference in the sound field due to the audio signal.

Digital signal processing apparatus 1 having the above configuration
0 is the first and second memories 33 and 34 of the coefficient setting means 8.
In, the information signal is written and read to and from the alternating addresses latched by the first and second latch circuits 31 and 32, and the first and second memories 31 and 32 are operated in parallel. The operation speed can be increased even when a low-speed and inexpensive memory is used. Therefore, it is inexpensive and the operating speed is high.

[0037]

As described above in detail, according to the digital signal processing device of the present invention, the addresses alternately stored in the first and second memories are latched by the first and second latch circuits. Information signals are written and read.
As described above, since the first and second memories are operated in parallel, it is possible to increase the operation speed even when an inexpensive memory having a low operation speed is used. Therefore, it is possible to provide a digital signal processing device that is inexpensive and has a high operating speed.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a DAT provided with a digital signal processing device according to the present invention.

FIG. 2 is a diagram showing a standard of a main part of a recording / playback mode and a playback only mode of the DAT.

FIG. 3 shows a schematic configuration diagram of a format of a digital information signal of one track of the DAT, FIG. 3A is a configuration diagram of a main data area, and FIGS. 3 is a configuration diagram of a sub data area provided in the empty area of FIG.

4A and 4B are schematic configuration diagrams of a format of one block of the main data of DAT, FIG. 4A is an overall diagram, FIG. 4B is a configuration diagram of main ID, and FIG. ) Is a figure which shows the function of each main ID.

5A and 5B are schematic configuration diagrams of a format of one block of DAT sub data, FIG. 5A is an overall diagram, and FIG. 5B is a configuration diagram of sub IDs.

FIG. 6 is a schematic configuration diagram of a digital signal processing device according to the present invention.

FIG. 7 is a configuration diagram of a main part of the digital signal processing device.

FIG. 8 is a timing chart of a main part of the digital signal processing device.

[Explanation of symbols]

 8 Coefficient Setting Means 9 Arithmetic Means 31 First Latch Circuit 32 Second Latch Circuit 33 First Memory 34 Second Memory

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[Procedure amendment]

[Submission date] December 18, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

[0004]

By the way, when the above-mentioned data memory is manufactured by using the static memory which makes the operating speed of the above-mentioned semiconductor element high, the manufacturing cost becomes high and the digital signal processing apparatus becomes expensive. There was a problem. Further, when the data memory is manufactured by the dynamic memory, it is difficult to increase the operating speed of the digital signal processing device.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

In the digital signal processing apparatus according to the present invention which has achieved this object, the address generating means for incrementing and transmitting the address and the first for latching the address supplied from the address generating means at the timings alternating with each other. A second latch circuit, first and second memories in which readable information signals are written at addresses latched by the first and second latch circuits, and the first and second memories alternate with each other And a calculation means for calculating the information signal read at the timing of.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

[0007]

According to the digital signal processing device of the present invention having the above-described structure, the first and second memories have the first and second memories.
Information signals are written in and read from the addresses alternately generated by the second latch circuit.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

The instruction address generator 1
Address 6 is reset by an address clear signal generated by the rising edge of the sampling clock, and the count value is incremented by 1 in synchronization with the system clock signal SK of the DAT to obtain an instruction address.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0027

[Correction method] Change

[Correction content]

The calculation means 9 has a multiplier 23 for multiplying the coefficient supplied from the coefficient selector 22 of the coefficient setting means 8 by the information signal supplied from the data selector 19.
A shifter 24 that shifts the output signal of the multiplier 23 or holds it without shifting, and the shifter 24 at one input terminal.
An output signal is supplied from the adder 25, the adder 25 adds the output signal and a signal supplied to another input terminal, and the adder 25
Second accumulator 27 that stores the output signal of the selector 28 and a selector 28 that selects the signal stored in the second accumulator 27 or 0 and supplies it to the other input terminal of the adder 25.
And a clipper 29 that rounds the output signal of the second accumulator 27 to the word length of the bus 30 and supplies the word to the bus 30.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

As shown in FIG. 8, the coefficient setting means 8 and the arithmetic means 9 having the above-mentioned configuration are supplied with the system clock signal SK having a frequency which is an integral multiple of the sampling clock signal, and are generated by the rising edge of the sampling clock signal. The address of the instruction address generator 15 is reset by the generated signal I-ADDCLR, and the address signal I-ADDGEN is generated. An instruction is generated from the address of the instruction memory 16 designated by the address signal I-ADDGEN. The data address generator 17 generates a data address according to the supplied instruction.

Claims (1)

[Claims] 1. An address generating means for incrementing and transmitting an address, first and second latch circuits for latching an address supplied from said address generating means at mutually alternating timings, said first and second First and second information signals are written readable at the addresses latched in the latch circuit
And a computing means for computing the information signals read from the first and second memories at alternate timings.