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JPH08298299A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08298299A
JPH08298299A JP7103404A JP10340495A JPH08298299A JP H08298299 A JPH08298299 A JP H08298299A JP 7103404 A JP7103404 A JP 7103404A JP 10340495 A JP10340495 A JP 10340495A JP H08298299 A JPH08298299 A JP H08298299A
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
insulating layer
thermal expansion
resin mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7103404A
Other languages
Japanese (ja)
Inventor
Toshio Ogawa
敏夫 小川
Masaaki Takahashi
正昭 高橋
Noritaka Kamimura
典孝 神村
Masahiro Aida
正広 合田
Kuniyuki Eguchi
州志 江口
Kazuhiro Suzuki
和弘 鈴木
Motonobu Hattori
元信 服部
Hiroyuki Hanei
博幸 羽根井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7103404A priority Critical patent/JPH08298299A/en
Publication of JPH08298299A publication Critical patent/JPH08298299A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】 【構成】パワー半導体素子を含む回路部を、熱膨張係数
を特定した材質の樹脂系モールドで一体的に補強する。 【効果】小型,高密度の半導体装置を低価格で提供する
ことができる。
(57) [Summary] [Structure] The circuit part including the power semiconductor element is integrally reinforced by a resin mold of a material having a specified thermal expansion coefficient. [Effect] A compact and high-density semiconductor device can be provided at a low price.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子を含むチッ
プ部品が基板上に搭載され、導体回路に電気的に接続さ
れた半導体装置に係り、特に、能動素子としてのパワー
半導体素子を固着する金属ベース基板上の絶縁層の信頼
性を向上させた混成集積回路系パワー半導体装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a chip component including a semiconductor element is mounted on a substrate and electrically connected to a conductor circuit, and in particular, a power semiconductor element as an active element is fixed to the semiconductor device. The present invention relates to a hybrid integrated circuit power semiconductor device in which the reliability of an insulating layer on a metal base substrate is improved.

【0002】[0002]

【従来の技術】従来のこの種パワー半導体装置として次
の二つの構成がある。一つは特開昭62−2587号公報に開
示される。これは、金属板上に樹脂系絶縁層及び導体パ
ターンを形成した配線基板である。この導体パターン上
にパワー半導体素子などを固着することによって所定の
回路を構成し、ゲル状シリコン系樹脂で充填された構造
を有している。この構造を有する配線基板では、金属板
表面に均質で平坦な絶縁層を配置できるので、底部にコ
レクタ電極を有した非絶縁型パワー半導体素子を、ヒー
トスプレッダなどの導体層を介して直接固着することが
でき、導体配線を配置するときの設計自由度が高く、高
密度化もしくは小型化に有効である。しかし、次の欠点
を有している。パワー半導体素子と金属ベース基板との
間に樹脂層を介するため、この樹脂層が厚くなると熱抵
抗が大きくなってしまう。一方、通常使用される層厚1
00μm以下程度に薄くすると、半導体素子と金属ベー
ス基板との熱膨張係数の差に起因する温度変化時の内部
応力が、この樹脂層に集中し、クラックなどを発生して
絶縁特性が劣化しやすいという現象がある。
2. Description of the Related Art The conventional power semiconductor device of this type has the following two configurations. One is disclosed in Japanese Patent Laid-Open No. 62-2587. This is a wiring board in which a resin-based insulating layer and a conductor pattern are formed on a metal plate. A predetermined circuit is formed by fixing a power semiconductor element or the like on this conductor pattern, and has a structure filled with a gelled silicone resin. In a wiring board having this structure, a uniform and flat insulating layer can be arranged on the surface of the metal plate.Therefore, a non-insulated power semiconductor element having a collector electrode at the bottom should be directly fixed via a conductor layer such as a heat spreader. Therefore, there is a high degree of freedom in design when arranging conductor wiring, and it is effective for high density or miniaturization. However, it has the following drawbacks. Since the resin layer is interposed between the power semiconductor element and the metal base substrate, the thermal resistance increases as the resin layer becomes thicker. On the other hand, normally used layer thickness 1
When the thickness is reduced to about 00 μm or less, the internal stress at the time of temperature change due to the difference in thermal expansion coefficient between the semiconductor element and the metal base substrate is concentrated on the resin layer, and cracks or the like are likely to occur to easily deteriorate the insulation characteristics. There is a phenomenon.

【0003】他の一つは、特開昭64−42160 号及び特許
開平6−80748号公報に開示される。すなわち、金属のベ
ース基板上に、予め所定間隔の隙間を設けてパワー半導
体素子をセットし、この隙間を含むモールド層として樹
脂を流し込んで半導体装置を構成するものである。この
構造によれば、半導体素子を取り巻く構造体としての樹
脂層が多く存在するので、応力集中によるクラックは発
生しにくく、絶縁層として高い信頼性が得られる。しか
し、前述したように予め素子をセットした空間に樹脂を
流し込む方法であり、樹脂層の厚さが不安定になりやす
い。通常、この種樹脂層の熱伝導率は極めて低く、若干
の層厚の誤差が熱抵抗として大きなばらつきとなり、量
産工場での安定した品質を得るのが難しい。
The other one is disclosed in JP-A-64-42160 and JP-A-6-80748. That is, a power semiconductor element is set in advance on a metal base substrate with a predetermined gap, and a resin is poured as a mold layer including the gap to form a semiconductor device. According to this structure, since there are many resin layers as a structure surrounding the semiconductor element, cracks due to stress concentration are less likely to occur and high reliability as an insulating layer can be obtained. However, as described above, this is a method in which the resin is poured into the space in which the elements are set in advance, and the thickness of the resin layer tends to become unstable. Usually, the thermal conductivity of this kind of resin layer is extremely low, and a slight error in the layer thickness causes a large variation in thermal resistance, and it is difficult to obtain stable quality in a mass production factory.

【0004】[0004]

【発明が解決しようとする課題】本発明の目的は、高信
頼性かつ小型のパワー半導体装置を実現することにあ
る。すなわち、予め絶縁層を形成したいわゆる絶縁金属
基板を適用することによって、パワー半導体素子の下部
に均質で安定した層厚を有する絶縁層が配置でき、かつ
半導体素子周辺に多量の樹脂層を配置して、前述した温
度変化時の絶縁層への応力集中を緩和し、結果的に高信
頼性かつ小型のパワー半導体装置を提供する。
SUMMARY OF THE INVENTION An object of the present invention is to realize a highly reliable and compact power semiconductor device. That is, by applying a so-called insulating metal substrate on which an insulating layer is formed in advance, an insulating layer having a uniform and stable layer thickness can be arranged under the power semiconductor element, and a large amount of resin layer is arranged around the semiconductor element. Thus, the stress concentration on the insulating layer when the temperature changes as described above is relaxed, and as a result, a highly reliable and compact power semiconductor device is provided.

【0005】本発明の他の目的は、実用パワー半導体装
置に要求される、熱放散に好適で、かつ安定した熱抵抗
を有する構造を容易にかつ低価格で提供することにあ
る。
Another object of the present invention is to provide a structure suitable for heat dissipation required for a practical power semiconductor device and having a stable thermal resistance easily and at low cost.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明では次の手段をとる。
In order to achieve the above object, the present invention takes the following means.

【0007】(1)金属基体表面の少なくとも一面が有
機絶縁層によって予め被覆された絶縁金属基板の前記絶
縁層上に固着された能動素子及びもしくは受動素子と、
それを電気的に接続する導体回路及び外部との入出力用
端子とを有し、これら回路系が樹脂系モールドによって
保護された構造のパワー半導体装置において、前記樹脂
系モールドが一体的に構成され、前記モールドが実質的
に単一の樹脂層からなる構成の半導体装置とする。
(1) An active element and / or a passive element fixed on the insulating layer of an insulating metal substrate in which at least one surface of the metal substrate is previously coated with an organic insulating layer,
In a power semiconductor device having a conductor circuit for electrically connecting it and an input / output terminal with the outside, and the circuit system is protected by a resin mold, the resin mold is integrally configured. The semiconductor device is configured such that the mold is substantially composed of a single resin layer.

【0008】(2)(1)において、前記能動素子が、
非絶縁型パワー半導体素子で構成した半導体装置とす
る。
(2) In (1), the active element is
The semiconductor device is composed of a non-insulated power semiconductor element.

【0009】(3)(1)または(2)において、通常
の使用環境温度における熱膨張係数の比が、前記金属基
体に対して、前記有機絶縁層が最大1.2,最小0.5の
範囲に調節された半導体装置とする。
(3) In (1) or (2), the ratio of the coefficient of thermal expansion at a normal operating environment temperature is such that the organic insulating layer has a maximum of 1.2 and a minimum of 0.5 with respect to the metal substrate. The semiconductor device is adjusted to the range.

【0010】(4)(1)または(2)において、通常
の使用環境温度における熱膨張係数の比が、有機絶縁層
に対して、前記樹脂系モールドが最大1.5,最小0.5
の範囲に調節された半導体装置とする。
(4) In (1) or (2), the ratio of the coefficient of thermal expansion at a normal operating environment temperature is such that the resin-based mold has a maximum of 1.5 and a minimum of 0.5 with respect to the organic insulating layer.
The semiconductor device is adjusted to the range of.

【0011】(5)(1)または(2)において、通常
の使用環境温度における熱膨張係数の比が、金属基体に
対して、前記樹脂系モールドが最大1.2,最小0.5の
範囲に調節された半導体装置とする。
(5) In (1) or (2), the ratio of the coefficient of thermal expansion at a normal operating environment temperature is such that the resin-based mold has a maximum of 1.2 and a minimum of 0.5 with respect to the metal substrate. The semiconductor device is adjusted to.

【0012】(6)(1)または(2)において、通常
の使用環境温度における熱膨張係数の比が、金属基体に
対して、有機絶縁層が最大1.2,最小0.5の範囲に、
かつ前記樹脂系モールドが最大1.2,最小0.5の範囲
にそれぞれ調節された半導体装置とする。
(6) In (1) or (2), the ratio of the coefficient of thermal expansion at the normal operating environment temperature is such that the organic insulating layer has a maximum of 1.2 and a minimum of 0.5 with respect to the metal substrate. ,
In addition, the semiconductor device is such that the resin-based mold is adjusted to a maximum range of 1.2 and a minimum range of 0.5.

【0013】(7)(1)または(6)において、前記
金属基体がアルミニウムもしくは銅を主成分として構成
された半導体装置とする。
(7) In (1) or (6), the semiconductor device is such that the metal substrate is composed mainly of aluminum or copper.

【0014】(8)(1)または(7)において、前記
樹脂系モールドがエポキシ樹脂,フェノール樹脂,三酸
化アンチモン,エポキシシラン,エポキシ変性シロキサ
ン,酸化アルミニウム,酸化けい素のうちの少なくとも
二つを有効成分として含み、構成された半導体装置とす
る。
(8) In (1) or (7), the resin-based mold contains at least two of epoxy resin, phenol resin, antimony trioxide, epoxysilane, epoxy-modified siloxane, aluminum oxide, and silicon oxide. A semiconductor device is constituted by including as an active ingredient.

【0015】(9)(1)または(8)において、前記
絶縁金属基板上に前記パワー半導体素子を駆動する制御
系回路用チップ部品及びもしくは過電流,過温度などを
監視する保護系回路用チップ部品を含んで構成された半
導体装置とする。
(9) In (1) or (8), a chip part for a control system circuit for driving the power semiconductor element on the insulating metal substrate and / or a chip for a protection system circuit for monitoring overcurrent, overtemperature, etc. A semiconductor device including components is used.

【0016】[0016]

【作用】本発明の構成による作用は次のとおりである。The function of the present invention is as follows.

【0017】(1)金属基体表面の少なくとも一面が有
機絶縁層によって予め被覆された絶縁金属基板の絶縁層
上に固着された能動素子及びもしくは受動素子と、それ
を電気的に接続する導体回路及び外部との入出力用端子
とを有し、これら回路系が樹脂系モールドによって保護
された構造のパワー半導体装置において、樹脂系モール
ドが一体的に構成され、モールドが実質的に単一の樹脂
層いわゆる硬質樹脂によって構成されるので、金属板表
面に均質で平坦な絶縁層を配置でき、底部にコレクタ電
極を有した非絶縁型パワー半導体素子を、ヒートスプレ
ッダなどの導体層を介して直接固着することができ、導
体配線を配置するときの設計自由度が高く、高密度化も
しくは小型化に有効である。さらに、パワー半導体素子
を含む回路全体が単一のモールド樹脂層によって覆われ
ているために、有機絶縁層が補強され、絶縁層への応力
集中を緩和できる。通常、この有機絶縁層に要求される
材料特性として、十分な電気絶縁性に加えて良好な熱伝
導性がある。これを実現するため、一般には内部に多量
のフィラを含有している。従って応力により、クラック
を発生しやすい構成といえる。一方、モールド用樹脂に
ついては、熱伝導性を特別配慮する必要は無く、材料選
定の自由度が高い。従って、耐応力性の材料を選定でき
る。この材料によって有機絶縁層を補強することで、シ
リコンとの熱膨張係数の差に起因するクラックの発生な
どを抑制できる。
(1) An active element and / or a passive element fixed on the insulating layer of an insulating metal substrate, at least one surface of which is preliminarily covered with an organic insulating layer, and a conductor circuit for electrically connecting it In a power semiconductor device having a structure having an external input / output terminal and a circuit system protected by a resin mold, the resin mold is integrally configured, and the mold is substantially a single resin layer. Since it is composed of so-called hard resin, a uniform and flat insulating layer can be arranged on the surface of the metal plate, and a non-insulated power semiconductor element with a collector electrode at the bottom can be directly fixed via a conductor layer such as a heat spreader. Therefore, there is a high degree of freedom in design when arranging conductor wiring, and it is effective for high density or miniaturization. Furthermore, since the entire circuit including the power semiconductor element is covered with the single mold resin layer, the organic insulating layer is reinforced and stress concentration on the insulating layer can be relaxed. Usually, as a material property required for this organic insulating layer, there is a good thermal conductivity in addition to a sufficient electric insulating property. To achieve this, a large amount of filler is generally contained inside. Therefore, it can be said that the structure is likely to cause cracks due to stress. On the other hand, regarding the molding resin, it is not necessary to give special consideration to the thermal conductivity, and the degree of freedom in selecting the material is high. Therefore, a stress resistant material can be selected. By reinforcing the organic insulating layer with this material, it is possible to suppress the occurrence of cracks and the like due to the difference in thermal expansion coefficient from silicon.

【0018】(2)(1)において、予め絶縁層を形成
した金属基板上に能動素子を直接固着することができ、
非絶縁型パワー半導体素子の適用が可能である。従っ
て、絶縁型のみに限定されること無く、例えばパワート
ランジスタ,IGBTなど汎用パワー素子の搭載ができ
る。
(2) In (1), the active element can be directly fixed on the metal substrate on which the insulating layer is formed in advance.
A non-insulated type power semiconductor device can be applied. Therefore, general-purpose power elements such as power transistors and IGBTs can be mounted without being limited to the insulating type.

【0019】(3)(1)または(2)において、通常
の使用環境温度における熱膨張係数の比が、金属基体に
対して、有機絶縁層が最大1.2,最小0.5の範囲に調
節されるので、温度変化時の金属基体−有機絶縁層間の
熱膨張係数の差に起因する内部応力が緩和される。従っ
て、実使用環境を想定した熱サイクル試験などの繰り返
し熱負荷によっても、基板全体の反りもしくは局部的な
応力集中を抑制できる。
(3) In (1) or (2), the ratio of the coefficient of thermal expansion at the normal operating environment temperature is such that the organic insulating layer has a maximum of 1.2 and a minimum of 0.5 with respect to the metal substrate. Since the temperature is adjusted, the internal stress caused by the difference in the coefficient of thermal expansion between the metal substrate and the organic insulating layer when the temperature changes is relaxed. Therefore, it is possible to suppress warpage of the entire substrate or local stress concentration even by repeated heat loads such as a heat cycle test assuming an actual use environment.

【0020】(4)(1)または(2)において、通常
の使用環境温度における熱膨張係数の比が、有機絶縁層
に対して、樹脂系モールドが最大1.5,最小0.5の範
囲に調節されるので、有機絶縁層−樹脂系モールド層間
の熱膨張係数の差に起因する内部応力が緩和される。従
って、実使用環境を想定した熱サイクル試験などの繰り
返し熱負荷によっても、基板全体の反りもしくは局部的
な応力集中を抑制できる。
(4) In (1) or (2), the ratio of the coefficient of thermal expansion at a normal operating environment temperature is such that the resin-based mold has a maximum of 1.5 and a minimum of 0.5 with respect to the organic insulating layer. Therefore, the internal stress due to the difference in thermal expansion coefficient between the organic insulating layer and the resin-based mold layer is relaxed. Therefore, it is possible to suppress warpage of the entire substrate or local stress concentration even by repeated heat loads such as a heat cycle test assuming an actual use environment.

【0021】(5)(1)または(2)において、通常
の使用環境温度における熱膨張係数の比が、金属基体に
対して、樹脂系モールドが最大1.2,最小0.5の範囲
に調節されるので、金属基体−樹脂系モールド層間の熱
膨張係数の差に起因する内部応力が緩和される。従っ
て、実使用環境を想定した熱サイクル試験などの繰り返
し熱負荷によっても、基板全体の反りもしくは局部的な
応力集中を抑制できる。
(5) In (1) or (2), the ratio of the coefficient of thermal expansion at a normal operating environment temperature is within the range of 1.2 for resin molds and 0.5 for metal bases. Since it is adjusted, the internal stress caused by the difference in the coefficient of thermal expansion between the metal substrate and the resin-based mold layer is relaxed. Therefore, it is possible to suppress warpage of the entire substrate or local stress concentration even by repeated heat loads such as a heat cycle test assuming an actual use environment.

【0022】(6)(1)または(2)において、通常
の使用環境温度における熱膨張係数の比が、金属基体に
対して、有機絶縁層が最大1.2,最小0.5の範囲に、
かつ樹脂系モールドが最大1.2,最小0.5の範囲にそ
れぞれ調節されるので、金属基体−有機絶縁層−樹脂系
モールド層間の熱膨張係数の差に起因する内部応力が緩
和される。従って、実使用環境を想定した熱サイクル試
験などの繰り返し熱負荷によっても、基板全体の反りも
しくは局部的な応力集中を抑制できる。
(6) In (1) or (2), the ratio of the coefficient of thermal expansion at a normal operating environment temperature is such that the organic insulating layer has a maximum of 1.2 and a minimum of 0.5 with respect to the metal substrate. ,
In addition, since the resin-based mold is adjusted to a maximum range of 1.2 and a minimum range of 0.5, the internal stress caused by the difference in the thermal expansion coefficient between the metal substrate-organic insulating layer-resin-based mold layer is relaxed. Therefore, it is possible to suppress warpage of the entire substrate or local stress concentration even by repeated heat loads such as a heat cycle test assuming an actual use environment.

【0023】(7)(1)または(6)において、金属
基体がアルミニウムもしくは銅を主成分として構成され
る。これら材料は熱伝導性が良好で、熱放散性が良く、
材料価格も低い。
(7) In (1) or (6), the metal substrate is composed mainly of aluminum or copper. These materials have good thermal conductivity, good heat dissipation,
Material prices are also low.

【0024】(8)(1)または(7)において、樹脂
系モールドがエポキシ樹脂,フェノール樹脂,三酸化ア
ンチモン,エポキシシラン,エポキシ変性シロキサン,
酸化アルミニウム,酸化けい素のうちの少なくとも二つ
を有効成分として含むことにより、上記熱膨張係数の好
ましい範囲に調節することができる。さらに、成形性及
び耐湿性など一般にモールド用樹脂に要求される基本的
特性を満足できる。
(8) In (1) or (7), the resin mold is epoxy resin, phenol resin, antimony trioxide, epoxysilane, epoxy-modified siloxane,
By including at least two of aluminum oxide and silicon oxide as an active ingredient, the thermal expansion coefficient can be adjusted to a preferable range. Further, it can satisfy the basic properties generally required for molding resins such as moldability and moisture resistance.

【0025】(9)(1)または(8)において、絶縁
金属基板上にパワー半導体素子を駆動する制御系回路用
チップ部品及びもしくは過電流,過温度などを監視する
保護系回路用チップ部品を含んで構成することにより、
インバータとしての機能が構造的に一体化できる。従っ
て、部品間の配線長を最小限に短縮でき、装置の小型化
及びノイズの低減ができる。
(9) In (1) or (8), a chip part for a control system circuit for driving a power semiconductor element and / or a chip part for a protection system circuit for monitoring overcurrent, overtemperature and the like are mounted on an insulating metal substrate. By including it,
The function as an inverter can be structurally integrated. Therefore, the wiring length between components can be shortened to the minimum, and the device can be downsized and noise can be reduced.

【0026】[0026]

【実施例】以下、本発明を実施例によってさらに詳細に
説明する。
EXAMPLES The present invention will now be described in more detail by way of examples.

【0027】(実施例1)図1に本発明の一実施例によ
る断面図を示す。例えば、IGBT(InsulatedGate Bip
olar Transistor)などのパワー半導体素子11がヒート
スプレッダ12を介して導体パターン13上に固着され
る。本構造のパワー半導体装置は次の工程によって作製
される。アルミニウムを主成分とする厚さ2.5mm,幅
55mm,長さ72mmの金属ベース基板15の片面に、厚
さ100μmのエポキシ系絶縁層14を熱圧着して絶縁
基板を作製する。絶縁層14の熱伝導性を改善する目的
から、少なくとも60vol% のアルミナもしくは酸化け
い素などのフィラを含有させる。この金属基板の絶縁層
上に、めっきもしくは熱圧着などの手段により銅導体層
を形成する。この銅導体層を選択的にエッチング除去
し、所定形状を有する導体パターン13を形成する。
(Embodiment 1) FIG. 1 is a sectional view showing an embodiment of the present invention. For example, IGBT (Insulated Gate Bip
A power semiconductor element 11 such as an orange transistor is fixed on the conductor pattern 13 via the heat spreader 12. The power semiconductor device having this structure is manufactured by the following steps. An epoxy-based insulating layer 14 having a thickness of 100 μm is thermocompression-bonded to one surface of a metal base substrate 15 having a thickness of 2.5 mm, a width of 55 mm, and a length of 72 mm, which is mainly composed of aluminum, to produce an insulating substrate. For the purpose of improving the thermal conductivity of the insulating layer 14, at least 60 vol% of filler such as alumina or silicon oxide is contained. A copper conductor layer is formed on the insulating layer of the metal substrate by plating or thermocompression. This copper conductor layer is selectively removed by etching to form a conductor pattern 13 having a predetermined shape.

【0028】一方、銅のチップからなるヒートスプレッ
ダ12上にパワー半導体素子11を95Pb−5Snな
どの高温半田21で接合する。この接合部材を予め準備
した導体パターン上に、例えば60Sn−40Pbなど
の低温半田20で固着する。この時、回路形成に必要な
他のコンデンサ,抵抗体などの他のチップ部品及び出力
端子16,入力端子17などを同時に接合しても良い。
On the other hand, the power semiconductor element 11 is joined to the heat spreader 12 made of a copper chip with a high temperature solder 21 such as 95Pb-5Sn. This joining member is fixed on a conductor pattern prepared in advance with a low temperature solder 20 such as 60Sn-40Pb. At this time, other chip parts such as capacitors and resistors necessary for forming a circuit and the output terminal 16 and the input terminal 17 may be simultaneously joined.

【0029】この工程で準備された一連の回路を、所定
温度に設定した金型中にセットし、射出法によって樹脂
モールド18を成形し、本発明によるパワー半導体装置
を得る。本実施例では、モールド18材料として表1を
用いた。
The series of circuits prepared in this step is set in a mold set to a predetermined temperature and a resin mold 18 is molded by an injection method to obtain a power semiconductor device according to the present invention. In this example, Table 1 was used as the material of the mold 18.

【0030】[0030]

【表1】 [Table 1]

【0031】表1の配合割合は重量比で示す。The blending ratios in Table 1 are shown by weight ratio.

【0032】比較のため、従来法によるパワー半導体装
置を図2に示す。従来法による構造では、モールドケー
ス22,端子ブロック23などを個別に作製する必要が
あり、加えてゲル24充填−硬化など、本発明に比較し
て多くの工程が必要である。 (実施例2)実施例1と同様の条件で、絶縁層14及び
樹脂モールド18の材料を変えて、熱膨張係数の異なる
複数のサンプルを作製し、これらサンプルの初期状態に
おける、金属ベース基板15の反り量を評価した。その
結果を表2に示す。
For comparison, a conventional power semiconductor device is shown in FIG. In the structure according to the conventional method, the mold case 22, the terminal block 23 and the like need to be individually manufactured, and in addition, many steps such as filling and curing of the gel 24 are required as compared with the present invention. (Example 2) Under the same conditions as in Example 1, the materials of the insulating layer 14 and the resin mold 18 were changed to prepare a plurality of samples having different thermal expansion coefficients, and the metal base substrate 15 in the initial state of these samples was prepared. The amount of warp was evaluated. The results are shown in Table 2.

【0033】[0033]

【表2】 [Table 2]

【0034】反り量は三次元デジタル位置測定装置によ
って測定し、最も低い点と高い点との差の絶対値で表現
した。反りが大きいと、冷却フィン35との熱抵抗が上
昇し、実用上問題となるため、反りの最大許容量は80
μmとした。表2の結果から、金属ベース基板15に対
応する、絶縁層14及び樹脂モールド18の好ましい熱
膨張係数の範囲が得られた。
The amount of warpage was measured by a three-dimensional digital position measuring device and expressed as the absolute value of the difference between the lowest point and the highest point. If the warp is large, the thermal resistance with the cooling fins 35 increases, which poses a practical problem. Therefore, the maximum allowable warp is 80.
μm. From the results in Table 2, the range of preferable thermal expansion coefficients of the insulating layer 14 and the resin mold 18 corresponding to the metal base substrate 15 was obtained.

【0035】(実施例3)実施例1で作製した、本発明
による図1に示す構造のパワー半導体装置と、樹脂モー
ルド18以外はほぼ同様の条件で作製した図2の構造の
もの両者を対象として、次の熱サイクル試験によって信
頼性の比較を試みた。条件は、125℃60分−25℃
30分−零下40℃60分−25℃30分の繰り返しと
した。評価は金属ベース基板15及び導体パターン13
間の破壊限界電圧の経時変化を測定した。その結果を図
3に示す。従来法によるものは、繰り返し数300サイ
クルを越えると破壊電圧が急峻に低下してしまう。一
方、本発明によるものは、2000サイクルでも2kV
以上を維持しており、実用可能な領域にある。この原因
を知る目的で、両サンプルの断面をSEMによって観察
した。その結果従来法によるものは、半導体チップ直下
部の絶縁層14に微細なクラックの発生が観察された。
破壊電圧の低下はこのクラックが原因と考えられる。
(Embodiment 3) Both the power semiconductor device having the structure shown in FIG. 1 according to the present invention manufactured in Embodiment 1 and the structure shown in FIG. 2 manufactured under substantially the same conditions except for the resin mold 18 are targeted. As a result, an attempt was made to compare reliability by the following heat cycle test. Conditions are 125 ° C 60 minutes -25 ° C
30 minutes-under zero 40 ° C 60 minutes-25 ° C 30 minutes. Evaluation is based on the metal base substrate 15 and the conductor pattern 13.
The change with time of the breakdown limit voltage during the period was measured. The result is shown in FIG. With the conventional method, the breakdown voltage drops sharply when the number of repetitions exceeds 300 cycles. On the other hand, according to the present invention, 2 kV is obtained even after 2000 cycles.
The above has been maintained and is in a practical area. In order to know the cause of this, the cross sections of both samples were observed by SEM. As a result, in the conventional method, generation of fine cracks was observed in the insulating layer 14 immediately below the semiconductor chip.
This crack is considered to be the cause of the decrease in breakdown voltage.

【0036】有限要素法による内部応力シミュレーショ
ンの結果次のことが分かった。従来法によるものには、
シリコンチップで構成する半導体素子11と,金属ベー
ス基板15との熱膨張係数の差によって、温度変化に伴
う寸法変化量に差を生じる。その結果、両材料の中間に
位置するに絶縁層14に応力集中部が発生する。ところ
が、本発明による構造では、半導体素子11の周辺が、
金属ベース基板15と熱膨張係数の差が小さい樹脂モー
ルド18で覆われているため、こうした応力集中部の発
生が大幅に抑制される。
As a result of the internal stress simulation by the finite element method, the following was found. According to the conventional method,
A difference in the coefficient of thermal expansion between the semiconductor element 11 formed of a silicon chip and the metal base substrate 15 causes a difference in the amount of dimensional change due to a temperature change. As a result, a stress concentration part is generated in the insulating layer 14 at a position intermediate between the two materials. However, in the structure according to the present invention, the periphery of the semiconductor element 11 is
Since the metal base substrate 15 and the resin mold 18 having a small difference in thermal expansion coefficient from each other are covered, the occurrence of such stress concentration portions is significantly suppressed.

【0037】(実施例4)図1に示す実施例1の本発明
によるパワー半導体装置を基礎として、インバータを試
作した。その断面図を図4に、回路ブロック図を図5に
それぞれ示す。本実施例では、図1の構成の他に、ゲー
ト駆動用IC31,平滑コンデンサ32、及び整流回路
用コンデンサブリッジ33などを加え、制御用マイコ
ン,電源回路34等を付加してインバータモジュールを
構成したものである。
(Embodiment 4) An inverter was prototyped based on the power semiconductor device according to the present invention of Embodiment 1 shown in FIG. The cross-sectional view is shown in FIG. 4 and the circuit block diagram is shown in FIG. In this embodiment, in addition to the configuration shown in FIG. 1, a gate driving IC 31, a smoothing capacitor 32, a rectifying circuit capacitor bridge 33, etc. are added, and a control microcomputer, a power supply circuit 34, etc. are added to form an inverter module. It is a thing.

【0038】本試作インバータを三相インダクションモ
ータに接続し、良好な特性を得ることを確認した。温度
変化を伴う繰り返し使用による信頼性も高いことがわか
った。
It was confirmed that the prototype inverter was connected to a three-phase induction motor to obtain good characteristics. It was also found that reliability is high due to repeated use with temperature changes.

【0039】[0039]

【発明の効果】以上説明したように、本発明によれば次
の効果がある。
As described above, the present invention has the following effects.

【0040】(1)均質で層厚の薄い有機絶縁層14上
に、パワー半導体装置11を固着し、全体を樹脂モール
ド18で補強する構造を有するため、低い熱抵抗と,高
い信頼性を同時に実現する。
(1) Since the power semiconductor device 11 is fixed onto the homogeneous and thin organic insulating layer 14 and the whole is reinforced by the resin mold 18, low thermal resistance and high reliability are achieved at the same time. To be realized.

【0041】(2)パワー半導体素子11として絶縁形
の他、非絶縁形のパワー素子を適用でき、回路構成上自
由度が高く、小型化及び高密度化しやすい。
(2) As the power semiconductor element 11, not only an insulating type but also an non-insulating type power element can be applied, which has a high degree of freedom in terms of circuit configuration, and is easy to be miniaturized and highly integrated.

【0042】(3)金属ベース基板15の熱膨張係数1
に対して、有機絶縁層14のそれが1.2〜0.5の範囲
にあるので、温度変化時の内部応力を抑制する。
(3) Coefficient of thermal expansion 1 of the metal base substrate 15
On the other hand, since the organic insulating layer 14 has a thickness in the range of 1.2 to 0.5, the internal stress when the temperature changes is suppressed.

【0043】(4)有機絶縁層14の熱膨張係数1に対
して、樹脂モールド層18のそれが1.5〜0.5の範囲
にあるので、温度変化時の内部応力を抑制する。
(4) Since the resin mold layer 18 has a coefficient of thermal expansion of 1 in the range of 1.5 to 0.5 with respect to the coefficient of thermal expansion of the organic insulating layer 14, the internal stress when the temperature changes is suppressed.

【0044】(5)金属ベース基板15の熱膨張係数1
に対して、樹脂モールド層18のそれが1.2〜0.5の
範囲にあるので、温度変化時の内部応力を抑制する。
(5) Coefficient of thermal expansion 1 of the metal base substrate 15
On the other hand, since the resin mold layer 18 has a thickness in the range of 1.2 to 0.5, the internal stress when the temperature changes is suppressed.

【0045】(6)金属ベース基板15の熱膨張係数1
に対して、樹脂モールド層18のそれが1.2〜0.5の
範囲にあるので、温度変化時の内部応力を抑制する。
(6) Coefficient of thermal expansion 1 of the metal base substrate 15
On the other hand, since the resin mold layer 18 has a thickness in the range of 1.2 to 0.5, the internal stress when the temperature changes is suppressed.

【0046】(7)金属ベース基板15用材料としてア
ルミニウムもしくは銅を主成分とするので、低熱抵抗か
つ低価格を実現する。
(7) Since the material for the metal base substrate 15 is mainly composed of aluminum or copper, low thermal resistance and low price are realized.

【0047】(8)樹脂モールド材料としてエポキシ樹
脂,フェノール樹脂,三酸化アンチモン,エポキシシラ
ン,エポキシ変性シロキサン,酸化アルミニウム,酸化
けい素のうちの二つを含むので、熱膨張係数を上記本発
明の好ましい範囲に調整でき、かつ、成形性及び樹脂モ
ールドに要求される基本的特性を実現する。
(8) Since the resin mold material contains two of epoxy resin, phenol resin, antimony trioxide, epoxysilane, epoxy-modified siloxane, aluminum oxide, and silicon oxide, the thermal expansion coefficient of the present invention is the same as that of the present invention. It can be adjusted to a preferable range and realizes the basic characteristics required for moldability and resin molding.

【0048】(9)小型,高密度インバータモジュール
を実現するという効果があり、例えばモータと一体化し
た構造のインバータが得られる。
(9) There is an effect of realizing a compact and high-density inverter module, and for example, an inverter having a structure integrated with a motor can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例によるパワー半導体装置の断
面図。
FIG. 1 is a sectional view of a power semiconductor device according to an embodiment of the present invention.

【図2】従来の構成によるパワー半導体装置の断面図。FIG. 2 is a sectional view of a power semiconductor device having a conventional configuration.

【図3】破壊限界電圧の比較図。FIG. 3 is a comparison diagram of breakdown limit voltages.

【図4】本発明の一実施例によるインバータモジュール
の断面図。
FIG. 4 is a sectional view of an inverter module according to an embodiment of the present invention.

【図5】本発明の一実施例によるインバータモジュール
の回路ブロック図。
FIG. 5 is a circuit block diagram of an inverter module according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11…パワー半導体素子、13…導体パターン、14…
絶縁層、15…金属ベース基板、16…出力端子、17
…入力端子、18…樹脂モールド、19…ボンデングワ
イヤ、20…低温半田、21…高温半田。
11 ... Power semiconductor element, 13 ... Conductor pattern, 14 ...
Insulating layer, 15 ... Metal base substrate, 16 ... Output terminal, 17
Input terminals, 18 resin molds, 19 bonding wires, 20 low temperature solders, 21 high temperature solders.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 合田 正広 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 江口 州志 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 鈴木 和弘 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 服部 元信 千葉県習志野市東習志野七丁目1番1号 株式会社日立製作所産業機器事業部内 (72)発明者 羽根井 博幸 千葉県習志野市東習志野七丁目1番1号 株式会社日立製作所産業機器事業部内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masahiro Goda, Inventor Masahiro Goda 7-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Research Laboratory, Hitachi, Ltd. 1-1 Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Kazuhiro Suzuki Kazuhiro Suzuki 1-1-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Motonobu Hattori Narashino Chiba Prefecture 7-1-1 Higashi Narashino, Higashi Narashino Industrial Equipment Division, Hitachi, Ltd. (72) Inventor Hiroyuki Hanai 7-1-1 Higashi Narashino, Narashino, Chiba Prefecture Industrial Equipment Division, Hitachi, Ltd.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】金属基体表面の少なくとも一面が有機絶縁
層によって、予め被覆された絶縁金属基板の前記有機絶
縁層上に固着された能動素子及びもしくは受動素子と、
それを電気的に接続する導体回路及び外部との入出力用
端子とを有し、これら回路系が樹脂系モールドによって
保護された構造のパワー半導体装置において、前記樹脂
系モールドが一体的に構成され、前記モールドが実質的
に単一の樹脂層からなることを特徴とする半導体装置。
1. An active element and / or a passive element fixed on the organic insulating layer of an insulating metal substrate, at least one surface of which is precoated with an organic insulating layer.
In a power semiconductor device having a conductor circuit for electrically connecting it and an input / output terminal with the outside, and the circuit system is protected by a resin mold, the resin mold is integrally configured. A semiconductor device, wherein the mold comprises a substantially single resin layer.
【請求項2】請求項1において、前記能動素子が、非絶
縁型パワー半導体素子である半導体装置。
2. The semiconductor device according to claim 1, wherein the active element is a non-insulated power semiconductor element.
【請求項3】請求項1または請求項2において、通常の
使用環境温度における熱膨張係数の比が、前記金属基体
に対して、前記有機絶縁層が最大1.2,最小0.5の範
囲に調節された半導体装置。
3. The ratio of the coefficient of thermal expansion at a normal operating environment temperature is in the range of maximum 1.2 and minimum 0.5 of the organic insulating layer with respect to the metal substrate according to claim 1 or 2. Adjusted semiconductor device.
【請求項4】請求項1または請求項2において、通常の
使用環境温度における熱膨張係数の比が、前記有機絶縁
層に対して、前記樹脂系モールドが最大1.5,最小0.
5の範囲に調節された半導体装置。
4. The resin mold according to claim 1 or 2, wherein the ratio of the coefficient of thermal expansion at a normal operating environment temperature is 1.5 at the resin mold and 0.5 at the minimum.
A semiconductor device adjusted to a range of 5.
【請求項5】請求項1または請求項2において、通常の
使用環境温度における熱膨張係数の比が、前記金属基体
に対して、前記樹脂系モールドが最大1.2,最小0.5
の範囲に調節された半導体装置。
5. The resin mold according to claim 1, wherein the ratio of the coefficient of thermal expansion at a normal operating environment temperature is 1.2 at the maximum and 0.5 at the minimum with respect to the metal substrate.
Device adjusted to the range of.
【請求項6】請求項1または請求項2において、通常の
使用環境温度における熱膨張係数の比が、前記金属基体
に対して、前記有機絶縁層が最大1.2,最小0.5の範
囲に、前記樹脂系モールドが最大1.2,最小0.5の範
囲にそれぞれ調節された半導体装置。
6. The ratio of coefficient of thermal expansion at a normal operating environment temperature in the claim 1 or claim 2 is such that the organic insulating layer has a maximum of 1.2 and a minimum of 0.5 with respect to the metal substrate. A semiconductor device in which the resin mold is adjusted to a maximum range of 1.2 and a minimum range of 0.5.
【請求項7】請求項1または請求項6において、前記金
属基体がアルミニウムもしくは銅を主成分として構成さ
れた半導体装置。
7. The semiconductor device according to claim 1 or 6, wherein the metal substrate is composed mainly of aluminum or copper.
【請求項8】請求項1または請求項7において、前記樹
脂系モールドが、エポキシ樹脂,フェノール樹脂,三酸
化アンチモン,エポキシシラン,エポキシ変性シロキサ
ン,酸化アルミニウム,酸化けい素のうちの少なくとも
二つを有効成分として含む半導体装置。
8. The resin mold according to claim 1 or 7, wherein at least two of epoxy resin, phenol resin, antimony trioxide, epoxysilane, epoxy-modified siloxane, aluminum oxide and silicon oxide are used. A semiconductor device containing an active ingredient.
【請求項9】請求項1または請求項8において、前記絶
縁金属基体上に前記パワー半導体素子を駆動する制御系
回路用チップ部品及びもしくは過電流,過温度などを監
視する保護系回路用チップ部品を含んで構成された半導
体装置。
9. The chip component for a control system circuit for driving the power semiconductor device and / or the chip component for a protection system circuit for monitoring overcurrent, overtemperature, etc. according to claim 1 or 8. A semiconductor device configured to include.
JP7103404A 1995-04-27 1995-04-27 Semiconductor device Pending JPH08298299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7103404A JPH08298299A (en) 1995-04-27 1995-04-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7103404A JPH08298299A (en) 1995-04-27 1995-04-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH08298299A true JPH08298299A (en) 1996-11-12

Family

ID=14353122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7103404A Pending JPH08298299A (en) 1995-04-27 1995-04-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH08298299A (en)

Cited By (13)

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EP0936671A1 (en) * 1998-02-12 1999-08-18 Hitachi, Ltd. Resin-moulded semiconductor hybrid module and manufacturing method thereof
EP1032042A3 (en) * 1999-02-22 2003-01-02 Hitachi, Ltd. Semiconductor module, power converter using the same and manufacturing method thereof
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Publication number Priority date Publication date Assignee Title
EP0936671A1 (en) * 1998-02-12 1999-08-18 Hitachi, Ltd. Resin-moulded semiconductor hybrid module and manufacturing method thereof
US6291880B1 (en) 1998-02-12 2001-09-18 Hitachi, Ltd. Semiconductor device including an integrally molded lead frame
EP1032042A3 (en) * 1999-02-22 2003-01-02 Hitachi, Ltd. Semiconductor module, power converter using the same and manufacturing method thereof
JP2003017631A (en) * 2001-06-28 2003-01-17 Sanyo Electric Co Ltd Hybrid integrated circuit device and manufacturing method therefor
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JP2006100759A (en) * 2004-08-31 2006-04-13 Sanyo Electric Co Ltd Circuit device and its manufacturing method
JP2006100752A (en) * 2004-09-30 2006-04-13 Sanyo Electric Co Ltd Circuit arrangement and its manufacturing method
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