JPH08297581A - Interruption management system of real-time operating system - Google Patents

Abstract

PURPOSE: To process an interruption which need not issue a system call without any delay by a system which is controlled by the real-time OS by enabling an interruption which exerts no influence on resource management by the OS to be initiated during system call processing. CONSTITUTION: A specific interruption operation processing means 14 which operates an interruption mask table 30 in an interruption controller 12 is provided in the OS 6, and only information regarding interruptions to be managed by the OS 6 is stored in a managed interruption storage means 9. In a section wherein exclusive control during the system call processing of the OS 6 is performed, only interruptions whose information is stored in the managed interruption storage means 9 are inhibited from being initiated and interruptions which issue no system call are allowed continuously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt management system in a real-time operating system (real-time OS).

[0002]

2. Description of the Related Art In a computer system in which resources and processes are managed by a real-time OS, interrupt processing for asynchronous interrupts caused by various factors is also managed by the real-time OS.
Software routines that perform interrupt processing are generally called interrupt handlers. In a conventional computer system controlled by a real-time OS, all interrupts are generally managed collectively by this real-time OS in order to enable all interrupt handlers to issue system calls to the OS. Target.
A system call is an instruction issued by a task or an interrupt handler to request a service supplied by the OS.

FIG. 9 shows a computer system controlled by a conventional real-time OS. CPU
To the (central processing unit) 51, an interrupt controller 50 that notifies the CPU 51 of the occurrence of an interrupt and a main storage device 40 are connected. Interrupt controller 50
An interrupt A from the interrupt factor 48 and an interrupt B from the interrupt factor 49 are input to the. An OS (operating system) 45 is resident in the main memory 40, and a routine 41 of task A, a routine 42 of task B, an interrupt handler 44 activated by interrupt A, and an interrupt handler 44 activated by interrupt B. The interrupt handler 43 is expanded. Among them, the interrupt handler 44 corresponding to the interrupt A executes the OS 45 by executing its software routine.
However, the interrupt handler 43 corresponding to the interrupt B does not issue the system call in its software routine. Further, inside the OS 45, an interrupt prohibition processing means 46 for setting the CPU 51 in the interrupt prohibition state, and the CPU 5
Interrupt permission processing means 47 for setting 1 to the interrupt enable state
It is included.

By the way, in the routine (system call processing routine) executed by the OS in response to the issuance of the system call, the same resources are operated by the system calls issued from different interrupt handlers.
Some require exclusive control to prevent inconsistencies in resources. This exclusive control is realized by setting a specific section of the system call process as an interrupt-disabled section and preventing the CPU 51 from accepting an interrupt during the execution of the routine in this section.

The interrupt processing in the above computer system will be described below with reference to FIG. Here, a system call to the OS 45 is issued by the task A during the execution of the task A, and the interrupt A is input to the interrupt controller 50 from the interrupt factor 48 within the interrupt prohibited section during the processing of the system call. A case where the interrupt B is input to the interrupt controller 50 from 49 will be described. In FIG. 10, a bold line indicates which routine the CPU 51 is executing. Further, EI indicates an interrupt enable section, and DI indicates an interrupt disable section.

Assuming that the interrupt is enabled, task A
It is assumed that a system call to the OS 45 is issued at time 52 during execution of the routine 41. as a result,
The processing by the CPU 51 transits to the OS 45 and system call processing is performed. Since the exclusive control as described above is performed by the processing in the OS 45, the interrupt prohibition processing unit 46 executes the interrupt prohibition processing at time 53, and the interrupt prohibition section starts. The interrupt prohibition process is performed, for example, by executing the interrupt prohibition instruction (DI) of the CPU 51.

When an interrupt A from the interrupt factor 48 is input to the interrupt controller 50 at time 54 in the interrupt prohibited section during the system call processing, the interrupt controller 50 outputs an interrupt request to the CPU 51. However, since interrupts are disabled here, the CPU 51 causes the interrupt handler 44 to
(F) The system call processing is continued without transferring the processing. Furthermore, the time 55 during this interrupt-disabled section
When the interrupt B from the interrupt factor 49 which is another interrupt factor is input to, the same as in the case of the interrupt A,
Interrupt handler processing is suspended. The interrupt handler 43 does not issue a system call inside, and even if the interrupt handler 43 executes the processing during the system call processing, it does not cause a contradiction in the resources managed by the OS 45. Although not present, the interrupt processing is suspended by the OS 45 here.

When the processing requiring exclusive control during the system call processing is finished, the interrupt permission processing means 47 executes the interrupt permission processing. Here, it is assumed that the interrupt disable section ends at time 56 and the interrupt enable section starts. Then, the interrupt handler 44 is executed only when the interrupt permission section starts, and the interrupt handler 43 is executed after the processing of the interrupt handler 44 is completed. The interrupt permission process is performed, for example, by executing an interrupt permission instruction (EI) of the CPU 51.

After all, the processing when an interrupt factor occurs in this system is performed as shown in FIG. That is, the process branches depending on whether the interrupt enabled state (EI) or the interrupt disabled state (DI) (step S
15) If the interrupt is enabled, the process moves to the corresponding interrupt handler (step S16), waits for the completion of the interrupt handler process, returns to the process before the interrupt (step S17), and the series of processes ends. . On the other hand, in the interrupt disabled state, the interrupt handler process is suspended until the interrupt enabled state is set (step S18), and after the interrupt enabled state, the process proceeds to step S16.

[0010]

In the above-mentioned conventional interrupt management method for the real-time OS, the OS collectively performs the interrupt prohibition / permission processing for all the interrupt factors. That is, in the interrupt disabled section,
All interrupts cannot be accepted.
Therefore, for any interrupt factor, there is a uniform restriction by the interrupt prohibition time caused by the OS, which is a problem in improving the operation efficiency of the system. This also means that the real-time OS can be used for systems that have interrupts that are never allowed to be delayed, or for systems that have timer interrupts with a cycle shorter than the maximum interrupt disable time specified by the real-time OS. It is also an obstacle to the introduction and is a cause of narrowing the applicable range of the real-time OS.

Japanese Unexamined Patent Publication No. 2-220138 discloses system call processing when a system call is issued in a system call prohibition section in the processing of an interrupt handler by an external interrupt, that is, a software interrupt prohibition section. A technique of delaying until the prohibition period ends and prioritizing interrupt processing is disclosed. However, in the case of this technique, the interrupt has priority over the system call only in the system call prohibition section explicitly specified in the interrupt handler, so that there is still a limitation due to the interrupt prohibition time.

An object of the present invention is to enable interrupts that do not affect resource management by the OS to be interrupted even during system call processing, so that interrupts that do not need to issue system calls can be processed without delay. To provide.

[0013]

Real-time method of the present invention
The interrupt management method in the operating system (real-time OS) has a CPU and
This is an interrupt management method in a computer system in which resources are managed by S and an asynchronous interrupt is generated with respect to a CPU. The managed interrupt storage means stores information about interrupts to be managed by the real-time OS, and the real-time OS. In order to perform exclusive control regarding the processing in step 1, the information stored in the managed interrupt storage means is read, the interrupt prohibition processing means for prohibiting the interrupt specified by the information, and the interrupt enable for permitting the prohibited interrupt And processing means.

In the interrupt management system of the present invention, specifically, a plurality of interrupt inputs that can be individually masked are provided, and the CPU is responsive to the unmasked interrupt inputs.
It is preferable that an interrupt controller for transmitting an interrupt to be provided and a specific interrupt operation processing unit for setting a mask in the interrupt controller in response to an interrupt prohibited by the interrupt prohibition processing unit. Further, as the interrupt permission processing means, it is preferable to use a means for releasing the mask set in the interrupt controller.

Further, in the interrupt management system of the present invention, managed interrupt information receiving means for storing the managed interrupt information received from the application program in the managed interrupt storage means may be further provided. When the managed interrupt information receiving means is provided, the managed interrupt information receiving means may receive the managed interrupt information from the application program and store the managed interrupt information in the managed interrupt storing means when the real-time OS is initialized.

According to the present invention, among the interrupts that occur asynchronously, only the interrupt that issues a system call to the OS in the corresponding interrupt handler stores the information in the managed interrupt storing means, so that the OS
Manage with. Therefore, an interrupt that is not directly related to the operation of the OS, such as not issuing a system call, is not affected by the OS, and the processing related to the interrupt can be performed without delay. For example, a timer controller that generates a timer interrupt is provided,
In addition, when a system call to the OS is not issued in the timer interrupt handler corresponding to the timer interrupt, the information regarding the timer interrupt is not stored in the managed interrupt storage means, so that delay is not allowed for interrupt processing. The real-time OS can be installed in a system including a timer interrupt.
Further, regarding the interrupt issuing the system call to the OS, the same operation as that in the conventional system is guaranteed.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

<< First Embodiment >> FIG. 1 shows a computer system based on an interrupt management system according to a first embodiment of the present invention.

The CPU 13 is connected to the interrupt controller 12 for notifying the CPU of occurrence of an interrupt and the main storage device 1. In this embodiment, the number of interrupt inputs accepted by the interrupt controller 12 is 16
In this book, interrupt numbers 0 to 15 are assigned to interrupt inputs. Further, the interrupt controller 12 includes an interrupt mask table 30 for masking an interrupt for each interrupt input, and when an interrupt input that is not masked by the interrupt mask table 30 has an input, the CPU 13 receives the interrupt. Report the occurrence.

A real-time OS 6 is resident in the main storage device 1, and a managed routine storing means 9 for storing a task routine, an interrupt handler routine, and an interrupt number managed by the OS 6 is developed. Here, the interrupt A from the interrupt factor 10 and the interrupt B from the interrupt factor 11 are input to the interrupt controller 12. Further, in the main storage device 1, a routine 2 of task A and a routine 3 of task B are developed as task routines, and an interrupt handler 4 activated by interrupt A is provided as an interrupt handler.
And interrupt handler 5 activated by interrupt B
Is being deployed. Further, the managed interrupt storing means 9 is
It is realized as a storage area referred to by the OS 6.

Inside the OS 6, there are interrupt prohibition processing means 7 for prohibiting interruption of a specific interruption number for exclusive control accompanying system call processing, and interruption permission processing means 8 for putting the CPU 13 in the interruption permitted state. ,
There is provided a specific interrupt operation processing means 14 for preventing the CPU 13 from accepting a specific interrupt whose interrupt is prohibited by the interrupt prohibition processing means 7. Specifically, the interrupt prohibition processing means 7 is a routine that is called when interrupts should be prohibited and reads the interrupt number from the managed interrupt storage means 9. The interrupt permission processing means 8 is a routine that operates the interrupt mask table 30 of the interrupt controller 12 via the CPU 13 to permit all interrupts. Further, the specific interrupt operation processing means 14 causes the interrupt mask table of the interrupt controller 12 via the CPU 13 so that only the interrupt having the interrupt number read from the managed interrupt storage means 9 by the interrupt prohibition processing means 7 is prohibited. This is a routine for writing to 30.

In the computer system of this embodiment, an interrupt generated for this system is classified into the type I: OS in the interrupt handler corresponding to the interrupt.
Interrupts that issue system calls for 6 and types
II: It is classified into two types, that is, an interrupt that does not issue a system call in the interrupt handler corresponding to that interrupt. The type I interrupt is an interrupt that needs to be managed by the OS 6 to enable / disable the interrupt, and its interrupt number is stored in the managed interrupt storage unit 9. On the other hand, since the type II interrupt does not issue a system call, the interrupt is not enabled / disabled by the OS 6, and therefore the interrupt number is not stored in the managed interrupt storage area 9.

Here, it is assumed that interrupt numbers 0 to 7 are type I interrupts, and interrupt numbers 8 to 15 are type II interrupts. Therefore, the interrupt numbers 0 to 7 are stored in the managed interrupt storing means 9. Further, the interrupt A generated by the interrupt factor 10 is a type I interrupt,
It is assumed that the interrupt B generated in the interrupt factor 11 is a type II interrupt. Therefore, the interrupt handler 4 issues a system call within its routine, and the interrupt handler 5 does not issue a system call.

Next, the interrupt processing in the above computer system will be described with reference to FIG. Here, a system call to the OS 6 is issued by the task A during the execution of the task A, and the interrupt A is input to the interrupt controller 12 from the interrupt factor 10 within the interrupt prohibited section during the system call processing, and then the interrupt factor is continued. A case where the interrupt B from 11 is input to the interrupt controller 12 will be described. In FIG.
Which routine the CPU 13 is executing is indicated by a thick line. EI indicates an interrupt enable section, and D
I indicates an interrupt prohibited section.

Assuming that all interrupts are in the interrupt enabled state, during execution of routine 2 of task A, time 1
It is assumed that a system call to OS6 is issued in 5. As a result, the processing by the CPU 13 transits from the task A to the OS 6 and the system call processing is performed. During system call processing, it is necessary to disable interrupts in the section where exclusive control of resources is required.
At 6, the interrupt prohibition processing means 7 is called. The interrupt prohibition processing means 7 reads the interrupt number stored in the managed interrupt storage means 9, and passes the read interrupt number to the specific interrupt operation processing means 14 as an interrupt to be prohibited. The specific interrupt operation processing means 14
Interrupt mask table 3 of interrupt controller 12
Operate 0 so that only type I interrupts are not accepted. As a result, the type I interrupt, that is, the interrupt A caused by the interrupt factor 10, is prohibited.
At this time, type II interrupts are not disabled.

Here, it is assumed that an interrupt A from the interrupt factor 10 occurs at time 17 in the interrupt prohibited section during the system call processing. Here, interrupt A
The interrupt controller 12 holds the interrupt A because the interrupt prohibition is set for. Therefore, the processing of the CPU 13 does not transit to the interrupt handler 4.

Next, the time 1 in the interrupt prohibited section
It is assumed that the interrupt B from the interrupt factor 11 occurs in 8. As described above, the interrupt B does not issue a system call in the interrupt handler 5, is not under the control of the OS 6, and the interrupt is permitted. Therefore, the interrupt B generated here
As a result, the system call processing is interrupted without being affected by the OS 6, and the interrupt handler 5 is immediately activated.

After the processing of the interrupt handler 5 is completed, the interrupted system call processing is resumed, and at time 19, the interrupt permission processing means 8 permits the interrupt for the type I interrupt. As a result, the interrupt A, which has been suspended, is accepted and the process proceeds to the interrupt handler 4.

FIG. 3 is a flow chart showing the processing when a type I interrupt occurs. When a type I interrupt occurs, the process branches depending on whether the interrupt is enabled (EI) or disabled (DI) (step S
1) If the interrupt is enabled, the process moves to the corresponding interrupt handler (step S2), waits for the completion of the interrupt handler process, returns to the process before the interrupt (step S3), and the series of processes ends. . On the other hand, in the interrupt disabled state, the interrupt handler process is suspended until the interrupt enabled state is entered (step S4), and after the interrupt enabled state is entered, the process proceeds to step S2. Eventually, the same processing as in the case of using the conventional interrupt management method will be performed.

On the other hand, FIG. 4 is a flow chart showing the processing when a type II interrupt occurs. When the type II interrupt occurs, as shown in step S5, the process does not branch depending on whether the interrupt is enabled (EI) or disabled (DI). In any case, the process moves to the corresponding interrupt handler (step S6), waits for the end of the interrupt handler process, returns to the process before the interrupt (step S7), and the series of processes ends. . After all, the interrupt is executed without being affected by the OS.

As described above, in the computer system according to the present embodiment, interrupt processing with high urgency can be immediately executed without being affected by the OS unless an OS system call is issued. . Therefore, it is possible to introduce a real-time OS in a field that has been conventionally prevented from being introduced due to a long interrupt prohibition time by the OS. Further, when it is necessary to issue an OS system call from within the interrupt handler, the same operation as in the conventional system is performed, so that compatibility with the conventional system is maintained.

<< Second Embodiment >> FIG. 5 shows a computer system based on an interrupt management system according to a second embodiment of the present invention. This computer system is similar to the computer system in the first embodiment, except that a timer controller 20 for generating a timer interrupt C is provided instead of an interrupt factor for generating an interrupt B, and a main storage device is provided. A timer interrupt handler 21 is prepared in place of the interrupt handler 5 in
The difference is that the managed interrupt information receiving means 22 is provided in S6. Timer interrupt handler 21
Is an interrupt handler that uses the timer interrupt C from the timer controller 20 as an interrupt factor, does not issue a system call of the OS 6, and assumes that the interrupt process is a process in which delay is not allowed. Further, the managed interrupt information receiving means 22 receives information on an interrupt to be managed by the OS 6 from the application program, and stores the corresponding interrupt number in the managed interrupt storing means 9.
To be stored in.

Next, the processing in the above-mentioned computer system will be described with reference to FIG. Here, it is assumed that the interrupt handler 4 corresponding to the interrupt A issues a system call.

First, as a setting at the time of initialization of the OS 6, it is set that only the interrupt A is managed by the OS 6. this is,
In the application program, the OS 6 is executed only from the interrupt handler 2 activated by the interrupt A.
This is because the system call is issued, and this setting can be changed by the application program.
At the time of initialization, the OS 6 receives the information to be stored in the managed interrupt storage means 9 from the application program by the managed interrupt information receiving means 22. Here, the interrupt number of the interrupt A is received, and the interrupt number is registered in the managed interrupt storage means 9.

Now, assuming that the registration in the managed interrupt storing means 9 is performed in this way, a system call to the OS 6 is issued by the task A during the execution of the task A, and within the interrupt prohibited section during the processing of the system call. Now, a case where the interrupt A is input to the interrupt controller 12 from the interrupt factor 10 and the timer interrupt C is subsequently generated will be described.

Assuming that all interrupts are in the interrupt enabled state, during execution of routine 2 of task A, time 3
It is assumed that a system call to OS6 is issued in 5. As a result, the processing by the CPU 13 transits to the OS 6 and system call processing is performed. During the system call processing, it is necessary to prohibit the interrupt in the section where the exclusive control of the resources is required, so the interrupt prohibition processing means 7 is called at time 36. Interrupt prohibition processing means 7
Reads out the interrupt number stored in the managed interrupt storing means 9. Since only the interrupt number corresponding to the interrupt A is stored in the managed interrupt storing means 9 as the setting at the time of initialization of the OS 6, only this interrupt number is passed to the specific interrupt operating means 14. The specific interrupt operating means 14 operates the interrupt mask table of the interrupt controller 12 based on the passed interrupt number, and as a result, only interrupt A is prohibited.

Here, it is assumed that an interrupt A from the interrupt factor 10 occurs at time 37 in the interrupt prohibited section during the system call processing. Here, interrupt A
Since the interrupt prohibition is set for, the interrupt controller 12 suspends the interrupt A. Therefore, the processing of the CPU 13 does not transit to the interrupt handler 4.

Next, at time 3 in this interrupt prohibited section.
8, it is assumed that a timer interrupt C is generated by the timer controller 20. Since the timer interrupt C is not placed under the control of the OS 6 as a setting at the time of initialization of the OS 6, the interrupt is permitted. Therefore, even during the interrupt disabled period, the system call processing is interrupted by the timer interrupt C and the timer interrupt handler 21 is immediately activated.

After the processing of the timer interrupt handler 21 is completed, the interrupted system call processing is returned to again, and at time 39, the interrupt permission processing means 8 permits the interrupt to the interrupt A. As a result, the interrupt A, which has been suspended, is accepted and the process proceeds to the interrupt handler 4.

FIG. 7 is a flow chart showing the processing when the interrupt A occurs. When interrupt A occurs, interrupt enable state (EI) or interrupt disable state (D)
I) Depending on whether or not the process branches (step S8), and if the interrupt is enabled, the process moves to the interrupt handler 4 (step S9), waits for the end of the interrupt handler process, and returns to the process before the interrupt. (Step S10), a series of processing ends. On the other hand, in the interrupt disabled state, the interrupt handler processing is suspended until the interrupt enabled state is set (step S11), and after the interrupt enabled state, the process proceeds to step S9. Eventually, the same processing as in the case of using the conventional interrupt management method will be performed.

On the other hand, FIG. 8 is a flowchart showing the processing when the timer interrupt C occurs. When the timer interrupt C is generated, as shown in step S12, no branching of the processing depending on the interrupt enabled state (EI) or the interrupt disabled state (DI) occurs. In any case, the process moves to the timer interrupt handler 21 (step S13), waits for the end of the process of the timer interrupt handler 21, returns to the process before the interrupt (step S14), and a series of processes is performed. finish. Eventually, the timer interrupt C is executed without being affected by the OS.

In this embodiment, a highly urgent timer interrupt is executed without being affected by the OS. For example, in a system in which communication is synchronized based on the clock generated by the timer controller 20, clock interrupts at precise intervals are essential. Even in such a field where importance is placed on the accuracy of the interrupt activation interval time, the use of the present embodiment makes it possible to introduce a real-time OS. In addition, when it is necessary to issue an OS system call from within the interrupt handler, the same operation as in the case of the conventional interrupt management method can be performed, and compatibility with the conventional system is maintained.

[0042]

As described above, the present invention is provided with the managed interrupt storing means and the specific interrupt operation processing means,
By storing in the managed interrupt storing means only the information about the interrupts that the OS wants to manage, the compatibility with the conventional system is maintained, and the interrupts not directly related to the operation of the OS are not affected by the OS. The advantage is that processing can be performed without delay.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a computer system to which an interrupt management system according to a first embodiment of this invention is applied.

2 is a timing chart showing processing in the computer system of FIG. 1 when an interrupt occurs.

FIG. 3 is a flowchart showing processing in the computer system of FIG. 1 when a type I interrupt occurs.

4 is a flowchart showing processing in the computer system of FIG. 1 when a type II interrupt occurs.

FIG. 5 is a block diagram showing a configuration of a computer system to which an interrupt management system according to a second embodiment of this invention is applied.

6 is a timing chart showing processing in the computer system of FIG. 5 when an interrupt occurs.

7 is a flowchart showing processing in the computer system of FIG. 5 when an interrupt A occurs.

8 is a flowchart showing processing in the computer system of FIG. 5 when a timer interrupt C occurs.

FIG. 9 is a block diagram showing a configuration of a conventional computer system controlled by a typical real-time OS.

10 is a timing chart showing processing in the computer system shown in FIG. 9 when an interrupt occurs.

FIG. 11 is a flowchart showing processing in the computer system shown in FIG. 9 when an interrupt occurs.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main memory 2, 3 Routines 4, 5 Interrupt handlers 6 Operating system 7 Interrupt prohibition processing means 8 Interrupt permission processing means 9 Managed interrupt storage means 10, 11 Interrupt factor 12 Interrupt controller 13 CPU 20 Timer controller 22 Managed interrupt information Receiving means 23 Timer interrupt handler 30 Interrupt mask table

Claims (8)

[Claims] 1. A CPU having a CPU, wherein resources are managed by a real-time operating system.
An interrupt management method in a computer system in which an asynchronous interrupt is generated with respect to a PU, and a managed interrupt storage unit that stores information regarding an interrupt to be managed by the real-time operating system, and In order to perform exclusive control regarding the processing, the information stored in the managed interrupt storage means is read, and the interrupt prohibition processing means for prohibiting the interrupt designated by the information, and the interrupt permission for permitting the prohibited interrupt An interrupt management method in a real-time operating system having a processing means. 2. An interrupt controller connected to the CPU, having a plurality of individually maskable interrupt inputs, and transmitting an interrupt to the CPU in response to an input to the unmasked interrupt input; 2. The interrupt management system in the real-time operating system according to claim 1, further comprising a specific interrupt operation processing unit that sets a mask in the interrupt controller in response to an interrupt prohibited by the processing unit. 3. The real-time operating system according to claim 2, wherein only information regarding an interrupt that issues a system call to the real-time operating system in a corresponding interrupt handler is stored in the managed interrupt storage means. Interrupt management method in. 4. The interrupt management method in a real-time operating system according to claim 2, wherein the interrupt permission processing means releases the mask set in the interrupt controller. 5. The interrupt management method in a real-time operating system according to claim 2, wherein a timer controller that generates a timer interrupt is connected to the interrupt controller, and the managed interrupt storage means does not store information about the timer interrupt. . 6. The interrupt management system according to claim 5, wherein a system call to the real-time operating system is not issued in the timer interrupt handler corresponding to the timer interrupt. 7. The interrupt management system in a real-time operating system according to claim 2, further comprising managed interrupt information receiving means for storing managed interrupt information received from an application program in the managed interrupt storage means. 8. The real-time operating system according to claim 7, wherein the managed interrupt information receiving means receives the managed interrupt information and stores the managed interrupt information in the managed interrupt storage means when the real-time operating system is initialized. Interrupt management method in.