JPH0658654B2 - Interrupt acceptance control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a plurality of processors, and more particularly to an interrupt acceptance control method for dynamically determining a processor that accepts an input / output interrupt from a channel device. .

[Technical background of the invention]

In this type of multiprocessor system, for example, the following three methods are well known as control methods when receiving an input / output interrupt from a channel device.

(i) Method 1 In this method, a processor that can perform input / output processing is, for example, a specific one of the _four processors 1 ₁ to 1 ₄ (the first processor) that configures the system as shown in FIG. in the figure is fixed to the processor 1 _4). Then, the specific processor 1 ₄ accepts all of the input and output interrupt from the channel unit 2.

(ii) Method 2 In this method, as shown in FIG.
O interrupt from is transmitted to all the processors 1 ₁ to 1 _4, processor performing first reception interrupt performs the interrupt processing.

(iii) Method 3 In this method, the processor 1 ₁ as shown in FIG.
To 1 (processor 1 ₂ in FIG. ₃₎ performs the interrupt processing processor which issued the output request of the _four. In this case, the channel device 2 is the processor 1 that issued the I / O request.
₂ stores the results in interrupting to the processor 1 _2.

[Problems of background technology]

 Each of these methods had the following problems.

(i) Method 1 i-i) If a processor that can perform input / output processing goes down due to a failure or the like, the system goes down.

i-ii) In order for another processor to issue an I / O request,
Programs for other processors need to be redispatched on a processor that can make I / O requests, and the overhead is high.

i-iii) Since the processor that can perform input / output processing is fixed, the processor is likely to become a bottleneck (a bottleneck) in performance.

(ii) Method 2 The processor that first accepts an interrupt and performs interrupt processing does not always become the optimum processor for performing interrupt processing in the system, and there is room for reducing the overhead associated with interrupt processing.

(iii) Method 3 iii-i) If the processor that issued the I / O request is in a state where it cannot accept the I / O interrupt from the channel device,
Interrupt processing will be delayed.

iii-ii) It is necessary to take measures when the processor that issued the I / O request is down due to a failure or the like before accepting the I / O interrupt.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and its purpose is to:
In a multiprocessor system, a processor that performs interrupt processing for an interrupt request from a channel device is dynamically determined according to the load status of each processor in the system, improving system performance and fault tolerance, and further interrupt processing efficiency. The object of the present invention is to provide an interrupt acceptance control method capable of improving the above.

[Outline of Invention]

In the present invention, when the channel device requests interrupt processing, it is configured to issue an interrupt request to the system controller instead of directly requesting to the processor. Each processor that constitutes the multiprocessor system generates and outputs status information indicating the interrupt enable / disable state, operating status, and operating rate of the corresponding processor. In response to the interrupt request from the channel device, the system control device determines the interrupt destination processor based on each status information from each processor and issues an interrupt processing command to the processor. The processor given the interrupt processing command from the system controller notifies the system controller of acceptance of the first interrupt or refusal of acceptance of the first interrupt depending on its own interrupt enable / disable state. In response to the first interrupt acceptance or first interrupt acceptance refusal notification from the processor, the system controller notifies the channel device (second interrupt acceptance or second interrupt acceptance refusal). The channel device is the second from the system controller.
When the interruption acceptance refusal is notified, the interruption request is again issued to the system controller.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present embodiment is applied to a multiprocessor system including four processors. FIG. 4 shows the configuration of a multiprocessor system to which the present invention is applied.
In the figure, 10 ₁ to 10 ₄ are processors, 20 is a channel device that performs input / output processing in response to input / output requests from the processors 10 ₁ to 10 ₄ , and 30 is a system control unit (hereinafter, SCU) that controls the entire system. It is called). The processor 10 _i (i = 1 to 4) generates and outputs status information STATUS _i indicating various states of the processor 10 _i . The status information STATUSi includes information of an interrupt prohibition / permission flag (IF) 11 _i , an operation status flag (not shown), and an operation rate flag (not shown). The interrupt prohibition / permission flag 11 _i indicates whether or not the corresponding processor 10 _i is in the interrupt prohibition state. The operation status flag indicates whether or not the corresponding processor 10 _i is in a stopped (standby) state. The operating rate flag indicates the latest operating rate. This operating rate is a fixed period (or arbitrary period)
Letting T _Y be the total period during which the processor 10 _i is not stopped in T _X , it is binary data of a numerical value represented by (T _Y / T _X ) × 100 (%). The information on the operating rate flag is updated sequentially or periodically. Processor 10
_The status information STATUSi generated and output by _i is supplied to the SCU 30. An interrupt request INT-REQ from the channel device 20 is also supplied to the SCU 30. When an interrupt request INT-REQ is issued from the channel device 20, the SCU 30 receives status information STATUS1 to STA from the processors 10 ₁ to 10 _4.
Optimal processor 1 for interrupt processing according to TUS4
0 _j (j is one of 1 to 4) is determined, and an interrupt processing instruction INTj is issued to the processor 10 _j .

The processor 10 _j receives the interrupt processing command INT from the SCU 30.
When j is received, the interrupt disable / enable flag 11 _j is referred to, and the interrupt acceptance INT depending on the state of this flag 11 _j
Either -ACKj or interrupt acceptance refusal INT-RJTj is issued to the SCU 30. Also SCU30
Is, INT-ACKj from the processor 10 _j, according to INT-RJTj, interrupt reception INT-ACK or interrupt reception deny IN,
Either one of T-RJT is issued to the channel device 20.

Next, the operation of the embodiment of the present invention will be described with reference to the timing chart of FIG. When the input / output request is given from any of the processors 10 ₁ to 10 ₄ , the channel device 20 starts the corresponding input / output processing. The channel device 20 issues an interrupt request INT-REQ to the SCU 30 when it becomes necessary to request an interrupt process from any of the processors 10 ₁ to 10 ₄ due to the completion of input / output processing. The SCU30 processor 10 ₁
10 status information STATUS1~STA generated output ₄
TUS4 is supplied. The SCU 30 is the channel device 20.
When receiving the interrupt request INT-REQ from the processor 10,
Based on the status information STATUS1~STATUS4 from ₁ to 10 _4, to select an optimum interrupt destination processor at that time. When the interrupt destination processor is selected, the weight of each information part of the status information STATUSi (i = 1 to 4) is the highest in the information part indicating whether or not the interrupt is prohibited,
Next, the information part indicating whether or not the system is in a stopped state and the information part indicating the operating rate are in that order. In this embodiment, the processors in the interrupt disabled state are not selected. It should be noted that, when the interrupt request is issued from the channel device, the above-mentioned technique for selecting the optimum processor for performing the interrupt processing based on the status information from each processor is described in October 29, 1982. It is described in the specification and the drawings attached to the application of Japanese Patent Application No. 57-190112 filed by the applicant. The present invention is a further improvement of the above technique as described below.

Now, according to the interrupt request INT-REQ from the channel device 20, for example, the processor 10 ₂ is the one selected as the interrupt destination processor. The SCU 30 is the processor 10
Issue an interrupt processing command INT2 to ₂ . in this case,
Processor 10 ₂ interrupt processing command from SCU30 INT2
Interrupt processing will be performed in accordance with. However, if the processor 10 ₂ is transitioning from interrupt enable state to the interrupt disable state, the processor 10 ₂ can no longer perform the interrupt processing. As is well known, the interrupt disabled state is set when another process having a higher priority than the interrupt process (here, the input / output interrupt process) is performed.
The period in the interrupt disabled state is a period required for these high-priority processes, and is normally several hundred T (T; clock cycle) to several thousand T, and in some cases, a period longer than that. Therefore, in special cases, such as described above, the processor 10 _2, the interrupt processing command I from SCU30
In the invention (prior invention) described in Japanese Patent Application No. 57-190112, a period of several hundred T to several thousand T or more is required until the interrupt processing can be executed according to NT2. Such inconvenience is as follows.
Processor from the state transition to the interrupt disable state (10 ₂₎ of the interrupt enable state, usually number until the condition is transmitted to SCU30 as status information (STATUS2) T
(T; clock period). That is, since the SCU 30 selects the interrupt destination processor depending on the state of the processors 10 ₁ to 10 ₄ before the number T, the SCU 30 determines that the processor that has transitioned to the interrupt disabled state during the number T is ( It is possible to issue an interrupt command (without knowing that it is in a prohibited state). This problem, taking a case where the processor 10 ₂ is a state transition from the interrupt enable state to the interrupt disable state as an example, the fifth
This will be described with reference to the timing chart in the figure.

In the example of FIG. 5, interrupt disable / enable flag (IF) 11 ₂ of the processor 10 in the _2, until the time t _A is the processor 10 ₂ interrupt enable state, indicating that it thereafter is in the interrupt disabled state ing. State of the processor 10 _2, as a status condition STATUS2, it is transmitted several T, for example, after 4T to SCU30. Therefore, the state transition to the interrupt disable state of the processor 10 ₂ SCU30 can first detected is the time t _{A +} 4T. By the way, in the present embodiment, the interrupt destination processor 10 from the SCU 30
Interrupt processing command for _j (j is one of 1 to 4)
The timing at which INTj is issued is the timing (clock cycle) next to the timing at which the interrupt request INT-REQ from the channel device 20 is generated. Therefore, the channel device 2
As the generation timing of the interrupt request INT-REQ from 0 is designated G1, G2 of FIG. 5, the time _t A _-T~t
If that is the clock period between _{A +} 4T, interrupt processing instruction INT2 might be issued to the processor 10 ₂ in the interrupt disabled state.

The processor 10 _2, the interrupt processing command INT from SCU30
Upon receipt of the 2, referring to its interrupt disable / enable flag 11 _2. As in this example, if the flag 11 ₂ indicates the interrupt disabled, it takes a lot of time before the processor 10 ₂ interrupt disabled state is released, the SC
Issue INT-RJT2 to U30.
Then, SCU30, upon receiving the interrupt reception refusal INT-RJT2 from the processor 10 _2, emit interrupt reception refusal INT-RJT to the channel device 20, the channel device 2
Notify that the interrupt request from 0 has been rejected. When receiving the interrupt acceptance refusal INT-RJT from the SCU 30, the channel device 20 again issues the interrupt request INT-REQ to the SCU 30. As a result, the SCU 30 causes the status information STATUS1 to S from the processors 10 ₁ to 10 _4.
Reselect the interrupt destination processor according to TATUS4. Here, the period from issues a reject INT-RJT2 accepted interrupt the processor 10 ₂ to SCU30, until the channel device 20 issues a re-interrupt request INT-REQ to SCU30, period required for the so-called retry is a matter of + T . On the other hand, from the transition to the interrupt disable state to the processor 10 ₂ is the time t _A, to return again to the interrupt enable state thousands T hundreds T as described above, or requires more time. Therefore, the channel device 2
0 is an interrupt request INT-REQ to the SCU 30 again.
Is issued, the status information STATUS2 from the processor 10 ₂ indicates the interrupt disabled state, and the processor 10 ₂ will not be selected again. That is, the processors 10 ₁ , 10 ₃ , 1 (excluding the processor 10 ₂ )
0 ₄ is the interrupt destination processor is selected from among the interrupt processing is executed by the processor. As described above, in this embodiment, even if the processor in the interrupt disabled state is selected as the interrupt destination processor due to the timing problem,
Since the alternative processor is immediately selected, an interrupt pending state does not occur and efficient interrupt processing can be performed.

On the other hand, the interrupt request INT-R from the channel device 20
When the generation timing of the EQ is time t _A -T Previously, if the processor 10 ₂ is selected as an interrupt destination processor, the corresponding interrupt processing instruction INT2 is generated from SCU30 during interrupt enable processor 10 ₂ To be The processor 10 _2, upon receiving the interrupt processing command INT2 from SCU30, its interrupt disable / enable flag 1
Referring to 1 _2. As in this example, if the flag 11 ₂ indicates the interrupt enable, the processor 10 ₂ SCU30
An interrupt acceptance INT-ACK2 is issued to and an interrupt process is started. The SCU 30 is the processor 1
0 When receiving the interrupt reception INT-ACK2 from ₂ issues an interrupt reception INT-ACK to the channel device 20, notifying that the interrupt request from the channel device 20 is accepted. The interrupt request INT from the channel device 20
When the generation timing of -REQ is time _T A + 4T later, the processor 10 ₂ becomes out of selection.

By the way, although the above-mentioned embodiment has been described as being applied to a multiprocessor system having four processors, the present invention can be applied to a system having an arbitrary number of processors.

〔The invention's effect〕

As described in detail above, according to the present invention, a processor that performs interrupt processing for an interrupt request from a channel device is dynamically determined according to the load status of each processor in a multiprocessor system, and system performance and fault tolerance are improved. And the interrupt processing efficiency can be improved.

[Brief description of drawings]

1 to 3 are diagrams for explaining a conventional interrupt acceptance control system, FIG. 4 is a block diagram showing an embodiment of a multiprocessor system to which the present invention is applied, and FIG.
The figure is a timing chart for explaining the operation. 10 ₁ to 10 ₄ ... Processor, 11 _{1 to} 11 ₄ ... Interrupt prohibition / permission flag, 20 ... Channel device, 30 ...
… System control unit (SCU).

Claims (1)

[Claims] 1. A multiprocessor system comprising a plurality of processors and a channel device for performing input / output processing in response to input / output requests from these processors, wherein interrupt enable / disable states of the processors from the plurality of processors are provided. A means for generating and outputting status information indicating an operating condition and an operating rate, and an interrupt destination processor is determined based on the status information from the plurality of processors in response to an interrupt request from the channel device, and the processor A system controller that issues an interrupt processing command to the system controller and a first interrupt acceptance or first interrupt from the processor to the system controller based on its own interrupt enable / disable state in response to the interrupt processing command from the system controller. A means to notify acceptance refusal,
Accepting the first interrupt from the processor or the first
Means for notifying the channel device of the second interruption acceptance or the second interruption acceptance refusal in response to the interruption acceptance refusal, and the channel equipment for responding to the second interruption acceptance refusal from the system control device An interrupt acceptance control system, comprising: means for issuing the interrupt request again to the system control device.