JPH08289232A - Display converting device for liquid crystal panel - Google Patents

Abstract

PURPOSE: To perform display on a liquid crystal wide panel while switching a wide display and a 4:3 display mode, suppressing the kind of a decode circuit for an output pulse onto the panel into one kind and further automatically keeping the phase relation. CONSTITUTION: At the time of wide display, the output of a VCO 1 is frequency- divided into (1/3)×(1/N) stages and the horizontal shift clock of N phases is provided. At the time of 4:3 display, the output of the VCO 1 is frequency- divided into (1/2)×(1/N) or (1/4)×(1/N) stages by a switcher 4. Then, a central display part uses the N-phase horizontal shift clock of (1/4)×(1/N) frequency- divided output and black display parts on both sides use the N-phase horizontal shift clock of (1/2)×(1/N) frequency-divided output. At the time of wide display or 4:3 display, a PLL 3 is composed of the 1/ 3 frequency-divided output of the VCO 1 and the external input signal of a horizontal synchronizing input terminal 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal wide panel display conversion device.

[0002]

2. Description of the Related Art First of all, a horizontal shift clock for a liquid crystal panel is usually required for an N-phase shift clock and a 1 / N frequency divider. Further, the frequency of the horizontal shift clock for 4: 3 display (4: 3 source) may be 0.75 times the frequency of the horizontal shift clock for wide display (16: 9 source) on the wide panel (9). / 16
÷ 3/4 = 0.75). In the case of 4: 3 display, normally both sides are normally displayed in black. However, this black display unit increases the frequency of the horizontal shift clock by 1.5 times that in wide display, thereby reducing the time for one horizontal period. It is matched. That is,
The horizontal shift clocks of the black display portions on both sides at the time of 4: 3 display have the frequency doubled with respect to the central display portion. The above operation will be described with reference to the circuit configuration diagram of the conventional liquid crystal panel display conversion device of FIG. 3 and the operation waveform diagram of each part of FIG.

In FIG. 4, a liquid crystal panel is displayed during wide display.
Horizontal shift clock frequency f₃N times the frequency f₂
Forms a PLL loop with the input signal H-SYNC.
It On the other hand, when displaying 4: 3, the black display on the LCD panel is horizontal.
Shift clock frequency f_FiveN times the frequency f_FourInput with
H-SYNC and PLL loop of
F, which is the flat shift clock frequency₆Of the black display
Horizontal shift clock frequency f_FiveAnd divide by 1/2 to obtain the table
Switching signal f between the display part and the black display part₇By switching with
Final horizontal shift clock frequency f₈Is getting Well
Also, the horizontal shift clock frequency f during wide display₃When
Horizontal shift clock frequency f at 4: 3 display ₈The choice of
Use a mode selection signal.

In FIG. 3, a common frequency oscillator VCO
1 of the output f ₁ divided by a 1/3 frequency divider 2 to obtain a f ₂ are, PLL loop between the output f ₂ of the H-SYNC and 1/3 frequency divider 2 from the horizontal synchronizing signal input terminal 14 Forming 3, PLL
1/3 frequency divider 2 output f ₂ output from loop 3
The frequency is divided by the N frequency divider 7, and the N-phase (N = 3 to 6) horizontal shift clock f ₃ during wide display is output via the mode selection switch SW13. On the other hand, at the time of 4: 3 display, the output f ₁ of the VCO ₁ is divided by the 1/2 divider 8 to obtain f _4, and H-SYNC from the horizontal synchronizing signal input terminal 14 and the 1/2 divider 8 are obtained.
The output f ₄ of the PLL loop 9 is formed, and the 1/2 divider 8 output f ₄ output from the PLL loop 9 is divided by the 1 / N divider 10 to produce a black display on both sides. The horizontal shift clock f ₅ is obtained, and the output f ₅ of the 1 / N frequency divider 10 is set to 1
The horizontal shift clock f ₆ of the central display portion is obtained by dividing the frequency by the 1/2 divider 11, and the output f ₇ from the PLL loop 9 which is a switching signal between the black display portions on both sides and the central display portion f ₇ causes f ₅ , the f ₆ by switching on the switch SW12 to obtain the output f _8, via the SW13 mode selection switch 4: 3 to output the N-phase horizontal shift clock f ₈ at the display.

With the above operation, assuming that the frequency of the horizontal shift clock f ₃ in wide display is 1, the horizontal shift clock f ₆ in the central display portion in 4: 3 display is 0.75 times,
Since the horizontal shift clock f ₅ of the black display portions on both sides is 1.5 times, 4: 3 display of both side black can be performed on the wide panel.

[0006]

In the conventional horizontal shift clock generator, the PLL frequencies f ₂ and f ₄ at the wide display and the 4: 3 display of the liquid crystal wide panel are tripled and doubled, respectively. Since the frequency f ₁ is common, V
CO can be unified into one, but two PLL loops are required.

Generally, a large number of timing pulses other than the horizontal shift clock are required to drive the liquid crystal panel, but all of them are produced by decoding from a programmable counter in the PLL loop. Therefore PL
The existence of two systems of L loops requires two kinds of decoding circuits for each pulse, which leads to an increase in the number of elements. Further, since the horizontal shift clock uses N phases (N = 3 to 6), the frequency f is displayed at 4: 3 display.
If you do not fully consider the timing of switching ₅ and f ₆ ,
It also had a performance defect that the continuity of the phase relationship was not preserved.

The present invention is intended to solve the above-mentioned problems.
With one L loop, one type of output pulse decoding circuit to the panel, and for horizontal shift clock frequency conversion during 4: 3 display, the phase relationship of the N phase is automatically saved. It is intended to provide a conversion device.

[0009]

In order to solve the above problems, a display conversion device for a liquid crystal panel according to the present invention has one PLL loop and 1 / N as a horizontal shift clock.
Before frequency division, mode selection of wide display or 4: 3 display is performed, and when 4: 3 display is performed, switching between the central display section and the black display sections on both sides as an input signal of the 1 / N frequency divider. A signal whose frequency is switched by a signal is used.

[0010]

In the above structure, as shown in FIG. 2, at the time of wide display, the common VCO frequency f ₁ is divided by ⅓ to f.
₂ is divided by 1 / N to obtain an N-phase horizontal shift clock f ₃ . On the other hand, during 4: 3 display, the common VCO frequency f ₁ is divided into ½ or ¼ by the switching signal f ₇ between the black display section on both sides and the central display section in the 4: 3 display mode. The output f ₉ is obtained by switching whether or not
It is divided by N to obtain an N-phase horizontal shift clock.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
I do. FIG. 1 shows a liquid crystal panel display conversion device according to an embodiment of the present invention.
2 is an operation waveform diagram of each part. FIG.
In the wide display, the output f of the common VCO 1 ₁
(Fig. 2) is divided by 1/3 frequency divider 2 to f₂(Fig. 2)
The output f of this 1/3 frequency divider 2₂And horizontal sync signal input
PLL with external input signal H-SYNC from terminal 14.
Loop 3 is formed, and 1/2 divider 2 output f₂The mode selection
Divide by 1 / N divider 6 via SW5 of the switch
N-phase horizontal shift clock frequency f when displaying id₃(Figure
2) is output from the horizontal shift clock output terminal 15.

On the other hand, when displaying 4: 3, the output f of the VCO 1
₁ is switched by the switching signal 4 by the switching signal f ₇ (FIG. 2) between the black display portion on both sides and the central display portion at the time of 4: 3 display obtained from the PLL loop 3.
The output f ₉ (FIG. 2) is divided by 4 and divided by the 1 / N divider 6 via SW5 of the mode selection switch, and the N-phase horizontal shift clock is displayed at 4: 3 display. The frequency f ₁₀ (FIG. 2) is output from the horizontal shift clock output terminal 15.

By the above operation, the horizontal shift clock frequency of the central display portion in the 4: 3 display is 0.75 times the horizontal shift clock frequency in the wide display, and the effective pixels of the panel can be thinned. Further, the horizontal shift clock frequency of the black display portions on both sides is doubled that of the central display portion to recover the thinned time.

[0014]

As described above, according to the present invention, since there is only one PLL loop, only one type of output pulse decoding to the panel is required, and the frequency conversion of the horizontal shift clock in 4: 3 display is performed. Also, since the frequency of the input clock signal is switched before being divided by 1 / N,
The phase relationship of the N phase is automatically saved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a liquid crystal panel display conversion device according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of each part in FIG.

FIG. 3 is a circuit configuration diagram of a conventional liquid crystal panel display conversion device.

FIG. 4 is an operation waveform diagram of each part in FIG.

[Explanation of symbols]

 1 Frequency Oscillator VCO 2 1/3 Divider 3 PLL Loop 4 1/2 Divider and 1/4 Divider Switcher 5 Mode Selection Switch SW 6 1 / N Divider 14 Horizontal Sync Signal Input Terminal 15 Horizontal Shift Clock output terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Amano 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] 1. An output signal of a frequency oscillator VCO is 1/3.
By the PLL loop to which the signal divided by the frequency divider and the input horizontal synchronizing signal are inputted, and the output signal of the PLL loop, the switching signal between the both-side black display section and the central display section in the 4: 3 display mode, Switching means for switching between dividing the output signal of the VCO by ½ or ¼ and an output signal of the ⅓ frequency divider or an output signal of the switching means to select wide display or The mode selection switch for 4: 3 display and the output from the mode selection switch are input and divided by 1 / N, and the N phase output signal is the N phase of the panel in the wide display mode or the 4: 3 display mode. A display conversion device for a liquid crystal panel, comprising: a 1 / N frequency divider used as a horizontal shift clock.