JPH026468Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a display in a frequency synthesizer-based channel selection device, particularly to a liquid crystal display circuit.

Conventionally, fluorescent display tubes, light emitting diodes, and liquid crystals have been used as frequency display elements in digital synthesizer tuners. Each type is used differently depending on its purpose, but in most cases a microcomputer plays the role of control. In other words, input channel selection information (usually key presses) is analyzed and processed by a microcomputer, and the frequency division value N is sent to the variable frequency divider in the frequency synthesizer circuit, and the corresponding received frequency display data is displayed on the display device. Output to.

Figure 1 shows a conventional phase-locked loop (PLL)
1 is a block diagram configuring a tuning section of a frequency synthesizer tuner using a frequency synthesizer tuner. 1 is a microcomputer for controlling the channel selection, 2 is a group of keys for inputting the channel selection operation, 3 is a display device for displaying the received frequency, and 4 is a
PLL circuit 5 is an intermediate frequency section of the receiver. A key source signal is sent from the microcomputer 1 to the key group 2. When a key is pressed, a key source signal corresponding to that key is fed back to the microcomputer 1 and analyzed. Display data corresponding to the resulting reception frequency is sent to the display device 3, and the frequency division value N is sent to the PLL circuit section 4. Display device 3 is a fluorescent display tube, LED or LCD
The display method can be either static or dynamic, and the optimal method is selected, but in either case, it is appropriately controlled by the microcomputer 1. The PLL section 4 includes a reference frequency divider, a variable frequency divider, and a phase comparator. The outputs are compared with a phase comparator. The output of this comparator drives a voltage controlled oscillator to create a local oscillation frequency, which is sent to intermediate frequency 5 and mixed to complete tuning.

Although the channel selection circuit is constructed with the microcomputer as its center, it is desirable to have as few components as possible in order to reduce the mounting area of the reception set. Therefore, it is required to incorporate the display device 3 and PLL section 4 into the microcomputer section 1 as much as possible. For this reason, liquid crystals are often used as display elements. Liquid crystals can be directly driven by a microcomputer relatively easily, and their power consumption is minimal, making them suitable for battery-powered sets. Also, display noise is less likely to jump into the radio. However, when the liquid crystal is dynamically driven, its display period is relatively long, so it is necessary to provide a special counter to divide the frequency of an appropriate clock signal. However, when the PLL section 4 is also incorporated into the microcomputer 1, the chip size of the microcomputer increases, often resulting in high costs. Therefore, it is necessary to suppress the increase in chip size as much as possible through circuit design.

The present invention has been devised in view of this point, and aims to reduce the chip size through common use of circuits, and to provide an inexpensive channel selection element.

According to the present invention, the channel selection elements include the reference frequency divider, variable frequency divider, and phase comparator in the PLL section, and the display section includes a liquid crystal driver, and the liquid crystal drive method uses a dynamic method. , is configured to obtain a basic signal for determining a display period from the reference frequency divider. Therefore, by commonly using the reference frequency divider, the circuit configuration can be reduced and the object of the present invention can be achieved.

The present invention will be explained in more detail below with reference to the drawings.

FIG. 2 shows one embodiment of the present invention. 10 is a control CPU, 20 is a variable frequency divider, 30 is a phase comparator,
40 is a reference frequency divider, 50 is a 1/2 divider, 60 is a voltage level selection circuit, 70 is a liquid crystal common electrode driver circuit, 80 is a liquid crystal segment driver circuit, 9
0 is a latch decoder for displayed data. In reality, there are a plurality of segment driver circuits 80, but they are omitted here.

FIG. 3 is a time chart for explaining the operation of FIG. 2. (1) is the output of the reference frequency divider 40, (2)
is the output of the 1/2 divider 50, (3) is the potential of Vac in the voltage level selection circuit 60, (4) is the potential of Vbc, (5)
is the output of COM ₁ in the common electrode driver 70, (6) is the output of COM ₂ , and (7) is the Sa in the latch decoder 90.
(8) is the output of the Sd, (9) is the output of the segment driver circuit 80, (10) is the relative voltage between COM ₁ and Seg, and (11) is the relative voltage between COM ₂ and Seg. . Next, the operation of the liquid crystal display shown in FIG. 2 will be explained with reference to FIG.

The output (1) of the frequency divider 40 is divided by a 1/2 divider 50, and this output (2) determines the frame frequency of the display. That is, the direction of the electric field between the liquid crystal electrodes is controlled to be reversed each time (2) is reversed. Therefore, first, in order to determine the voltage levels of the common electrodes COM ₁ and COM ₂ , Vac and Vbc are selected as shown in (3) and (4), respectively, in the voltage level selection circuit 60. As a result, the outputs COM ₁ and COM ₂ of the common electrode driver 70 become (5) and (6), respectively. The displayed data is transferred from the CPU 10 to the latch decoder 90, but two inputs Sa,
Sb is prepared and selected by (1). This Sa,
Sb is further controlled by (2), for example, when Sa and Sb are (7) and (8), respectively, the output of the segment electrode driver 80 is (9). Thus, the relative potential between the two poles of COM ₁ −Seg and COM ₂ −Seg is
As shown in (10) and (11), the segment on the COM ₁ -Seg intersection can be turned off, and the segment on the COM ₂ -Sog intersection can be turned on.

As explained above, according to the present invention, the output of the reference frequency divider can be used to control the display of the liquid crystal, so a special frequency divider is not required, and the chip size can be greatly reduced. In this embodiment, the output of the reference frequency divider is directly used, but it goes without saying that the result of further frequency division may be used for display control. In this case, a frequency divider is required, but it can be completed with a very small number of frequency dividers compared to the case where they are provided completely independently.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional frequency synthesizer, Fig. 2 is a diagram showing a liquid crystal display control circuit in the frequency synthesizer according to the present invention, and Fig. 3 is a time chart explaining the operation of Fig. 2. be. 1...Microcomputer, 3...Display element, 10...CPU, 40...Reference frequency divider, 60
... Voltage level selection circuit, 70 ... Common electrode driver circuit, 80 ... Segment electrode driver circuit.

Claims (1)

[Scope of utility model registration request] A PLL that divides a local oscillation frequency signal with a variable frequency divider, compares the phase of the divided signal with a reference signal from a reference frequency divider, and controls the frequency of the local oscillation frequency signal based on the comparison output. circuit and
first circuit means for generating a common electrode signal for a liquid crystal display in response to a first signal obtained from said reference frequency divider and a second signal of a higher frequency than said signal; a second signal and second circuit means for generating segment electrodes of the liquid crystal display in response to data to be displayed, the first circuit means comprising a voltage a level selection circuit and a common electrode driver circuit, the voltage level selection circuit generating a first output terminal, a second output terminal, and a third voltage between the first and second power supply voltages; means for supplying the first power supply voltage and the third voltage to the first output terminal;
a first switch means for alternately outputting the second power supply voltage and the third voltage to the second output terminal in synchronization with the first signal; The common electrode driver circuit includes a second switch means, an inverter receiving the voltage between the first and second output terminals as an operating voltage, and an exclusive OR signal of the first and second signals. A frequency synthesizer having a liquid crystal display circuit, comprising means for supplying an input signal to the inverter, and taking out an output of the inverter as the common electrode signal.