JPH0827465B2 - Plane display - Google Patents
Plane displayInfo
- Publication number
- JPH0827465B2 JPH0827465B2 JP8295588A JP8295588A JPH0827465B2 JP H0827465 B2 JPH0827465 B2 JP H0827465B2 JP 8295588 A JP8295588 A JP 8295588A JP 8295588 A JP8295588 A JP 8295588A JP H0827465 B2 JPH0827465 B2 JP H0827465B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- auxiliary capacitance
- pixel
- conductor
- scanning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 31
- 239000004973 liquid crystal related substance Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 10
- 239000010408 film Substances 0.000 description 19
- 239000010409 thin film Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 7
- 210000002858 crystal cell Anatomy 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は平面デイスプレイに係り、特に信頼性の高い
液晶デイスプレイに関する。The present invention relates to a flat panel display, and more particularly to a highly reliable liquid crystal display.
液晶デイスプレイは、低消費電極，薄型の特徴があ
り、応用が拡大しつつある。特に、各画素に薄膜トラン
ジスタを配したアクテイブマトリクス型液晶デイスプレ
イは、画質が良く、主流となりつつある。しかし信頼性
の点から見ると、画質の低下という問題がある。これは
液晶抵抗の経時変化（劣化）、スイツチングトランジス
タのリーク電流の増加などにより、所定の電圧が保持さ
れないため、液晶の透過率が変化し、コントラストの低
下等画質の劣化である。この対策として、各画素毎に補
助容量を形成する手法がとられている。この一例は、エ
ス・アイ・デイー,84,ダイジエスト、1984年,312頁から
315頁に述べられている（SID 84 DIGEST pp.312−31
5）。また具体的な平面及び断面構成は特開昭61−13228
号公報に示されている。Liquid crystal displays are characterized by low consumption electrodes and thin shape, and their applications are expanding. In particular, an active matrix type liquid crystal display in which a thin film transistor is arranged in each pixel has good image quality and is becoming the mainstream. However, from the viewpoint of reliability, there is a problem that the image quality is deteriorated. This is a deterioration in image quality such as a decrease in contrast due to a change in liquid crystal transmittance because a predetermined voltage is not maintained due to a change (deterioration) in liquid crystal resistance over time, an increase in leak current of a switching transistor, and the like. As a countermeasure, a method of forming an auxiliary capacitance for each pixel is adopted. An example of this is from S.I.D., 84, Digest, 1984, p. 312.
Page 315 (SID 84 DIGEST pp.312−31
Five). The specific plane and cross-sectional structure are disclosed in JP-A-61-13228.
It is shown in the publication.
第10図及び第11図により従来の補助容量の基本的な構
成を示す。画素毎に設けられた薄膜トランジスタ２のソ
ース14に画素透明電極12が設けられ、この下に絶縁膜を
介して補助容量透明電極13が設けられ、これがマトリク
ス基板端にまで連なつている。マトリクス端で補助容量
導体８で外部端子に接続される。画素透明電極12および
補助容量透明電極13共にITOが用いられる。信号線４で
送られた信号電圧は、走査線３に接続されたゲート15を
開くことにより、ドレイン16からソース14に伝達され、
画素透明電極12により液晶を駆動して容量を形成すると
ともに、絶縁膜を介して、補助容量電極13との間に、液
晶容量の数倍の容量を形成し、液晶に印加された電圧を
所定時間保持する。10 and 11 show the basic structure of a conventional auxiliary capacitance. A pixel transparent electrode 12 is provided on the source 14 of the thin film transistor 2 provided for each pixel, and an auxiliary capacitance transparent electrode 13 is provided below the transparent electrode 12 via an insulating film, and this is connected to the end of the matrix substrate. The auxiliary capacitance conductor 8 is connected to the external terminal at the matrix end. ITO is used for both the pixel transparent electrode 12 and the auxiliary capacitance transparent electrode 13. The signal voltage sent through the signal line 4 is transmitted from the drain 16 to the source 14 by opening the gate 15 connected to the scanning line 3,
A liquid crystal is driven by the pixel transparent electrode 12 to form a capacitance, and a capacitance several times as large as the liquid crystal capacitance is formed between the liquid crystal capacitance and the auxiliary capacitance electrode 13 via the insulating film, and the voltage applied to the liquid crystal is predetermined. Hold for time.
以上の構造は３〜５インチ対角の比較的小型のLCDに
適用され、その効果が実証されている。ところが、さら
に大型の液晶デイスプレイにおいては新たな問題があ
る。デイスプレイサイズが約10インチ対角以上に大きく
なると、補助容量透明電極13のみで連結した表示部内の
ラインの抵抗が大きくなり、所定走査時間内に補助容量
に十分な電荷が蓄積されなくなり、補助容量の効果がな
くなつてしまう。The above structure is applied to a relatively small LCD having a diagonal size of 3 to 5 inches, and its effect has been verified. However, there is a new problem in a larger liquid crystal display. When the display size becomes larger than about 10 inches diagonally, the resistance of the line in the display section connected only by the auxiliary capacitance transparent electrode 13 becomes large, and sufficient electric charge is not accumulated in the auxiliary capacitance within a predetermined scanning time, and the auxiliary capacitance The effect of will disappear.
以上述べたように、従来技術は、大画面デイスプレイ
の表示領域における補助容量透明電極内で発生する電位
降下については配慮されておらず、十分に補助容量の効
果を発揮できないという問題があつた。As described above, the prior art has not taken into consideration the potential drop generated in the auxiliary capacitance transparent electrode in the display area of the large-screen display, and has a problem that the effect of the auxiliary capacitance cannot be sufficiently exhibited.
本発明の目的は、大きな液晶デイスプレイにおいて、
補助容量への映像信号の書き込み速度を高速化し、画質
の良好な液晶ディスプレイを提供することにある。The object of the present invention is to provide a large liquid crystal display,
An object of the present invention is to provide a liquid crystal display having a good image quality by increasing the writing speed of a video signal to the storage capacitor.
上記目的を達成するために本発明は、各画素領域に独
立して補助容量電極を設け、画素領域を横切って延び、
シート抵抗が補助容量電極のそれより小さい補助容量導
体によって補助容量電極相互を接続することに特徴があ
る。In order to achieve the above object, the present invention provides an auxiliary capacitance electrode independently in each pixel region and extends across the pixel region,
It is characterized in that the auxiliary capacitance electrodes are connected to each other by an auxiliary capacitance conductor having a sheet resistance smaller than that of the auxiliary capacitance electrodes.
電位降下防止手段として設置した金属配線等の補助導
体は、十分低抵抗で補助容量と外部端子間における電位
降下を防止する。したがつて補助容量には所定の電荷が
蓄積されるようになるので、画質劣化を防止することが
できる。An auxiliary conductor such as a metal wiring installed as a potential drop prevention means has a sufficiently low resistance and prevents a potential drop between the auxiliary capacitance and the external terminal. Therefore, since predetermined charges are accumulated in the auxiliary capacitance, deterioration of image quality can be prevented.
特に、大きな表示領域を有する大型の平面デイスプレ
イにおいて、効果が著しい。Particularly, the effect is remarkable in a large-sized flat display having a large display area.
以下本発明の実施例を第１図〜第９図により説明す
る。An embodiment of the present invention will be described below with reference to FIGS.
第１図は、補助容量を有するマトリクス基板１の構造
概略、また第３図は、第１図の画素領域の拡大図を示
す。薄膜トランジスタ２が画素毎に配置されており、そ
のゲートが走査電極３、ドレインが信号電極４、ソース
が画素電極12にそれぞれ接続されている。各画素電極12
と対向電極７との間には液晶が挾持され、液晶セル５が
形成されている。また各画素電極12と補助容量透明電極
13とで補助容量６を形成している。すなわち、液晶セル
５及び補助容量６はともに一方の電極が画素電極12で構
成される。補助容量透明電極からは、本発明による補助
容量導体８を介して外部端子に接続するための補助容量
外部導体９に接続されている。また走査回路10,信号回
路11が内蔵されている。FIG. 1 shows a schematic structure of the matrix substrate 1 having an auxiliary capacitance, and FIG. 3 shows an enlarged view of the pixel region of FIG. A thin film transistor 2 is arranged for each pixel, and its gate is connected to the scan electrode 3, its drain is connected to the signal electrode 4, and its source is connected to the pixel electrode 12, respectively. Each pixel electrode 12
A liquid crystal is sandwiched between the counter electrode 7 and the counter electrode 7 to form a liquid crystal cell 5. In addition, each pixel electrode 12 and the auxiliary capacitance transparent electrode
A storage capacitor 6 is formed by 13 and. That is, one of the liquid crystal cell 5 and the auxiliary capacitor 6 is composed of the pixel electrode 12. The auxiliary capacitance transparent electrode is connected to an auxiliary capacitance outer conductor 9 for connecting to an external terminal through the auxiliary capacitance conductor 8 according to the present invention. Further, the scanning circuit 10 and the signal circuit 11 are built in.
第２図は、第１図において、走査回路，信号回路が内
蔵されていない点以外は、第１図と同一である。FIG. 2 is the same as FIG. 1 except that the scanning circuit and the signal circuit are not incorporated in FIG.
第４図は一画素部の具体的な構造を平面図で示した。
記号は第１図〜第３図と同一である。薄膜トランジスタ
２は、ソース14,ゲート15,ドレイン16で構成されてい
る。画素透明電極12の下に絶縁膜を介して補助容量透明
電極13が設けられ、これと隣接した画素部に形成された
補助容量透明電極とを接続する走査線３と平行に走る補
助容量導体８が設けられている。第５図は、第４図にお
けるＡ−Ａ′の断面概略図を示す。補助容量６は、補助
容量透明電極13,絶縁膜18,画素透明電極12で構成されて
いる。また、画素透明電極12と対向電極７との間に液晶
20を挾持して液晶セル５が構成される。補助容量導体８
は、走査線３と同時に形成され、材料は補助容量透明電
極よりシート抵抗が小さい材料例えばアルミニウムであ
る。第４図に示すように、走査電極３の信号電極４との
クロス部分以外は、信号線４と同時に形成した上層配線
17によつて２層配線となつている。上層配線17は薄膜ト
ランジスタのゲート２に接続される。FIG. 4 is a plan view showing a specific structure of one pixel portion.
The symbols are the same as in FIGS. 1 to 3. The thin film transistor 2 is composed of a source 14, a gate 15 and a drain 16. An auxiliary capacitance transparent electrode 13 is provided below the pixel transparent electrode 12 via an insulating film, and the auxiliary capacitance conductor 8 runs in parallel with the scanning line 3 connecting the auxiliary capacitance transparent electrode formed in the pixel portion adjacent thereto. Is provided. FIG. 5 shows a schematic sectional view taken along the line AA ′ in FIG. The auxiliary capacitance 6 is composed of an auxiliary capacitance transparent electrode 13, an insulating film 18, and a pixel transparent electrode 12. In addition, a liquid crystal is provided between the pixel transparent electrode 12 and the counter electrode 7.
A liquid crystal cell 5 is formed by holding 20. Auxiliary capacitance conductor 8
Is formed at the same time as the scanning line 3, and the material thereof is a material having a sheet resistance smaller than that of the transparent electrode of the auxiliary capacitance, such as aluminum. As shown in FIG. 4, except for the cross portion of the scanning electrode 3 with the signal electrode 4, the upper layer wiring formed at the same time as the signal line 4.
17 forms a two-layer wiring. The upper layer wiring 17 is connected to the gate 2 of the thin film transistor.
以上第１図〜第５図において、信号線４に入つた信号
電圧は、薄膜トランジスタ２を介してソース14に入り、
画素透明電極12に印加される。画素透明電極と対向電極
との間で液晶セルが構成されると同時に、補助容量透明
電極８との間に液晶セルの数倍の補助容量が形成され
る。この時、抵抗の低い補助容量導体及び信号電極から
高束で電荷が補助容量に供給される。したがつて、走査
の所定時間に、十分な書込み可能となる。補助容量導体
がメタル等不透明な場合、光を通さないが、低抵抗で細
くできるため、実質的影響はない。1 to 5, the signal voltage that has entered the signal line 4 enters the source 14 via the thin film transistor 2,
It is applied to the pixel transparent electrode 12. A liquid crystal cell is formed between the pixel transparent electrode and the counter electrode, and at the same time, an auxiliary capacitance several times as large as that of the liquid crystal cell is formed between the liquid crystal cell and the auxiliary capacitance transparent electrode 8. At this time, electric charges are supplied to the auxiliary capacitance in high flux from the auxiliary capacitance conductor having a low resistance and the signal electrode. Therefore, it becomes possible to write sufficiently in a predetermined time of scanning. When the auxiliary capacitance conductor is opaque such as metal, it does not transmit light, but has a low resistance and can be made thin, so there is no substantial effect.
第６図は異なる実施例の平面図、第７図は第６図のＢ
−Ｂ′部の断面図を示す。この画素の配線は２層となつ
ており、信号線４は下層，走査線３は上層に形成されて
いる。ここでは、補助配線導体８は、信号線４と同時に
これに沿つた方向に形成されている。またこの実施例に
おいて走査電極３と信号電極４のクロス部分に透明電極
からなる下層配線保護膜19が形成されている。この下層
配線保護膜10は、画素透明電極12と同一プロセスで信号
線４の上に形成されている。下層配線保護膜の材質はIT
Oであり、この膜は安定しており、例えばアルミニウム
で形成される下層配線の信号配線に発生する突起状のヒ
ルロツクを防止できる効果があり、二層配線の信頼性を
高める（短絡の防止）ことができる。また透明導電材料
であるITOからなる下層配線保護膜19を信号線４の上全
面に形成すれば二重配線構造とすることができ、下層配
線保護膜または信号線のいずれか一方で断線が生じても
他方で導通を確保できるため断線不良を防止できる。FIG. 6 is a plan view of a different embodiment, and FIG. 7 is B of FIG.
A sectional view of the portion -B 'is shown. The wiring of this pixel is in two layers, the signal line 4 is formed in the lower layer, and the scanning line 3 is formed in the upper layer. Here, the auxiliary wiring conductor 8 is formed at the same time as the signal line 4 in the direction along the signal line 4. Further, in this embodiment, a lower wiring protection film 19 made of a transparent electrode is formed at the cross portion of the scanning electrodes 3 and the signal electrodes 4. The lower wiring protection film 10 is formed on the signal line 4 in the same process as the pixel transparent electrode 12. The material of the lower wiring protection film is IT
O, this film is stable, and has the effect of preventing protruding hillocks that occur in the signal wiring of the lower layer wiring made of aluminum, for example, and improves the reliability of the two-layer wiring (prevention of short circuit) be able to. If a lower wiring protection film 19 made of ITO, which is a transparent conductive material, is formed on the entire upper surface of the signal line 4, a double wiring structure can be obtained, and a disconnection occurs in either the lower wiring protection film or the signal line. However, on the other hand, since continuity can be secured, disconnection defects can be prevented.
第８図は異なる実施例を示す。第５図に対応する部分
の断面図を示す。ここでは、補助容量導体８が補助容量
透明電極13の上に形成されている点が特徴である。この
構造では、補助容量透明電極13を単独で加工，熱処理等
が可能となり、製造プロセスの適用範囲が拡大される。FIG. 8 shows a different embodiment. A sectional view of a portion corresponding to FIG. 5 is shown. The feature here is that the auxiliary capacitance conductor 8 is formed on the auxiliary capacitance transparent electrode 13. In this structure, the auxiliary capacity transparent electrode 13 can be processed, heat-treated, etc. independently, and the applicable range of the manufacturing process is expanded.
第９図は異なる実施例を示す。補助容量導体８を、画
素透明電極12の下部（基板側）には形成していない。こ
の場合、補助容量導体８及び補助容量透明電極13の端部
の段差で、絶縁膜18のカバレージが悪くなって絶縁耐圧
が低くなる可能性があり、この部分の上部には補助容量
の一方の電極である画素透明電極12が形成されなくなる
（ソースへの接続のための画素透明電極12は、補助容量
透明電極13の端部段差を横切る必要はある）ため、上下
電極の短絡はなくなる。FIG. 9 shows a different embodiment. The auxiliary capacitance conductor 8 is not formed below the pixel transparent electrode 12 (substrate side). In this case, the step of the ends of the auxiliary capacitance conductor 8 and the auxiliary capacitance transparent electrode 13 may deteriorate the coverage of the insulating film 18 and lower the withstand voltage. Since the pixel transparent electrode 12 that is an electrode is not formed (the pixel transparent electrode 12 for connecting to the source needs to cross the end step of the auxiliary capacitance transparent electrode 13), the upper and lower electrodes are not short-circuited.
以上述べた実施例において、薄膜トランジスタは、単
結晶，非単結晶のシリコン、あるいは他の化合物半導体
でも同様である。また、その構造は逆スタガ、正スタガ
の、どちらの構造でも同様である。透明電極としてITO
を述べたが、SnO2，薄いシリコン膜，薄い金等のメタル
膜，薄いシリコン等の半導体膜等が使用できる。絶縁膜
として、SiO2以外に、SiN,Ta2O5，Al2O3等の絶縁膜を使
用できる。また、補助容量導体としては、アルミニウム
の外に、タングステン，モリブデン等のメタルに加え、
モリブデンシリサイド，白金シリサイド等のシリサイ
ド，低抵抗の半導体層，超伝導体層も使用できる。In the embodiments described above, the thin film transistor is also made of single crystal, non-single crystal silicon, or other compound semiconductor. Further, the structure is the same for both the inverted staggered structure and the normal staggered structure. ITO as a transparent electrode
However, SnO 2 , thin silicon film, metal film such as thin gold, semiconductor film such as thin silicon, etc. can be used. As the insulating film, an insulating film such as SiN, Ta 2 O 5 , Al 2 O 3 or the like can be used in addition to SiO 2 . In addition to aluminum, in addition to metals such as tungsten and molybdenum, as auxiliary capacitance conductors,
A silicide such as molybdenum silicide or platinum silicide, a low resistance semiconductor layer, or a superconductor layer can also be used.
また、デイスプレイとして液晶デイスプレイについて
述べたが、エレクトロルミネツセンス等のデイスプレイ
においても同様に実施することができる。Further, the liquid crystal display has been described as the display, but the same can be applied to the display such as electroluminescence.
上記実施例において、画素透明電極，補助容量透明電
極，補助容量導体は、膜質の点からスパツタリング法が
好ましい。CVD法，蒸着法も可能である。In the above embodiment, the pixel transparent electrode, the auxiliary capacitance transparent electrode, and the auxiliary capacitance conductor are preferably sputtered in terms of film quality. CVD and vapor deposition methods are also possible.
上記実施例において、画素透明電極，上層配線形成
時，静電破壊を防止するため、補助導体の電位を固定す
ることも可能である。In the above embodiment, the potential of the auxiliary conductor can be fixed in order to prevent electrostatic breakdown when forming the pixel transparent electrode and the upper layer wiring.
上記実施例において、画素間は補助容量導体のみで補
助容量電極が接続されているが、画素間及び表示部以外
の接続において、補助容量導体と補助容量電極の２層配
線とすることもできる。In the above embodiment, the auxiliary capacitance electrode is connected between the pixels only by the auxiliary capacitance conductor, but it is also possible to use a two-layer wiring of the auxiliary capacitance conductor and the auxiliary capacitance electrode in the connection between the pixels and other than the display portion.
以上、述べたように本発明では、種々の変形が考えら
れる。例えば、走査線，信号線の２層配線，回路の２層
配線の、少なくともクロス部分において、下層導体の上
部に補助容量透明電極と同一部材が配置された平面デイ
スプレイ、さらに、この上層導体上部に画素透明電極と
同一部材が形成され平面デイスプレイ、また、補助導体
が走査，信号線の下層配線と同一部材で形成された平面
デイスプレイ、さらにまた周辺駆動回路が内蔵された構
造において、マトリクス領域から引き出された補助導体
が、マトリクス領域と周辺回路領域の間に配置された平
面デイスプレイ、画素電極の主要部分が、補助容量透明
電極及び補助導体が形成する段差より内部に形成された
平面デイスプレイ、また、これらの平面デイスプレイを
用いたビデオ信号用表示システム、投射型ビデオ信号表
示システム，数値，文字，画像処理システムである。As described above, various modifications can be considered in the present invention. For example, a plane display in which the same member as the auxiliary capacitance transparent electrode is arranged above the lower layer conductor at least at the cross portion of the scanning line, the two-layer wiring of the signal line, and the two-layer wiring of the circuit, and further above this upper layer conductor. In a structure in which the same member as the pixel transparent electrode is formed, a plane display in which the auxiliary conductor is used for scanning and the lower layer wiring of the signal line is formed in the same member, and a structure in which a peripheral drive circuit is also incorporated, is extracted from the matrix region. A planar display disposed between the matrix region and the peripheral circuit region, a planar display in which the main part of the pixel electrode is formed inside the step formed by the auxiliary capacitance transparent electrode and the auxiliary conductor, and Video signal display system using these flat displays, projection type video signal display system, numerical values, characters It is an image processing system.
本発明によれば、補助容量に十分な書き込み（電荷蓄
積）を行なうことができるので、液晶デイスプレイの画
質および表示の信頼性を高めることができる。According to the present invention, since sufficient writing (charge storage) can be performed in the auxiliary capacitance, it is possible to improve the image quality and display reliability of the liquid crystal display.
第１図及び第２図は本発明を説明するためのマトリクス
基板平面構成図、第３図は本発明による画素の平面回路
図、第４図及び第５図は本発明による画素部の平面図及
びＡ−Ａ′の断面図を示す。第６図及び第７図は本発明
の応用例を説明するための画素平面図及び、Ｂ−Ｂ′部
の断面図を示す。第８図及び第９図は、本発明の応用例
を示すための画素部断面図を示す。第10図及び第11図
は、従来技術を説明するための画素平面図及びＢ−Ｂ′
部の断面図を示す。 ２……薄膜トランジスタ、３……走査電極、４……信号
電極、８……補助容量導体、12……画素透明電極、13…
…補助容量透明電極、18……絶縁膜、19……下層配線保
護膜。1 and 2 are plan views of a matrix substrate for explaining the present invention, FIG. 3 is a plan circuit diagram of a pixel according to the present invention, and FIGS. 4 and 5 are plan views of a pixel portion according to the present invention. And A-A 'sectional drawing. 6 and 7 are a pixel plan view and a cross-sectional view taken along the line BB 'for explaining an application example of the present invention. FIG. 8 and FIG. 9 are sectional views of a pixel portion for showing an application example of the present invention. FIG. 10 and FIG. 11 are a plan view of a pixel and BB ′ for explaining the prior art.
Sectional drawing of a part is shown. 2 ... Thin film transistor, 3 ... Scan electrode, 4 ... Signal electrode, 8 ... Auxiliary capacitor conductor, 12 ... Pixel transparent electrode, 13 ...
… Auxiliary capacitor transparent electrode, 18 …… insulating film, 19 …… lower layer wiring protection film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉村 雅夫 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 小西 信武 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 大和田 淳一 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (56)参考文献 特開 昭61−13228（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masao Yoshimura 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitate Manufacturing Co., Ltd., Hitachi Research Institute (72) Nobutake Konishi 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitate Manufacturing Co., Ltd. Hitachi Research Laboratory (72) Inventor Junichi Owada 4026, Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-61-13228 (JP, A)
Claims (5)
査電極と、 前記基板上に前記走査電極とは絶縁されて交差するよう
に形成され、互いに平行な複数の信号電極と、 隣合った２本の走査電極及び隣合った２本の信号電極に
よって囲まれて規定される画素領域ごとに形成された光
を透過する画素電極と、 各画素領域に形成され、ドレイン及びソースがそれぞれ
前記信号電極及び画素電極に接続され、ゲートが前記走
査電極に接続されたスイッチング素子と、 前記画素領域ごとに独立して設けられ、前記画素電極と
絶縁膜を介して対向して形成され、前記画素電極との間
に補助容量を形成する光を透過する補助容量電極と、 前記走査電極、信号電極のいずれかに沿い、前記画素領
域を横切って延び、前記補助容量電極相互を接続する、
シート抵抗が補助容量電極のそれより小さい補助容量導
体と、 画素電極群に対向して設けられた対向電極と、 前記対向電極と画素電極との間に挾持された液晶を具備
した平面ディスプレイ。1. A plurality of scanning electrodes formed on a substrate and parallel to each other, and a plurality of signal electrodes parallel to each other formed on the substrate so that the scanning electrodes are insulated and intersect with each other. A pixel electrode that transmits light formed in each pixel region defined by two scanning electrodes and two adjacent signal electrodes, and a drain and a source formed in each pixel region. A switching element, which is connected to a signal electrode and a pixel electrode and has a gate connected to the scanning electrode, is provided independently for each of the pixel regions, and is formed to face the pixel electrode with an insulating film interposed therebetween. An auxiliary capacitance electrode that transmits light forming an auxiliary capacitance between the electrode and the scanning electrode, extends along the signal electrode across the pixel region, and connects the auxiliary capacitance electrodes to each other,
A flat display comprising an auxiliary capacitance conductor having a sheet resistance smaller than that of the auxiliary capacitance electrode, a counter electrode provided so as to face the pixel electrode group, and a liquid crystal sandwiched between the counter electrode and the pixel electrode.
容量導体は前記走査電極とほぼ平行に形成された平面デ
ィスプレイ。2. The flat display according to claim 1, wherein the auxiliary capacitance conductor is formed substantially parallel to the scanning electrode.
容量導体は前記信号電極とほぼ平行に形成された平面デ
ィスプレイ。3. The flat display according to claim 1, wherein the auxiliary capacitance conductor is formed substantially parallel to the signal electrode.
容量電極は前記画素電極より前記基板側に形成され、前
記補助容量導体と重なり領域を有し、前記重なり領域に
おいて、前記補助容量導体は前記補助容量電極より前記
基板側に形成された平面ディスプレイ。4. The auxiliary capacitance electrode according to claim 1, wherein the auxiliary capacitance electrode is formed closer to the substrate than the pixel electrode, and has an overlapping region with the auxiliary capacitance conductor, and the auxiliary capacitance conductor is provided in the overlapping region. Is a flat display formed on the substrate side of the auxiliary capacitance electrode.
容量電極は前記画素電極より前記基板側に形成され、前
記補助容量導体と重なり領域を有し、前記重なり領域に
おいて、前記補助容量電極は前記補助容量導体より前記
基板側に形成された平面ディスプレイ。5. The auxiliary capacitance electrode according to claim 1, wherein the auxiliary capacitance electrode is formed closer to the substrate than the pixel electrode, and has an overlapping region with the auxiliary capacitance conductor, and the auxiliary capacitance electrode is provided in the overlapping region. Is a flat display formed on the substrate side of the auxiliary capacitance conductor.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8295588A JPH0827465B2 (en) | 1988-04-06 | 1988-04-06 | Plane display |
| KR89004449A KR0137470B1 (en) | 1988-04-06 | 1989-04-04 | Flat panel display |
| US07/869,085 US5283566A (en) | 1988-04-06 | 1992-04-15 | Plane display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8295588A JPH0827465B2 (en) | 1988-04-06 | 1988-04-06 | Plane display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01255831A JPH01255831A (en) | 1989-10-12 |
| JPH0827465B2 true JPH0827465B2 (en) | 1996-03-21 |
Family
ID=13788642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8295588A Expired - Lifetime JPH0827465B2 (en) | 1988-04-06 | 1988-04-06 | Plane display |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0827465B2 (en) |
| KR (1) | KR0137470B1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162901A (en) * | 1989-05-26 | 1992-11-10 | Sharp Kabushiki Kaisha | Active-matrix display device with added capacitance electrode wire and secondary wire connected thereto |
| JPH03163529A (en) * | 1989-11-22 | 1991-07-15 | Sharp Corp | Active matrix display device |
| JPH06208132A (en) * | 1990-03-24 | 1994-07-26 | Sony Corp | Liquid crystal display device |
| KR960001611B1 (en) | 1991-03-06 | 1996-02-02 | 가부시끼가이샤 한도다이 에네르기 겐뀨쇼 | Insulated gate field effect semiconductor device and fabrication method thereof |
| US6979840B1 (en) | 1991-09-25 | 2005-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistors having anodized metal film between the gate wiring and drain wiring |
| TW444257B (en) * | 1999-04-12 | 2001-07-01 | Semiconductor Energy Lab | Semiconductor device and method for fabricating the same |
| KR100770543B1 (en) * | 2001-03-20 | 2007-10-25 | 엘지.필립스 엘시디 주식회사 | LCD and its driving method |
| WO2010106710A1 (en) * | 2009-03-18 | 2010-09-23 | シャープ株式会社 | Active matrix substrate and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6113228A (en) * | 1984-06-28 | 1986-01-21 | Matsushita Electric Ind Co Ltd | Liquid crystal picture display device |
-
1988
- 1988-04-06 JP JP8295588A patent/JPH0827465B2/en not_active Expired - Lifetime
-
1989
- 1989-04-04 KR KR89004449A patent/KR0137470B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR890016413A (en) | 1989-11-29 |
| KR0137470B1 (en) | 1998-05-15 |
| JPH01255831A (en) | 1989-10-12 |
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