JPH0824180B2 - How to configure the electrode extraction part - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of configuring an electrode lead-out portion in a semiconductor integrated circuit device.

(Prior Art) With recent progress in high density and high integration of semiconductor integrated circuit devices, ultra-miniaturization of integrated elements and multilayering of wiring layers are major problems to be solved. Above all, it is difficult to miniaturize metal wiring, and there are many technical problems to be solved in order to make generally used aluminum wiring finer than 1 μm. The formation of holes, the instability of the connection due to the deterioration of the coverage of the aluminum wiring in the contact hole, and the variety of the depth of the contact hole in the electrode lead-out portion due to the multi-layered wiring are considered.

FIG. 4 is a diagram for explaining the above problems by taking an NMOS type DRAM as an example. FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along line XX ′, showing one capacitor having a trench capacitor. A memory cell forming one bit by one transistor is shown. Hereinafter, the electrode part will be mainly described with reference to FIG. 2B showing the contact hole and the electrode extraction part (Nikkei Microdevices Separate Volume, 1987, No. 1, p117, and p.
133).

In FIG. 2B, 1 is a P-type silicon substrate, in which an element isolation region 2 and a groove 3 are formed, an N ⁺ diffusion layer 4 is formed on the inner wall thereof, and a capacitive insulating film 5 is formed on the upper surface thereof. The crystalline silicon electrode 6 is buried to form a trench capacitor. Further, a gate insulating film 7, a polycrystalline silicon film 8 serving also as a word line, a source / drain diffusion layer 9,
The transfer gate transistors are composed of 9a, and an interlayer insulating film 10 and a contact hole are formed on the upper surfaces thereof.
11 and an aluminum alloy film 12 forming a bit line are provided. The surface protective film is omitted.

The contact hole 11 has an area of 1 μm ² , the thickness of the interlayer insulating film 10 is 1 μm, and a mask alignment margin of 0.6 μm for the polycrystalline silicon film 8 is provided. Therefore, in order to form the contact hole 11, the interval between the polycrystalline silicon films 8 on both sides must be at least 2.2 μm or more. In addition, it is difficult to uniformly vapor-deposit the aluminum alloy on the contact hole 11 having an opening with a high aspect ratio of 1 μm ² and a depth of 1 μm. The film thickness of aluminum vapor deposition becomes thin, and microcracks are generated at the bottom corners.

As described above, in the structure of the electrode portion of the semiconductor integrated circuit device, if the diameter of the contact hole is reduced to 1.0 μm, it becomes difficult for aluminum atoms to sufficiently enter the inside of the contact hole during the aluminum alloy vapor deposition process. Therefore, it becomes impossible to form a stably connected electrode with a uniform aluminum coating.

(Problems to be Solved by the Invention) In view of the above problems in the conventional electrode part configuration, the present invention is applicable to electrode extraction having a fine structure of a high-density semiconductor integrated circuit device, and maintains connection stability. It is an object of the present invention to provide a method of forming an electrode structure that can be easily formed.

(Means for Solving the Problems) The present invention has the above-mentioned object to form a contact hole in an insulating film formed on the main surface of a semiconductor substrate having an impurity diffusion layer and connect an electrode to the impurity diffusion layer. Window, a step of sequentially depositing a silicon nitride film and a polycrystalline silicon film over the entire main surface of the semiconductor substrate including the contact hole, and anisotropic etching of the polycrystalline silicon film selectively. A step of selectively leaving a polycrystalline silicon film on the inner wall surface of the contact hole, a step of forming an insulating film by oxidizing the remaining polycrystalline silicon film, and a step of nitriding exposed at the bottom of the contact hole. The step of exposing the impurity diffusion layer by removing the silicon film and the step of depositing one or a plurality of conductive coatings and forming a wiring pattern on the conductive coatings are carried out. This is achieved by taking out the electrodes in the integrated circuit device.

(Operation) According to the present invention having the above electrode configuration, the electrode can be stably taken out from the fine contact hole, and the reliability of the semiconductor integrated circuit device can be improved.

(Example) The present invention will be described below by way of an example with reference to the drawings.

FIG. 1 is a diagram for explaining the first embodiment of the present invention, and in the same way as FIG. 4 described above, taking an NMOS type DRAM as an example, a memory cell forming one bit from one transistor having one trench capacitor and one capacitor is shown. Figure (a) is a plan view,
FIG. 6B is a sectional view taken along the line XX '.

Similar to FIG. 4, this is composed of an element isolation region 2 and a groove 3 formed in a P-type silicon substrate 1, an N ⁺ diffusion layer 4 on the side wall thereof, a capacitive insulating film 5 on the upper surface thereof, and a polycrystalline silicon electrode 6. Trench capacitor and the gate insulating film 7,
A transfer gate transistor including a polycrystalline silicon film 8 also serving as a word line, source / drain diffusion layers 9 and 9a, an interlayer insulating film 10, and a silicon dioxide film in which the sidewall of the polycrystalline silicon film 8 is oxidized on the inner walls of the contact hole 11. 13, a silicon nitride film 21a, and a silicon dioxide film 23 are formed, and are insulated by the three-layer film to separate the polycrystalline silicon film 8 which is a word line from the aluminum alloy film 12 which constitutes a bit line. There is. The protective film is omitted in the above description.

FIG. 2 is a cross-sectional view showing the steps for constructing the electrode section shown in FIG.

First, the element isolation regions 2 and 3 made of silicon dioxide are formed on the main surface of the P-type silicon substrate 1, the N ⁺ diffusion layer 4 is formed on the inner wall of the groove 3, and the capacitive insulating film 5 is formed thereon. A trench capacitor having a polycrystalline silicon electrode 6 embedded therein, a transfer gate transistor including a gate insulating film 7, a polycrystalline silicon film 8 also serving as a word line, and source / drain diffusion layers 9 and 9a are formed. An interlayer insulating film 10 is deposited on the main surface and is flattened by heat treatment or the like.

Next, as shown in FIG. 2B, a contact hole 11 is opened corresponding to the source / drain diffusion layer 9a of the interlayer insulating film 10. At this time, as shown in FIG. 1 (b), unlike the conventional method, the polycrystalline silicon film 8 is partially overlapped and opened. Inside the opening, the sidewall 111 of the interlayer insulating film 10,
The side wall 112 of the polycrystalline silicon film 8 constitutes the inner wall of the contact hole 11, and the source / drain diffusion layer 9a is exposed at the bottom. In this embodiment, the polycrystalline silicon film 8
A hole was formed by partially overlapping the contact hole 11 and the polycrystalline silicon film 8 as in the conventional example of FIG.
A space may be provided between the contact hole and
The oxide film etching for forming 11 can be easily processed by known dry etching.

Next, as shown in FIG. 2C, the side wall 111 of the interlayer insulating film 10 forming the inner wall of the contact hole 11, the side wall 112 of the polycrystalline silicon film 8 and the like are thinly oxidized to form the silicon dioxide film 1
After forming 3, the silicon nitride film 21 is sequentially deposited to a thickness of 50 nm and the polycrystalline silicon film 22 is similarly deposited to a thickness of 50 nm.

Next, as shown in FIG. 2D, anisotropic dry etching was performed using a mixed gas of sulfur hexafluoride (SF ₆ ) and Freon 115 (C ₂ ClF ₅ ), and the side wall 111 of the interlayer insulating film 10 and the multi-layered film were removed. The polycrystalline silicon film 22 is left only on the side wall 112 of the crystalline silicon film 8 to form a polycrystalline silicon film 22a, which is shown in FIG.
And is converted into the silicon dioxide film 23. Further, using this silicon dioxide film 23 as a mask, the silicon nitride film 21 is removed by anisotropic dry etching with a mixed gas of CF ₄ , O ₂ and CH ₃ Br to remove the silicon dioxide film forming the inner wall of the contact hole 11. Only the silicon nitride film 21a sandwiched between the films 23 is left. Further, the source / drain diffusion layer 9a at the bottom of the contact hole 11 is exposed, the aluminum alloy film 12 is vapor-deposited, and then an aluminum wiring pattern forming a bit line or the like is formed by well-known photo etching and an annealing treatment is performed to take out the electrode The department is composed.

At this time, the contact hole 11 is self-aligned with the polycrystalline silicon film 8 (word line) as shown in FIG. 1 (a) and is opened in a rectangular shape in the lateral direction to form a contact hole having a substantially large area. It is formed. The aluminum alloy film 12 and the polycrystalline silicon film 8 are the oxide film 13, the silicon nitride film 21a, and the silicon dioxide film 2 on the sidewalls of the polycrystalline silicon film 8.
It is insulated by the three-layered film of 3 and therefore, the withstand voltage of about 30 V or more is secured and the withstand voltage is sufficient. Further, since a contact hole having a substantially large area can be formed, the coverage of a metal such as aluminum into the contact hole is improved.

FIG. 3 is a cross-sectional view of the manufacturing process for explaining the second embodiment, showing a simplified portion of the electrode taken out from the contact hole 11 in FIG.

FIG. 3A shows a P-type silicon substrate 1, a gate insulating film 7, a polycrystalline silicon film 8, source / drain diffusion layers 9 and 9a.
1 shows a structure in which a MOS transistor made of is covered with an interlayer insulating film 10. A contact hole 11 is formed in this, as shown in FIG. 3 (b), and the opening is overlapped with the polycrystalline silicon film 8 as in the first embodiment.

Next, as shown in FIG. 3C, a silicon nitride film 21 and a polycrystalline silicon film 22 are laminated so as to cover the contact hole 11,
It is oxidized to form a silicon dioxide film 23 (FIG. 3 (d)).

Next, as shown in FIG. 3 (e), anisotropic dry etching is performed to leave the silicon dioxide film 23 and the silicon nitride film 21 only on the inner wall of the contact hole 11, and then the aluminum alloy film 12 is coated to cover the electrode. To form the take-out part of.

Even if the coated polycrystalline silicon film 22 is oxidized to form the silicon dioxide film 23 as in this embodiment, and is left together with the silicon nitride film 21 only on the inner wall of the contact hole 11 by anisotropic dry etching, The same electrode extraction effect as in the first embodiment can be obtained. Further, the same effect can be obtained even if the aluminum electrode is made into a metal electrode wiring composed of a two-layer film of a heat resistant alloy and an aluminum alloy by miniaturizing the pattern,
Furthermore, the present invention can be applied even if the conductive electrode is a polycrystalline silicon film and a metal silicide, for example, a polycrystalline silicon film and a tungsten silicide.

(Effects of the Invention) As will be apparent from the above description, the present invention can be applied to the formation of an electrode having a fine structure of a high-density semiconductor device, for example.
Even when forming a contact hole with a high aspect ratio of 1.0 μm square and depth of 1.0 μm, the contact hole mask alignment margin to the polycrystalline silicon film is not required, and the contact hole opening area is substantially expanded. It is possible to improve the coating property of aluminum alloy or the like by vapor deposition and to stably take out the electrode. In addition, since the mask alignment of the contact holes to the polycrystalline silicon is self-aligned, the degree of integration can be improved at the same time. Further, since the aluminum electrode and the polycrystalline silicon film are insulated by the multilayer film of the silicon nitride film and the silicon dioxide film, the withstand voltage is 30%.
Since it is V or more and it does not depend on the accuracy of mask alignment, it has an effect of greatly improving the reliability of the semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing an essential part of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a sectional view of the manufacturing process thereof, and FIG. 3 is a manufacturing process diagram of the second embodiment. FIG. 4 is a plan view and a sectional view showing a conventional example of an electrode lead-out portion of a semiconductor integrated circuit device. 1 ... P-type silicon substrate, 2 ... Element isolation region, 3 ...
Groove, 4 ... N ⁺ diffusion layer, 5 ... Capacitance insulating film, 6 ... Polycrystalline silicon electrode, 7 ... Gate insulating film, 8 ... Polycrystalline silicon film, 9,9a ... Source / drain diffusion layer, 10 …… Interlayer insulating film, 11 …… Contact hole, 111 …… (Interlayer insulating film 1
Side wall (of 0), 112 ... Side wall (of polycrystalline silicon film 8), 12
...... Aluminum alloy film, 13,23 ...... Silicon dioxide film, 21,21a ...
… Silicon nitride film, 22,22a …… Polycrystalline silicon film.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/822 27/04 29/43 H01L 21/88 T 21/90 C 27/04 E

Claims (1)

[Claims] 1. A step of forming a contact hole in an insulating film formed on a main surface of a semiconductor substrate having an impurity diffusion layer and providing a window for connecting an electrode to the impurity diffusion layer,
A step of sequentially depositing a silicon nitride film and a polycrystalline silicon film over the entire main surface of the semiconductor substrate including the contact hole, and selectively anisotropically etching the polycrystalline silicon film to form an inner wall surface of the contact hole. A step of selectively leaving the polycrystalline silicon film remaining, a step of forming an insulating film by oxidizing the remaining polycrystalline silicon film, and removing the silicon nitride film exposed at the bottom of the contact hole, Structure of electrode take-out portion characterized by taking out an electrode in a semiconductor integrated circuit device by a step of exposing an impurity diffusion layer and a step of depositing one or a plurality of conductive films and forming a wiring pattern on the conductive film Method.