JP3200974B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device called a bit line shield type stacked capacitor type DRAM.

[0002]

2. Description of the Related Art In a bit line shield type stacked capacitor type DRAM, a capacitor constituting a memory cell is formed after a bit line is formed, and the capacitor shields the bit line. Is small, there is little noise due to capacitive coupling between these adjacent bit lines.

In addition, since the capacitor can be extended over the contact portion between the transistor constituting the memory cell and the bit line, it is necessary to increase the area of the capacitor relative to the area of the memory cell to increase the memory cell capacity. Can be. Therefore, even if the memory cell area is reduced,
The required memory cell capacity can be secured. For these reasons, the bit line shield type multilayer capacitor type D
The RAM is considered suitable for miniaturization and high integration.

In order to manufacture such a bit line shield type stacked capacitor type DRAM, a contact hole for electrically connecting a storage node electrode of a capacitor and a diffusion layer of a transistor is opened from a layer above the bit line. Need to make a hole. Conventionally, a contact hole has been formed using a mask processed into the pattern of the contact hole.

[0005]

However, if a mask is used to form a contact hole for a storage node electrode, a lithography step or the like for patterning the mask is required. Therefore, with the conventional manufacturing method, it was not possible to manufacture a bit line shield type multilayer capacitor type DRAM in a small number of steps.

[0006]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising:
Storage node electrode 3 through contact holes 25 and 36
In a method for manufacturing a semiconductor memory device in which a memory cell is constituted by a capacitor 43 to which transistors 4 and 37 are electrically connected and the transistor 17, a bit line 32 is formed on a first insulating film 33 on the bit line 32. A step of forming the first conductive film 34 on the first insulating film 33 in the same pattern as the first conductive film 34;
Forming a contact hole 36 surrounded by the second insulating film 35, and covering the contact hole 36 and the first conductive film 34 with a second conductive film 37. Forming the storage node electrodes 34 and 37 by using the second conductive film 37 and the first conductive film 34.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device.
The other diffusion layer 16 of the transistor 17 and the bit line 32 are electrically connected through third conductive films 22 and 27.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device.
The thickness of the first conductive film 34 is set to 500 nm or more.

[0009]

In the method of manufacturing a semiconductor memory device according to the first aspect, the side wall made of the second insulating film 35 insulates the bit line 32 from the storage node electrodes 34 and 37. The contact holes 36 for the electrodes 34 and 37
By etching back the second insulating film 35 deposited on the entire surface, it is possible to form the second insulating film 35 in a self-aligned manner with respect to the bit line 32. Therefore, the storage node electrode 34,
A mask for opening the contact hole 36 for 37 is unnecessary.

In addition, since the surface area of the storage node electrodes 34 and 37 can be increased by the side surfaces of the first conductive film 34, the memory cell capacity can be increased relative to the planar area of the memory cell.

In the method of manufacturing a semiconductor memory device according to the second aspect, the third conductive films 22 and 27 are extended to the element isolation region 12, and the bit line 32 is connected to the third conductive film on the element isolation region 12. By contacting the films 22 and 27, the element active regions forming the diffusion layers 15 and 16 of the transistor 17 and the bit line 32 are patterned in parallel with each other, and the capacitor 43 is formed after the bit line 32. The electrical connection between one of the diffusion layers 15 of the transistor 17 and the storage node electrodes 34 and 37 is not affected.

In the method of manufacturing a semiconductor memory device according to the third aspect, the width of the side wall formed by etching back the second insulating film 35 deposited on the entire surface is increased to increase the bit line 32 and the storage node electrodes 34, 37. And the storage node electrodes 34 and 37 are three-dimensionally formed, and the surface area thereof is sufficiently increased to sufficiently increase the memory cell capacity for the planar area of the memory cell. .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In this embodiment, as shown in FIGS. 1A and 3, an SiO ₂ film 12 is formed on the surface of an element isolation region of a Si substrate 11 by a LOCOS method or the like.
An SiO ₂ film 13 as a gate oxide film is formed on the surface of the element active region surrounded by the _two films 12.

Thereafter, in the memory cell region, a gate electrode serving as a word line is formed by the W-polycide film 14 or the like, and the impurity concentration is set to 10 ¹⁸ cm ^{− using the} W-polycide film 14 and the SiO ₂ film 12 as a mask. N-type diffusion layers 15 and 16 of about ³ are formed on the Si substrate 11. Thus, the transistor 17 included in the memory cell is completed.

Thereafter, the side wall 18 is formed on the W-polycide film 14.
Is formed, and only the transistors (not shown) in the peripheral circuit region are formed into an LDD structure by using the side walls 18 as LDD spacers. Then, as the interlayer insulating film 21, a PSG film, a SiO ₂ film containing no impurities, or a Si
An N film or a film combining these is deposited on the entire surface.

Next, as shown in FIG.
An opening 23 and the like are formed in the polycrystalline Si film 22 on the diffusion layers 15 and 16 using a patterned resist (not shown) as a mask.
Then, an SiO ₂ film 24 or a polycrystalline Si film is deposited on the entire surface, and the entire surface of the SiO ₂ film
And etch back continuously.

As a result, the side wall composed of the SiO ₂ film 24 and the like is formed in a self-aligned manner on the inner periphery of the opening 23 and the like.
As shown in FIG. 3, contact holes 25 and 26 reaching the diffusion layers 15 and 16 are formed in the interlayer insulating film 21 in a self-aligned manner with respect to the openings 23 and the like in the pattern surrounded by the side walls. . Therefore, if the size of the opening 23 and the like is set to the limit of lithography, the contact holes 25 and 26 become smaller than the limit of lithography.

Thereafter, a polycrystalline Si film 27 is deposited on the entire surface, and is isolated as a pattern isolated on the diffusion layer 15 and extended from the diffusion layer 16 onto the SiO ₂ film 12, as shown in FIG. The polycrystalline Si film 27 is processed into a pattern.

Next, as shown in FIG. 1C, after an interlayer insulating film 28 is formed by a BPSG film or the like, as shown in FIG.
A contact hole 31 that reaches a portion on the SiO ₂ film 12 in the polycrystalline Si film 27 in an isolated pattern extending from the diffusion layer 16 to the SiO ₂ film 12 is formed.
A hole is formed in the interlayer insulating film 28.

Thereafter, a W-polycide film 32, an interlayer insulating film 33 and a polycrystalline Si film 34 are successively deposited on the entire surface by a CVD method. As the interlayer insulating film 33, a BPSG film, a SiO ₂ film containing no impurities, a PSG film, a SiN film, or a combination thereof is used. In addition, polycrystalline Si
The film 34 has a thickness of several hundred nm to several μm.

Then, using a resist (not shown) of a bit line pattern as a mask, these polycrystalline Si film 34, interlayer insulating film 33 and W-polycide film 32 are different from each other as shown in FIG. By performing isotropic etching, a bit line made of the W-polycide film 32 is formed. Therefore, the W-polycide film 32 serving as a bit line is electrically connected to the diffusion layer 16 via the contact hole 31, the polycrystalline Si films 27 and 22, and the contact hole.

Next, as shown in FIG. 2A, an SiO ₂ film 35 having good step coverage is deposited on the entire surface by a normal pressure CVD method using TEOS and O ₃ as source gases. At this time, the thickness of the SiO ₂ film 35 is set to several numbers so that portions of the W-polycide films 32 and the like of the bit line patterns adjacent to each other which are close to each other, that is, portions near the contact holes 31 are completely filled. It is set to tens to hundreds of nm. Then, the SiO ₂ film 35
And the interlayer insulating film 28 are continuously etched back.

As a result, in the W-polycide film 32 and the like of the bit line pattern adjacent to each other, only the portion having a large interval, that is, the portion on the contact hole 25 is formed of SiO _2.
A side wall made of film 35 is formed in a self-aligned manner with respect to W-polycide film 32 and the like, and contact hole 3 reaching polycrystalline Si film 27 in a pattern surrounded by the side wall.
6 is opened in the interlayer insulating film 28 also in a self-aligned manner with respect to the W-polycide film 32 and the like. After that, the film thickness becomes several tens n
A polycrystalline Si film 37 of m is deposited on the entire surface by the CVD method, and a resist 38 is processed on the polycrystalline Si film 37 into a pattern of a storage node electrode.

Next, using the resist 38 as a mask, the polycrystalline Si films 37 and 34 are anisotropically etched to obtain a structure shown in FIG.
Then, as shown in FIG. 3, a storage node electrode composed of the polycrystalline Si films 34 and 37 is formed. Therefore, the polycrystalline Si films 34 and 37 serving as storage node electrodes are electrically connected to the diffusion layer 15 via the contact holes 36, the polycrystalline Si film 27, and the contact holes 25.

At this time, with respect to anisotropic etching of a portion of the polycrystalline Si films 37 and 34 on the W-polycide film 32, the interlayer insulating film 28 is used as a stopper and the polycrystalline Si films 37 and 34 are As described above, the anisotropic etching of the portion between the W-polycide films 32 is performed as described above. The SiO ₂ film 35 left thick in the vicinity of 31 is used as a stopper.

After that, a dielectric film 41 is formed on the entire surface with a SiN film, a Ta ₂ O ₅ film or the like, and polycrystalline Si doped with phosphorus is formed.
A film 42 is deposited on the entire surface by a CVD method. Then, the polycrystalline Si film 42 and the dielectric film 41 are processed into a pattern of a plate electrode to complete the capacitor 43 constituting the memory cell. Further, a metal wiring composed of a W film, an Al film or the like, a surface protection film, and the like are formed to complete the bit line shield type laminated capacitor DRAM.

[0027]

According to the method of manufacturing a semiconductor memory device of the first aspect, a mask for forming a contact hole for a storage node electrode is not required, so that the semiconductor memory device can be manufactured in a small number of steps. In addition, since the memory cell capacity can be increased relative to the planar area of the memory cell, a fine and highly integrated semiconductor memory device can be manufactured.

According to the method of manufacturing a semiconductor memory device of the present invention, since the element active region and the bit line can be patterned in parallel to each other even in the case of the bit line shield type, the planar area of the memory cell can be further increased. By reducing the size, a finer and more highly integrated semiconductor memory device can be manufactured.

According to the method of manufacturing a semiconductor memory device of the present invention, the memory cell capacity can be sufficiently increased for the planar area of the memory cell. Can be manufactured.

[Brief description of the drawings]

FIG. 1 is a side sectional view of a bit line shield type laminated capacitor type DRAM in a manufacturing step in the first half of an embodiment of the present invention, taken along a line AA of FIG. 3; .

FIG. 2 is a side sectional view taken along a line AA of FIG. 3, sequentially showing the DRAM in a manufacturing step in the latter half of the embodiment;

FIG. 3 is a plan view of a DRAM manufactured in one embodiment.

[Explanation of symbols]

Reference Signs List 15 diffusion layer 16 diffusion layer 17 transistor 22 polycrystalline Si film 25 contact hole 27 polycrystalline Si film 32 W-polycide film 33 interlayer insulating film 34 polycrystalline Si film 35 SiO ₂ film 36 contact hole 37 polycrystalline Si film 43 capacitor

Claims (3)

(57) [Claims] 1. A method for manufacturing a semiconductor memory device comprising: a transistor in which a memory cell is constituted by a capacitor in which a storage node electrode is electrically connected to one diffusion layer of a transistor via a contact hole and said transistor; The first insulating film on the bit line and the first insulating film on the bit line;
Forming the same pattern as the first conductive film on the insulating film, and forming a second insulating film as a side wall of the pattern, and simultaneously forming the contact hole surrounded by the second insulating film. Opening a hole, covering the contact hole and the first conductive film with a second conductive film, and forming the storage node electrode with the second conductive film and the first conductive film; A method for manufacturing a semiconductor memory device, comprising: 2. The method according to claim 1, wherein the other diffusion layer of the transistor and the bit line are electrically connected via a third conductive film. 3. The method according to claim 1, wherein the first conductive film has a thickness of 500 nm or more.