JPH08236752A - Hetero junction field effect transistor - Google Patents

Abstract

PURPOSE: To improve the pinch off property by incorporating InP/In0.52 Al0.48 As superlattice of, at least, two periods or more within the buffer layer existing between an operation layer where carriers are running and an InP substrate. CONSTITUTION: A superlattice 114 (for example 20 periods) consisting of an In0.52 Al0.48 As layer 112 and an InP layer 113, a GaInPAs operation layer 115, an AlInAs spacer layer 116, an AlInAs carrier supply layer 117, and an AlInAs Schottky layer 118 are grown in order on an InP substrate 11. This transistor is made by arranging an ohmic electrode (source electrode 119 and a drain electrode 120) and a Schottky electrode (gate electrode 121) thereon. This way, the propagation to the operation layer of disposition existing in the InP substrate can be suppressed by using a superlattice consisting of the InP layer different in constituent matter from In0.52 Al0.48 As and In0.52 Al0.48 As layer as a buffer layer.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to heterojunction field effect transistors on InP substrates.

[0002]

2. Description of the Related Art Conventionally, in a heterojunction field effect transistor on an InP substrate, In which is lattice-bonded to the InP substrate is used.
The InAlAs / InGaAs superlattice that prevents the generation of a two-dimensional electron gas at the interface between the buffer layer and the operating layer, which occurs when only the AlAs layer is used as the buffer layer, and uses the InAlAs / InGaAs superlattice that is lattice-bonded to the InP substrate is used as the buffer layer. In order to prevent the occurrence of a two-dimensional electron gas in the InGaAs layer in the superlattice in some cases, a structure using an InAlAs / InGaAs superlattice as a buffer layer was proposed in Japanese Patent Application Laid-Open No. 63-27827 in 1988. ing.

FIG. 2 (a) shows a cross-sectional structural view of the field effect transistor described in the above publication, and FIG. 2 (b) shows an energy band diagram showing a change in conduction band. 211 is an InP substrate, 212 is an InAlAs / InGaAs superlattice, 21
3 is an InGaAs operating layer, 214 is an n-InAlAs electron supply layer, 215 is an n-InGaAs contact layer, 2
16 is a source electrode, 217 is a gate electrode, and 218 is a drain electrode. In this structure, In
Impurities serving as deep donors are trapped at the hetero interface lattice-bonded to the P substrate, and the InGaAs operating layer 213 and In
Generation of a two-dimensional electron gas at the interface with the AlAs buffer layer 212 is suppressed. InP as a buffer layer
Compared to a structure using an InAlAs / InGaAs superlattice that is lattice-bonded to a substrate, InAlG is better than an InGaAs layer.
Since the aAs layer has a larger band gap, the two-dimensional electron gas generated in the InAlGaAs layer in the superlattice is reduced.

[0004]

However, in the conventional structure, the GaAs composition ratio of the InAlGaAs layer is 0.8.
When it is lower than 7, the difference in composition between the two layers of AlInAs and InAlGaAs is small, so that dislocations existing in the InP substrate propagate to the operating layer and Fe added to increase the resistance of the InP substrate is added. The effect of suppressing the diffusion of impurities is small, the crystallinity of the operating layer deteriorates, and the mutual conductance of the transistors becomes low. In addition, AlInAs
The layer is an n-type of about 1 × 10 ¹⁵ / cm ³ , and in the conventional structure, the GaAs composition ratio of the InAlGaAs layer is 0.8.
When it is higher than 7, the bandgap of the InAlGaAs layer is smaller than that of the InP substrate, so AlInAs / I
The thickness of the nAlGaAs superlattice buffer layer is adjusted to eliminate the propagation of dislocations existing in the InP substrate to the operating layer, and the diffusion of impurities such as Fe added to increase the resistance of the InP substrate into the operating layer. If the thickness is sufficient to
Electrons are generated in the AnAs / InAlGaAs superlattice buffer layer, an electron conduction path is formed in a layer other than the operating layer, and the pinch-off characteristic of the transistor is deteriorated.

An object of the present invention is to eliminate the above-mentioned drawbacks in the prior art, to propagate dislocations existing in the InP substrate to the operating layer, or to add impurities such as Fe added for increasing the resistance of the InP substrate. An object of the present invention is to provide a heterojunction field effect transistor having a good pinch-off characteristic, in which an electron conduction path is not formed in the buffer layer while eliminating the influence and maintaining a high transconductance.

[0006]

To achieve the above object, according to a basic aspect of the present invention, in a heterojunction field effect transistor on an InP substrate, an operating layer on which carriers travel and the InP substrate are formed. InP / In _0.52 Al of at least 2 cycles or more in the buffer layer existing between
A heterojunction field effect transistor is provided that includes a _0.48 As superlattice.

The total thickness of the buffer layer in the basic embodiment is 5
It is in the range of 0 nm to 400 nm, and the material forming the operating layer is GaInAs, InP, GaInAsP, I.
1 selected from the group consisting of nSb and InGaSb
In addition, the GaAs composition ratio in the operating layer is in the range of 0 to 1.

According to another aspect of the present invention,
At least two cycles of In _0.52 Al on the InP substrate
_0.48 Superlattice composed of As layer and InP layer, GaInAs
There is provided a heterojunction field effect transistor characterized in that an operating layer, an AlInAs spacer layer, an AlInAs carrier supply layer, and an AlInAs Schottky layer are sequentially grown, and a source electrode, a drain electrode and a gate electrode are arranged on the growth layer.

[0009]

In the present invention, since the buffer layer is composed only of a substance having a band gap equal to that of the InP substrate and a substance having a band gap larger than that of the InP substrate, AlI
The accumulation of electrons in the buffer layer due to the nAs layer being an n-type of about 1 × 10 ¹⁵ / cm ³ is suppressed. Further, since the constituent materials of the two layers forming the hetero interface are different from each other, dislocation existing in the InP substrate at the hetero interface propagates to the operating layer, or impurities such as Fe added for increasing the resistance of the InP substrate are added. Diffusion into the operating layer is suppressed. Therefore, an operating layer having good crystallinity can be obtained, the buffer layer can be thinned, and an electron conduction path is not formed in the buffer layer. Therefore, the FET can obtain good pinch-off characteristics without reducing the transconductance.

[0010]

The preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 (a) is a sectional view showing the structure of an embodiment of the present invention as defined in claim 1, and FIG. 1 (b) is shown in FIG.
It is an energy band figure showing the change of the conduction band in (a). The field effect transistor shown in FIG. 1A has an In _0.52 Al _0.48 As layer 1 on an InP substrate 111.
Superlattice 114 (for example, 20) composed of 12 (for example, 5 nm in thickness) and InP layer 113 (for example, 5 nm in thickness)
Period), GaInAs operating layer 115 (eg GaAs
Composition ratio 0.47, film thickness 45 nm), AlInAs spacer layer 116 (eg AlAs success / failure 0.48, film thickness 4 nm), AlInAs carrier supply layer 117 (eg AlAs composition ratio 0.48, film thickness 15 nm), AlIn
An As Schottky layer 118 (for example, AlAs composition ratio 0.48, film thickness 15 nm) is sequentially grown, and an ohmic electrode (source electrode 119, drain electrode 12) is formed thereon.
0), a Schottky electrode (gate electrode 121) is arranged. However, Si of 3 × 10 ¹⁸ cm ⁻³ , for example, is added to the AlInAs carrier supply layer 117.

In this way, In _0.52 A is used as the buffer layer.
By using a superlattice consisting of l _0.48 As layer and the different InP layer of constituents to and the In _0.52 Al _0.48 As layer, by suppressing the propagation of the active layer of the dislocations present in the InP substrate, the buffer layer The thickness can be reduced to 200 nm, an electron conduction path is not formed in the buffer layer, and a transistor having excellent pinch-off characteristics can be obtained.

In this embodiment, In forming the superlattice is used.
_{Although the} thickness of each of the _0.52 Al _0.48 As layer and the InP layer is set to 5 nm, the thickness of each layer forming the superlattice can be set to a desired thickness. However, when the thickness of the entire buffer layer exceeds 400 nm, electrons accumulate in the buffer layer,
There is a risk of forming a conduction path, and if the thickness is less than 50 nm, I
The total thickness of the buffer layer is 50 nm to 400 nm, because the propagation of dislocations existing in the nP substrate to the operating layer and the diffusion of impurities such as Fe in the InP substrate may not be completely removed.
It is preferably in the range of.

The operating layer 115 is a GaInAs layer and the GaAs composition ratio is 0.47. The constituent materials are InP, GaInAsP, InSb and InGaS.
b and the GaAs composition ratio can be changed from 0 to 1.

Similarly, the AlInAs carrier supply layer 11
7. The AlAs composition ratio of the AlInAs Schottky layer 118 can also be changed from 0.48 to 1.0.

Further, the doping concentration can be a desired concentration.

As for the dopant, since electrons were used as carriers in this example, S was used as the n-type dopant.
Although i is used, any other n-type dopant such as S or Se may be used. In a heterojunction field effect transistor that uses holes as carriers, a p-type dopant such as Be or C can be used.

[0018]

According to the present invention, the propagation of dislocations existing in the InP substrate to the operating layer or the influence of impurities such as Fe added for increasing the resistance of the InP substrate on the operating layer is eliminated. It is possible to obtain a heterojunction field effect transistor having good pinch-off characteristics without forming an electron conduction path in the buffer layer while maintaining high transconductance.

[Brief description of drawings]

1A is a sectional view showing a structure of an embodiment of the present invention, and FIG. 1B is an energy band diagram showing a change of a conduction band in the structure shown in FIG. 1A.

FIG. 2A is a sectional view showing a structure of a conventional example,
FIG. 2B is an energy band diagram showing a change in conduction band in the structure shown in FIG.

[Explanation of symbols]

111 InP Substrate 112 Al _0.48 In _0.52 As Layer 113 InP Layer 114 Superlattice 115 InGaAs Operating Layer 116 AlInAs Spacer Layer 117 AlInAs Carrier Supply Layer 118 Non-Doped AlInAs Layer 119 Source Electrode 120 Drain Electrode 121 Gate Electrode 211 InP Substrate 212 InGaAs Super InAs / InAs Lattice 213 InGaAs operating layer 214 n-InAlAs electron supply layer 215 n-InGaAs contact layer 216 Source electrode 217 Gate electrode 218 Drain electrode

Claims (8)

[Claims] 1. In a heterojunction field effect transistor on an InP substrate, an operating layer in which carriers travel and the I
A heterojunction field effect transistor, characterized in that it contains an InP / In _0.52 Al _0.48 As superlattice of at least two periods in a buffer layer existing between the nP substrate and the nP substrate. 2. The total thickness of the buffer layer is 50 nm to 4 nm.
The heterojunction field effect transistor according to claim 1, wherein the range is up to 00 nm. 3. The material forming the operation layer is GaIn
As, InP, GaInAsP, InSb, InGaS
The heterojunction field effect transistor according to claim 1, wherein the heterojunction field effect transistor is one selected from the group consisting of b. 4. The GaAs composition ratio in the operating layer is 0.
The heterojunction field effect transistor according to claim 3, wherein the heterojunction field effect transistor has a range from 1 to 1. 5. A superlattice composed of an In _0.52 Al _0.48 As layer and an InP layer of at least two periods or more, a GaInAs operating layer, an AlInAs spacer layer, on an InP substrate,
A heterojunction field effect transistor characterized in that an AlInAs carrier supply layer and an AlInAs Schottky layer are sequentially grown, and a source electrode, a drain electrode, and a gate electrode are disposed on the AlInAs carrier supply layer. 6. The total thickness of the buffer layer is 50 nm to 4 nm.
The heterojunction field effect transistor according to claim 1, wherein the range is up to 00 nm. 7. The GaAs composition ratio in the operating layer is 0.
7. The heterojunction field effect transistor according to claim 5, wherein the heterojunction field effect transistor has a range from 1 to 1. 8. The heterojunction field effect transistor according to claim 5, wherein the AlAs composition ratio in the carrier supply layer and the Schottky layer is in the range of 0.48 to 1.0.