JPH0821857B2 - Analog-digital conversion method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for converting an analog information signal such as an audio signal into a digital information signal, and more specifically, adding a dither signal to the analog signal. To a digital signal and then removes the dither signal to obtain a digital output.

[Prior Art] Quantization distortion becomes a problem in PCM recording of audio signals. Also, non-linear distortion at the small signal level becomes a problem. In order to solve this kind of problem, dither is added to an analog information signal for A / D conversion, and then dither is subtracted, for example, in Japanese Patent Laid-Open Nos. 61-159825 and 62-13124. It is disclosed.

[Problems to be Solved by the Invention] By the way, as disclosed in the above publication, A / D
If the converter is used in time division and both the analog information signal and dither are converted to digital signals by the same A / D converter, the dither being added and the independent dither have a high degree of identity. Therefore, the dither subtraction (removal) can be achieved with high accuracy. However, the A / D converter has a different conversion error depending on the level of the input signal level.
It is difficult to completely remove the dither component after conversion.

Therefore, an object of the present invention is to provide an analog / digital conversion method capable of highly accurately removing a dither component after A / D conversion.

[Means for Solving the Problem] The present invention for achieving the above object generates a positive polarity analog dither (Da) and a negative polarity analog dither (−Da) having substantially the same absolute value, Positive polarity dither addition analog information signal (Sa + Da) obtained by adding the positive polarity analog dither (Da) to the analog information signal (Sa) and the negative polarity analog dither (-D) to the analog information signal (Sa).
negative dither addition analog information signal (Sa)
-Da) and the positive dither-added analog information signal (Sa + Da) and the negative dither-added analog information signal (Sa-Da) by the same or different analog-digital converters. Signal (Sd + Dd) and negative dither addition digital information signal (Sd-Dd), respectively, and adds the negative dither addition digital information signal (Sd + Dd) to the negative dither addition digital information signal (Sd-Dd) , An analog-digital conversion method for digitally attenuating the digital data (2Sd) obtained by the addition to 1/2.

[Operation] In the present invention, the dither component necessary for removing the dither after A / D conversion is not A / D converted by the dither alone, but the positive dither addition analog information signal (Sa + Da) and the negative dither are used. A / as addition analog information signal (Sa-Da)
D converted. Positive dither addition analog information signal (Sa
+ Da) and negative dither addition analog information signal (Sa-Da)
Since there is not much difference in the signal level between and, there is not much difference in the A / D conversion error. A / D only with dither
When converting, a small amplitude dither causes a large non-linear distortion at the time of A / D conversion.However, when the A / D conversion is performed by adding to the dither analog information signal as in the present invention, the non-linearity at the time of small amplitude input becomes small. The problem of linear distortion is reduced.

[First Embodiment] An apparatus for converting an information analog signal corresponding to an audio signal according to the first embodiment shown in FIG. 1 into a digital signal is, for example, an analog information signal composed of an audio signal of about 0 to 20 kHz. Of the analog adder 3 via the first monkey pull-hold circuit 2.
It is connected to the.

Reference numeral 4 denotes a digital dither generator composed of an M-sequence pseudo-random pulse generating circuit, which has a digital dither (white noise having a substantially constant response in the audio band) at the same period as the sampling period of the first monkey hold circuit 2. Corresponding digital signal).

The polarity selection circuit 5 connected to the dither generator 4 is a circuit that sends positive dither in the first half period of one dither cycle and generates negative dither in the second half. That is, the polarity selecting circuit 5 has a built-in polarity reversing circuit, and outputs the output of the dither generator 4 as it is in the first half of one cycle, and inverts the polarity of the dither in the first half in the latter half and sends it.

The output terminal of the polarity selection circuit 5 is connected to the adder 3 via a digital / analog (D / A) converter 6.

At the output stage of the adder 3, a second sample / hold circuit 7, A / D (analog / digital) converter 8, latch circuit 9, digital adder 10, digital attenuator 11, sampling gate 12, digital output terminal. 13 are connected in order.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIG. It should be noted that each signal should be distinguished by a different symbol for each sampling, but in order to facilitate understanding, the first
The same symbols are used in the figures and FIG.

The analog information signal composed of the audio signal of the input terminal 1 is sampled at the cycle T by the first sample hold circuit 2 as shown in FIG. Figure 2 (A)
During the period from t0 to t4, the analog information signal Sa which is the sample immediately before the time point t0 is input to the analog adder 3.

On the other hand, the dither generator 4 also outputs the digital dither Dd at the cycle T as shown in FIG. Dither Dd
Is the period t0 of the first half of the cycle T as shown in FIG. 2 (C).
From ~ t2, it passes through the polarity selection circuit 5 as it is,
In the second half of the period t2 to t5, the polarity is inverted and the negative polarity digital dither Dd is obtained. The positive polarity digital dither Dd and the negative polarity digital dither-Dd shown in FIG. 2 (C) are converted into a positive polarity analog dither Da and a negative polarity analog dither-Da by the D / A converter 6 and input to the analog adder 3. To do. As a result, from the analog adder 3, the first half of the cycle T
During the period from t0 to t2, the positive dither addition analog information signal (Sa + Da), which is the addition signal of the analog information signal sa and the positive polarity dither Da, is output, and t2 to t4 in the second half t2 to t5 of the cycle T are output. During the period, the negative dither addition analog information signal (Sa-Da) which is the addition signal of the analog information signal Sa and the negative analog dither Da is output.

The output of the adder 3 is sampled and held by the second sample and hold circuit 7 as shown in FIG. That is, the positive dither addition analog information signal (Sa + Da) is sampled from t0 to t1, this hold output is obtained during the period t1 to t2, and the negative dither addition analog information signal (Sa-Da) is obtained from t2 to t3. It is sampled and this hold output is obtained during the period from t3 to t5.

The positive dither-added analog information signal (Sa + Da) and the negative dither-added analog information signal (Sa-Da) are converted by the A / D converter 8 into digital signals having, for example, a two's complement code, respectively, and as shown in FIG. The positive dither addition digital information signal (Sd + Dd) and the negative dither addition digital information signal (Sd-Dd) shown in E) are obtained.

The latch circuit 9 latches and outputs the positive dither addition digital information signal (Sd + Dd) for a period of t1 to t6 as shown in FIG. 2 (F). The time point t6 coincides with the end time point of sampling the positive polarity dither addition analog information signal in the next cycle.

In the digital adder 10, the latched positive dither addition digital information signal (Sd shown in FIG.
+ Dd) and the output of the A / D converter 8 obtained on the line 14 are added. In the period from t1 to t3, it becomes (Sd + Dd) + (Sd + Dd) and dither Dd cannot be removed, but t3 to t6
In the period, (Sd + Dd) + (Sd−Dd) = 2Sd, and an output without dither Dd can be obtained.

The output of the adder 10 is attenuated to 1/2 by the digital attenuator 11 and becomes the input of the sampling gate circuit 12. The sampling gate circuit 12 has t3 to t6 as shown in FIG.
The digital information signal Sd is obtained because it is configured to pass the signal of the period.

Now, the operation for one cycle has been described, but the same operation occurs in the next cycle.

As is clear from the above description, the dither Da required for removing the dither Dd from the dither-added digital information signal (Sd + Dd) after A / D conversion is converted into a digital signal by the common A / D converter 8. Not only that, A / D conversion is performed as a negative dither addition digital information signal (Sa-Da). The difference between the amplitude levels of (Sa + Da) and Da is generally large, but the difference between the amplitude levels of (Sa + Da) and (Sa−Da) is not so large. Therefore, the conversion error in the A / D converter 8 is almost the same. As a result, the absolute value level of the dither Dd included in the digital signal (Sd + Dd) corresponding to (Sa + Da) and the digital signal (Sd) corresponding to (Sa−Da).
The absolute value level of dither Dd included in −Dd) becomes almost equal. Therefore, the dither Dd remains less in the calculation of (Sd + Dd) + (Sd-Dd).

In addition, negative dither addition analog information signal (Sa-Da)
Can be considered as a signal obtained by applying a bias to the dither Da, so that it is less likely to be affected by nonlinear distortion in the minute input of the A / D converter 8.

[Second Embodiment] Next, an A / D converter according to a second embodiment shown in FIG. 3 will be described. However, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The apparatus of FIG. 3 has a second sample-and-hold circuit 7 for the positive dither addition analog information signal (Sa + Da) at the output stage of the analog adder 3.
Besides, negative dither addition analog information signal (Sa-Da)
A third sample and hold circuit 14 for

In the output stage of the third sample and hold circuit 14, the first
A second A / D converter 15 having the same performance as that of the A / D converter 8 is provided. The negative dither addition digital information signal (Sd-Dd) obtained from this is input to the digital adder 10 and added to the positive dither addition digital information signal (Sd + Dd) obtained from the latch circuit 9. As a result, the adder 10 calculates (Sd + Dd) + (Sd-Dd) to obtain an output of 2Sd.

Also in this embodiment, since the positive dither Da and the negative dither Da are both input to the first and second A / D converters 8 and 15 in a state of being biased by the information signal Sa, these conversions are performed. The difference in error is small, and the dither residue is small.

[Modifications] The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.

(1) In FIG. 1, the negative dither addition analog information signal (Sa−Da) is arranged in the first half of one sampling cycle, and the positive dither addition analog information signal (Sa + D) is arranged in the latter half.
a) may be placed. In this case, the latch circuit 9 latches the negative dither addition digital information signal (Sd-Dd).

(2) The sampling gate 12 of FIG. 1 can be moved to the input line 14 of the adder 10.

(3) The sample hold circuits 7 and 14 can be omitted in FIGS. 1 and 3.

[Advantages of the Invention] As described above, according to the present invention, it is possible to highly accurately remove a dither component included in a digital signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an A / D conversion device of a first embodiment of the present invention, FIG. 2 is a diagram showing a state of each part of FIG. 1, and FIG. 3 is an A / D of the second embodiment. It is a block diagram showing a D converter. 1 ... Input terminal, 2 ... First sample and hold circuit, 3 ... Digital adder, 4 ... Dither generator, 5
...... Polarity selection circuit, 6 ... D / A converter, 7 ... Second sample and hold circuit, 8 ... A / D converter, 9 ... Latch circuit, 10 ... Digital adder, 11 ... … Attenuator.

Claims (1)

[Claims] 1. A positive polarity analog dither (Da) and a negative polarity analog dither (-Da) having substantially the same absolute value are generated, and the positive polarity analog dither (Da) is added to an analog information signal (Sa). To form a positive dither addition analog information signal (Sa + Da) and a negative dither addition analog information signal (Sa−Da) in which the negative analog dither (−Da) is added to the analog information signal (Sa). , The positive dither-added analog information signal (Sa + Da) and the negative dither-added analog information signal (Sa-Da) by the same or different analog / digital converters. The dither-added digital information signal (Sd-Dd) is converted into the positive dither-added digital information signal (Sd + Dd), and the negative dither-added digital information signal (Sd + Dd) is added. Information signals (Sd-Dd) are added, and the digital data (2Sd) obtained by the addition is added to 1
An analog-to-digital conversion method characterized by digital attenuation to 1/2.