JPH03151719A - Analog to digital conversion method - Google Patents

Abstract

PURPOSE:To eliminate a dither component included in a digital signal with high accuracy by using a dither component required to eliminate dither after A/D conversion to A/D-convert the dither component as positive and negative dither summing analog information signals. CONSTITUTION:A positive digital dither Dd and a negative digital dither -Dd are inputted to an analog adder 3. Thus, a positive dither summing analog information signal (Sa+Da) of analog information signals Sa, Da is outputted from an analog adder 3 for a 1st half period (t0-t2) of a period T. The signal (Sa+Da) is outputted for a period of (t2-t4) in a later half (t2-t5) of the period T. The signals (Sa+Da) and (Sa-Da) are converted into positive and negative dither adding digital information signals (Sa+Da), (Sa-Da) by an A/D converter 8. The signals are given to a digital adder 10 and the resulting signal is (Sd+ Dd)+(Sd-Dd)=2Sd for a period of (t3-t6) and an output including no dither Dd is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of converting an analog information signal such as an audio signal into a digital information signal, and more specifically,
Analog/Digital (A/D): Adds a dither signal to an analog signal, converts it to a digital signal, and then removes the dither signal to obtain a digital output.
Concerning the conversion method.

[Prior Art] In PCM recording of audio signals, quantization distortion becomes a problem. Additionally, nonlinear distortion at small signal levels becomes a problem. In order to solve this kind of problem, it is possible to add dither to an analog information signal, perform A/D conversion, and then perform dither subtraction, as disclosed in Japanese Patent Application Laid-Open No. 159820/1983.
No. 62-13124.

[Problem to be solved by the invention] By the way, as disclosed in the above-mentioned publication, the A/D
If converters are used in time division and both the dithered analog information signal and the dither are converted into digital signals by the same A/D converter, the dither being added and the independent dither will be highly identical. Therefore, dither subtraction (removal) can be achieved with high precision. However, since the conversion error of the A/D converter varies depending on the input signal level,
It is difficult to completely remove dither components after A/D conversion.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an analog-to-digital conversion method that can remove dither components with high precision after A/D conversion.

[Means for Solving the Problems] To achieve the above object, the present invention generates positive analog dither (Da) and negative analog dither (-Da) having substantially the same absolute value, Positive polarity dither addition analog information signal (Sa+Da) obtained by adding the positive polarity analog dither (Da) to the analog information signal (Sa)
and a negative polarity dither addition analog information signal (Sa-Da) obtained by adding the negative polarity analog dither (-D a >) to the analog information signal (Sa), The positive polarity dither addition analog information signal (Sa+Da) and the negative polarity dither addition analog information signal (Sa-Da) are respectively converted into a positive polarity dither addition digital information signal (Sd+Dd) and a negative polarity dither addition digital information signal (Sd-Dd). Convert and convert the positive polarity dither addition digital information signal (
The present invention relates to an analog-to-digital conversion method in which the negative polarity dither addition digital information signal (Sd-Dd) is added to Sd+Dd) and the digital data (2Sd) obtained by the addition is digitally attenuated to 1/2.

[Operation] In the present invention, the dither component necessary to remove dither after A/D conversion is not converted into A/D by dither alone, but is converted into a positive dither addition analog information signal (Sa+Da).
) and negative polarity dither addition analog information signal (Sa-Da
) is A/D converted. Since there is not much difference in signal level between the positive polarity dither addition analog information signal (Sa+Da) and the negative polarity dither addition analog information signal (Sa-Da), there is not much difference in A/D conversion error.

Furthermore, when A/D conversion is performed using only dither, non-linear distortion during A/D conversion becomes large due to small amplitude dither.
As in the present invention, A/
D conversion also reduces the problem of nonlinear distortion when inputting small amplitudes.

[First Embodiment] A device for converting an information analog signal corresponding to an audio signal into a digital signal according to the first embodiment shown in FIG. It has an input line 1 , which is connected to an analog adder 3 via a first monkey pull and hold circuit 2 .

4 is a digital dither generator consisting of an M-sequence pseudo-random pulse generation circuit, which generates digital dither (white noise having an almost constant response in the audio band) at the same period as the sampling period of the first monkey pull-hold circuit 2. corresponding digital signal).

A polarity selection circuit 5 connected to the dither generator 4 is a circuit that sends out positive polarity dither during the first half of one dither cycle and generates negative polarity dither during the second half. That is, the polarity selection circuit 5 has a built-in polarity inversion circuit, and in the first half of one cycle, output from the dither generator 4 is sent out as is, and in the second half, the polarity of the dither in the first half is inverted and sent out.

The output terminal of the polarity selection circuit 5 is a digital analog (D
/A) Connected to adder 3 via converter 6.

A second sample and hold circuit 7 is provided at the output stage of the adder 3.
, A/D (analog-digital) converter 8, latch circuit 9, digital adder 10, digital attenuator 11
, sampling gate 12, and digital output terminal 13 are connected in this order.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. It should be noted that each signal should be indicated with a different symbol for each sampling, but for ease of understanding, the same symbols are used in FIGS. 1 and 2.

The analog information signal consisting of the audio signal at the input terminal 1 is sampled at a period T by a first sample and hold circuit 2, as shown in FIG. 2(A). During the period from 10 to t4 in FIG. 2(A), the analog information signal Sa, which is the sample immediately before time 10, is input to the analog adder 3.

On the other hand, the dither generator 4 also outputs digital dither Dd with a period T as shown in FIG. 2(B). Dither D
As shown in FIG. 2(C), d passes through the polarity selection circuit 5 as it is during the first half period tO to t2 of the period T, but in the second half period t2 to t5, the polarity is inverted and becomes a negative polarity digital signal. It becomes dither Dd. The positive polarity digital dither Dd and the negative polarity digital dither -Dd shown in FIG.
and is converted into negative polarity analog dither -Da and input to the analog adder 3. As a result, the analog adder 3 outputs a positive dither addition analog information signal (Sa+Da>
is output, and t2 to t4 in the second half of period T, t2 to t5.
During the period, analog information signal Sa and negative polarity analog dither
A negative polarity dither addition analog information signal (Sa-Da), which is an addition signal with Da, is output.

The output of the adder 3 is sampled and held by the second sample and hold circuit 7 as shown in FIG. 2(D). That is, the positive polarity dither addition analog information signal (Sa+Da) is sampled from tO to t1, and from t1 to
This hold output is obtained during the t2 period, and from t2 to t3
negative polarity dither addition analog information signal (Sa-D
a) is sampled, and this hold output is obtained during the period t3 to t5.

The positive polarity dither addition analog information signal (Sa+Da) and the negative polarity dither addition analog information signal (Sa−Da) are A
The /D converter 8 converts them into digital signals of, for example, two's complement codes, and produces a positive dither addition digital information signal (Sd+Dd) and a negative dither addition digital information signal (Sd-) shown in FIG. 2(E). Dd) becomes.

The latch circuit 9 outputs the positive polarity dither addition digital information signal (Sd+Dd) from t1 to t6 as shown in FIG. 2(F).
Latch and output only the period. Note that the 70th point coincides with the end point of sampling of the positive polarity dither addition analog information signal in the next cycle.

In the digital adder 10, the latched positive polarity dither addition digital information signal (S
d+T)d) and the output of the A/D converter 8 available on line 14 are added. During the period t1 to t3, (Sd+Dd) + (Sd+Dd) and dither Dd cannot be removed, but during t3
In the period from 70 to 70, (Sd+Dd)+(Sd-Dd>=2Sd, and an output that does not include dither Dd can be obtained.

The output of the adder 10 is attenuated to 1/2 by a digital attenuator 11 and becomes an input to a sampling gate circuit 12. Since the sampling gate circuit 12 is configured to pass the signal during the period t3 to t6 as shown in FIG. 2(H), the digital information signal Sd is obtained.

Although the operation for one cycle has now been described, a similar operation occurs in the next cycle as well.

As is clear from the above explanation, after A/D conversion, the dither addition digital information signal (Sd+Dd) is converted to the dither Dd.
Not only is the dither Da necessary for removing
/D converted to 0. The difference in amplitude level between (Sa+Da) and Da is generally large, but the difference in amplitude level between (Sa+Da> and (Sa-Da)) is not so large.

Therefore, the conversion errors in the A/D converter 8 are also approximately the same. As a result, the absolute value level of dither Dd included in the digital signal (Sd+Dd) corresponding to (Sa+Da>) and the digital signal (S
d−Dd) is approximately equal to the absolute value level of the dither Dd included in the dither Dd. Therefore, (Sd+Dd)+(S
The remaining amount of dither Dd in the calculation of d-Dd) is reduced.

In addition, a negative polarity dither addition analog information signal (Sa-Da
) can be considered as a signal obtained by adding a bias to the dither Da, so that it is less affected by non-linear distortion in the minute input of the A/D converter 8.

[Second Embodiment] Next, an A/D conversion device according to a second embodiment shown in FIG. 3 will be described. However, parts common to those in FIG. 1 are given the same reference numerals 1 and their explanations will be omitted. The device shown in FIG. 3 includes a second sample-and-hold circuit 7 for the positive dither addition analog information signal (Sa+Da) as well as a negative dither addition analog information signal (Sa+Da) at the output stage of the analog adder 3. -Da) is provided.

The output stage of the third sample-and-hold circuit 14 includes a first
A second A/D converter 15 with the same performance as the A/D converter 8 of
is provided. The negative polarity dither addition digital information signal (Sd-Dd) obtained from this becomes an input to the digital adder 10 and is added to the positive polarity dither addition digital information signal (S d +D d ) obtained from the latch circuit 9. Thereby, the calculation (Sd+Dd)+(Sd-Dd) is performed in the adder lO, and an output of 2Sd is obtained.

Also in this embodiment, both the positive polarity dither Da and the negative polarity dither Da are input to the first and second A/D converters 8.125 while being biased with the information signal Sa. Differences in conversion errors are reduced, and dither residuals are reduced.

[Modifications] The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.

(1) In Figure 1, a negative polarity dither addition analog information signal (Sa-Da) is arranged in the first half of one sampling period, and a positive polarity dither addition analog information signal (S
a+D a ) may be arranged.

In this case, the latch circuit 9 latches the negative polarity dither addition digital information signal (Sd-Dd).

(2) The sampling gate 12 in FIG. 1 is replaced by the adder 10.
input line 14.

(3) The sample and hold circuits 7.14 in FIGS. 1 and 3 can also be omitted.

[Effects of the Invention] As described above, according to the present invention, it is possible to remove dither components included in a digital signal with high precision.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an A/D converter according to a first embodiment of the present invention, FIG. 2 is a diagram showing the state of each part in FIG. 1, and FIG. It is a block diagram showing a D conversion device. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... First sample and hold circuit, 3... Digital adder, 4... Dither generator, 5... Polarity selection circuit, 6... D/A converter, 7
...Second sample and hold circuit, 8...Al1
) converter, 9... latch circuit, 10... digital adder, 11... attenuator.

Claims (1)

[Claims] [1] Generate positive analog dither (Da) and negative analog dither (-Da) having substantially the same absolute value, and add the positive analog dither (-Da) to the analog information signal (Sa). A positive polarity dither addition analog information signal (Sa+Da) obtained by adding dither (Da) and a negative polarity dither addition analog information signal (Sa-Da) obtained by adding the negative polarity analog dither (-Da) to the analog information signal (Sa). the positive polarity dithered addition analog information signal (Sa+Da) and the negative polarity dithered addition analog information signal (Sa-Da) by the same or separate analog-to-digital converters;
) as a positive polarity dither addition digital information signal (Sd+Dd
) and negative polarity dither addition digital information signal (Sd-D
d), and convert the positive polarity dither addition digital information signal (Sd+Dd
) to the negative polarity dither addition digital information signal (Sd-
Dd), and the digital data (2Sd) obtained by the addition
An analog-to-digital conversion method characterized by digitally attenuating to 1/2.