JPH08213631A - Thin film semiconductor device - Google Patents

Abstract

PURPOSE: To provide a form of patterns suitable for preventing the generation of a disconnection of metal wirings, which are formed on a thin film semiconductor device. CONSTITUTION: A thin film semiconductor device is constituted using an insulating substrate 1. A semiconductor thin film 2 is formed on the substrate 1. A thin film transistor 3 is formed by integration using this thin film 2 as an active layer. Metal wirings 7 are formed by patterning on the transistor 3 via a first interlayer insulating film 5. These metal wirings 7 are covered with a protective film 9. The wirings 7 respectively have patterns of a line width, which is periodically changed along their longitudinal directions, and narrow parts 10 and wide parts 11 are alternately arranged on the patterns and are continued As the narrow parts 10 only are never continued singly extending over a long distance, the probability of the disconnection of the wirings 7 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device. More specifically, it relates to a pattern shape of metal wiring formed in a thin film semiconductor device.

[0002]

2. Description of the Related Art A thin film semiconductor device is suitable for a drive substrate of an active matrix type display device and has been actively developed in recent years. A general configuration of a conventional thin film semiconductor device will be briefly described with reference to FIG. The thin film semiconductor device is configured using a transparent insulating substrate 201 such as quartz glass. Although not shown, a semiconductor thin film is formed on the insulating substrate 201. A thin film transistor is formed by using this semiconductor thin film as an active layer. The integrated thin film transistor is covered with a first interlayer insulating film 202 made of PSG or the like. A metal wiring 203 made of aluminum or the like is pattern-formed thereon. The metal wiring 203 is the second interlayer insulating film 20 made of PSG or the like.
4, the pixel electrodes and the like are integratedly formed thereon. The pixel electrode is covered with a protective film 205 made of silicon nitride (P-SiN) or the like formed by plasma chemical vapor deposition. Generally, hydrogen is introduced into a semiconductor thin film made of polysilicon or the like to improve electric characteristics of a thin film transistor. Specifically, annealing is performed to diffuse hydrogen contained in the protective film 205 made of a P-SiN film into polysilicon. Therefore, P-Si
The protective film 205 made of N functions as a hydrogen diffusion source.
In addition, this film has a dense composition and also functions as a cap film that prevents hydrogen once diffused in the polysilicon from being released to the outside.

[0003]

FIG. 12 shows a typical pattern shape of the metal wiring 203 shown in FIG. In general, the metal wiring 203 is linearly patterned. In the laminated structure shown in FIG. 11, the metal wiring 203
Are sandwiched by the interlayer insulating films 202 and 204 from above and below,
In addition, a protective film 205 such as P-SiN is formed on the uppermost part. In this laminated structure, disconnection of metal wiring is a problem. It is considered that the stress inherent in the laminated structure is applied to the metal wiring made of aluminum or the like to cut it. In particular, as shown in FIG. 12, a linear metal wiring having a long wiring length and a narrow wiring width frequently has a disconnection failure. The reason for this is that the PS existing in the upper part
It is largely due to the stress of the iN film. Further, it is known that the stress of the interlayer insulating film made of PSG or the like interposed above and below the metal wiring also promotes the disconnection of the metal wiring as a secondary factor. Therefore, with the conventional layered structure, it is difficult to increase the density of the pattern of the metal wiring made of aluminum or the like, and the long-term reliability of the product is adversely affected.

This point will be further described with reference to FIG. As described above, in the conventional thin film semiconductor device, annealing at 400 ° C. or higher is performed to hydrogenate polysilicon. When the hydrogen contained in the P-SiN film diffuses into the polysilicon, the stress of the protective film inevitably increases. This affects the film existing in the lower layer, and the strain due to the stress reaches the metal wiring. In this state, the metal wiring having a linear line width and a long line length is disadvantageous. And it is difficult for the current technology to absorb the stress by the metal wiring itself. As a result, the film stress causes the migration of aluminum constituting the metal wiring, and appears in the form of disconnection of the wiring 203 as illustrated.

As a measure for preventing disconnection of metal wiring, for example, P
A technique has been proposed in which the SiN film is entirely removed to reduce the film stress. However, with this, PS
Plasma damage is added when the iN film is removed by dry etching, and the characteristics of the thin film transistor change.
Further, if the P-SiN film, which also has a function of suppressing the release of hydrogen introduced into the polysilicon, is completely removed, the polysilicon is not removed during the annealing (damage-free annealing) for removing the damage caused in the previous step. Hydrogen once diffused is released. As a result, the characteristics of the thin film transistor change, causing deterioration of the integrated circuit.

[0006]

SUMMARY OF THE INVENTION In view of the above problems of the prior art, it is an object of the present invention to provide a pattern of metal wiring which is effective for preventing disconnection. The following measures have been taken in order to achieve this object. That is, the thin film semiconductor device according to the present invention has, as a basic configuration, an insulating substrate, a semiconductor thin film formed thereon, a thin film transistor formed by using the semiconductor thin film as an active layer, and an interlayer insulating film. The thin film transistor is provided with a metal wiring patterned on the thin film transistor, and a protective film covering the metal wiring. Characteristically, the metal wiring has a pattern in which the line width changes periodically along the longitudinal direction, and the narrow width portions and the wide width portions are alternately arranged and continuous. Specifically, the line width of the narrow portion is set to 5 μm or less, and the line width of the wide portion is set to 10 μm or more. Further, the line length of the narrow portion is set to 100 μm or less, the line length of the wide portion is set to 100 μm or less, and the total of both line lengths is 1 or less.
It is set to 00 μm or less. In some cases, the metal wiring is electrically connected to a wiring belonging to another layer through a contact hole formed in the wide portion.

The thin film semiconductor device having such a structure is suitable as a driving substrate of an active matrix type display device. That is, the active matrix display device according to the present invention has, as a basic configuration, a drive substrate on which pixel electrodes, thin film transistors, and metal wirings are formed, an opposite substrate including at least an opposite electrode, and a predetermined gap therebetween. And an electro-optic material held between the two bonded substrates. The drive substrate includes a transparent insulating base material, a semiconductor thin film to be an active layer of the thin film transistor, a first interlayer insulating film, the metal wiring, a second interlayer insulating film, the pixel electrode and a protective film. It has a laminated structure in which the layers are stacked in order. Characteristically, the metal wiring has a pattern in which the line width changes periodically along the longitudinal direction, and the narrow width portions and the wide width portions are alternately arranged and continuous.

[0008]

The metal wiring is frequently broken in a linear pattern having a long wiring length and a narrow wiring width. According to the measurement result of the inventor, the metal wiring having a linear pattern having a wiring length of 100 μm or more and a wiring width of 5 μm or less frequently has a break. From this, it is desirable that the metal wiring pattern has a wiring width of 5 μm or more and a wiring length of 100 μm or less. However, there are various restrictions in the actual pattern design, and it is difficult to faithfully follow the above pattern design conditions, especially when the density of the thin film semiconductor device is increased. In view of this, the present invention is characterized in that the line width of the metal wiring is periodically changed along the longitudinal direction to effectively take measures against disconnection without lowering the wiring density. The metal wiring is divided into a narrow portion and a wide portion. The narrow width portion and the wide width portion are alternately arranged and continuous to form a pattern of metal wiring. This prevents only the narrow portion from existing linearly over a long distance. In such a pattern, a wiring density similar to the conventional one can be obtained by skillfully combining the narrow width portion and the wide width portion between the adjacent metal wirings. As a result, it is possible to take measures against disconnection without increasing the area of the metal wiring in the thin film semiconductor device. When the thin film semiconductor device having such a structure is used as a drive substrate of an active matrix display device, the display device is eventually made compact. or,
The number of thin-film semiconductor device chips that can be taken out from one wafer increases, and the manufacturing cost can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a first embodiment of a thin film semiconductor device according to the present invention. (1) is a partial cross-sectional view of the thin film semiconductor device, and (2) is a plan view showing the pattern shape of the metal wiring. As shown in (1), the thin film semiconductor device includes a transparent insulating substrate 1 made of quartz glass or the like, and a semiconductor thin film 2 made of polysilicon or the like formed thereon. The thin film transistor (TFT) 3 is formed by using the semiconductor thin film 2 as an active layer. However, for simplification of the drawing, only one TFT is shown. TFT3
Has a gate electrode 4 formed by patterning on the semiconductor thin film 2 via the gate insulating film 2a. A portion of the semiconductor thin film 2 located on both sides of the gate electrode 4 is heavily doped with n-type impurities to form a source region S and a drain region D. Therefore, the TFT 3 is an N-channel type thin film transistor. Instead of this, P
When forming a channel type thin film transistor, p
Ions may be ion-implanted into the semiconductor thin film 2 at a high concentration. The TFT 3 having such a configuration is covered with the first interlayer insulating film 5 made of PSG or the like. The metal wirings 7a and 7b are patterned on it. The metal wirings 7a and 7b are made of aluminum, for example. Alternatively, an aluminum / silicon alloy containing about 1% silicon may be used. Alternatively, instead of aluminum, a metal material such as molybdenum, titanium, gold, silver, palladium, tantalum, tungsten, nickel, or chromium can be used. Furthermore, a compound (silicide) of these metal elements and silicon can be used as a metal wiring material. The metal wiring 7a is electrically connected to the source region S of the TFT 3 through a contact hole opened in the first interlayer insulating film 5. Similarly, the metal wiring 7b is electrically connected to the drain region D of the TFT 3 through a contact hole opened in the first interlayer insulating film 5. When the thin film semiconductor device is used as a driving substrate of an active matrix display device, the pixel electrode is further patterned by connecting to the metal wiring 7b. These metal wirings 7a and 7b are covered with a second interlayer insulating film 8 also made of PSG or the like. A protective film 9 made of, for example, silicon nitride (P-SiN) formed by plasma-enhanced chemical vapor deposition is formed thereon.
Is deposited. By selectively removing the protective film 9 from the upper portions of the metal wirings 7a and 7b by etching, the breakage of the metal wirings 7a and 7b can be suppressed to some extent.

As shown in FIG. 1B, the metal wiring 7 has a pattern in which the line width changes periodically along the longitudinal direction, and the narrow width portions 10 and the wide width portions 11 are alternately arranged. It is done and is continuous. In such a periodic pattern, the narrow portion 10 does not continue continuously over a long distance by itself, and the probability of occurrence of disconnection can be significantly suppressed as compared with the conventional case. Further, between the metal wirings 7 adjacent to each other, the narrow width portion 10 and the wide width portion 11 are intertwined with each other, and the surface area of the insulating substrate is effectively used to prevent the wiring density from decreasing. That is, in the present invention, although the wide width portion 11 that divides the narrow width portion 10 is provided, the wiring density is not deteriorated.

Preferably, the line width A of the narrow portion 10 is 5 μm.
The line width B of the wide part is set to 10 μm or more. Further, the line length C of the narrow width portion 10 is set to 100 μm or less, the line length D of the wide width portion 11 is set to 100 μm or less, and the total of both line lengths C and D is set to 100 μm or less.

FIG. 2A shows measured data showing the relationship between the wiring width and the wire breakage occurrence rate. According to this graph, when the wiring width is 5 μm or less, the occurrence rate of wire breakage sharply increases. Further, (2) of FIG. 2 is actually measured data showing the relationship between the wiring length and the wire breakage occurrence rate. According to this graph, if the wiring length exceeds 100 μm, the rate of occurrence of disconnection increases. Therefore, to prevent disconnection of metal wiring, the wiring width should be 5 μm.
It is desirable to secure the above and suppress the wiring length to 100 μm or less. However, when the integration of the thin film semiconductor device is advanced, it is always difficult to always satisfy this pattern condition. In some cases, the wiring width must be set to 5 μm or less and the wiring length must be set to 100 μm or more. Therefore, in the present invention, a narrow portion of 5 μm or less and 10 μm
The above wide parts are alternately arranged, and only the narrow part is 1
It is prevented from existing over a length of 00 μm or more. By arranging the narrow width portion and the wide width portion alternately, it becomes unnecessary to limit the total wiring length to within 100 μm.

FIG. 3 is a schematic plan view showing another pattern example of the metal wiring 7. Also in this example, the metal wiring 7 has a pattern in which the line width changes periodically along the longitudinal direction, and the narrow width portions 10 and the wide width portions 11 are alternately arranged and continuous. In this example, a pair of metal wirings 7 are alternately combined to enable high-density wiring. Also in this example, the line width A of the narrow portion 10 is set to 5 μm or less, and the line width B of the wide portion 11 is set to 10 μm or more. The line length C of the narrow width portion 10 is set to 100 μm or less, the line length D of the wide width portion 11 is set to 100 μm or less, and the total of both line lengths C and D is set to 100 μm or less. In practice, the line length C of the narrow width portion 10 may be set relatively large, and the line length D of the wide width portion 11 may be set relatively short. That is, the wide portion 11 is periodically divided so that the narrow portion 10 having a line width of 5 μm or less is not continuous over the line length of 100 μm or more. As described above, in the pattern according to the present invention, the thin portions and the thick portions of the aluminum metal wiring are alternately arranged and continuously repeated. In such a state, by combining a thin portion and a thick portion between adjacent metal wirings, it is possible to secure a wiring density similar to the conventional one. As a result, the chip area of the thin film semiconductor device can be reduced as much as possible,
When used as a drive substrate of an active matrix display device, it leads to downsizing. Further, in the semiconductor manufacturing process, the number of chips that can be taken out from one wafer increases, and the manufacturing cost can be reduced.

FIG. 4 is a schematic plan view showing another example of the metal wiring pattern according to the present invention. Also in this example, the metal wiring 7
Has a pattern shape in which narrow portions 10 and wide portions 11 are alternately arranged. In this example, two narrow portions 10 are divided by one wide portion 11. Also in this example, the narrow portion 1
The line width A of 0 is set to 5 μm or less, and the line width B of the wide portion 11 is set to 10 μm or more. The line length C of the narrow portion 10 is set to 100 μm or less, the line length D of the wide portion 11 is set to 100 μm or less, and the total of both line lengths C and D is set to 100 μm or less.

FIG. 5 is a schematic plan view showing an application example of the present invention. In this example, the metal wiring 7 is electrically connected to the wiring belonging to another layer through the contact hole 12 formed in the wide portion 11. In this example, the wiring belonging to this other layer is the gate wiring 4a. Thus, the pattern according to the present invention is suitable for forming the contact hole 12 in the wide width portion 11 of the metal wiring 7. Normally, a contact hole for electrical connection to the gate wiring (second polysilicon) 4a existing below is generally liable to open larger than the design size depending on the pattern accuracy of photolithography and the taper shape during etching. . Therefore, when the density and integration of the thin film semiconductor device are increased, a contact hole larger than the wiring width must be expected.
Therefore, if the contact can be formed in the wide width portion 11, the restriction can be dealt with. In this example, the size of the contact hole 12 is set to 2 μm × 3 μm. On the other hand, the line width B of the wide portion 11 is set to 10 μm, and the line length D is set to 5 μm. Therefore, the wide width portion 11 has a sufficient area dimension for providing the contact hole 12. The line width A of the narrow portion 10 is 4 μm, and the line length C is 90 μm.

FIG. 6 shows the contact hole 1 shown in FIG.
2 shows a sectional structure of 2. Second on the insulating substrate 1
The gate wiring 4a made of polysilicon is patterned. The gate wiring 4a is covered with a first interlayer insulating film 5 made of PSG or the like. A contact hole 12 is opened in the first interlayer insulating film 5 by etching. A metal wiring 7 made of aluminum or the like is patterned on the first interlayer insulating film 5, and is electrically connected to the gate wiring 4a through the above-mentioned contact hole. The contact hole 12 is just aligned with the wide portion 11 of the metal wiring 7. This metal wiring 7 is also PSG
It is covered with a second interlayer insulating film 8 made of, for example. With such an electrical connection structure, it is possible to design a high-definition pattern without impairing the dimensional accuracy of the contact portion and without causing breakage of the aluminum metal wiring 7. The wiring structure shown in FIG. 6 is suitable when, for example, the gate wiring 4a belonging to a certain thin film transistor is to be electrically connected to the source region or drain region of another thin film transistor. Since the second polysilicon forming the gate wiring 4a and the first polysilicon forming the source region belong to different layers, they cannot be directly electrically connected. Therefore, as shown in FIG. 6, the first polysilicon and the second polysilicon are electrically connected via the metal wiring 7.

FIG. 7 is a schematic plan view showing another contact hole structure. Basically, it is similar to the contact hole structure shown in FIG. 5, and corresponding parts are designated by corresponding reference numerals to facilitate understanding. The feature of this wiring pattern is that the linearity of the metal wiring is maintained as compared with the pattern of FIG. 5, so that the wiring resistance does not fluctuate due to the unevenness of the contact hole 12. That is, the straight line pattern of the metal wiring 7 is basically equivalent to the structure in which the narrow portion 10 is continuous regardless of the existence of the contact hole 12, and the wiring resistance does not change due to the unevenness of the contact hole. In this example, the line width B of the wide width portion 11 is set to 10 μm and the line length D is also set to 10 μm. This is a sufficient area size to include the contact hole 12. On the other hand, the narrow portion 10 has a line width A.
Is set to 5 μm and the line length C is set to 90 μm.

FIG. 8 is a schematic plan view showing another example of the contact structure according to the present invention. In this example, the pixel electrode 13 is electrically connected to the semiconductor thin film 2 made of the first polysilicon via the contact hole 12. A metal wiring 7 made of aluminum or the like is interposed between the pixel electrode 13 made of a transparent conductive thin film such as ITO and the semiconductor thin film 2. The metal wiring 7 has the ladder-shaped pattern shown in FIG. 4, and the window portion 14 is provided in the narrow width portion. In this example, the contact hole 12 is aligned in the window portion 14, and the pixel electrode 13 is electrically connected to the lower semiconductor thin film 2 without coming into contact with the intermediate metal wiring 7.

FIG. 9 schematically shows a sectional structure of the contact hole shown in FIG. A semiconductor thin film 2 made of a first polysilicon is patterned on the insulating substrate 1. The surface is covered with the gate insulating film 2a. Further, its surface is covered with the first interlayer insulating film 5. The metal wiring 7 made of aluminum or the like is patterned on the first interlayer insulating film 5, and the window portion 14 of the metal wiring 7 is located just above the semiconductor thin film 2. The metal wiring 7 is covered with a second interlayer insulating film 8. Contact hole 12 shown in FIG.
Is provided so as to penetrate the second interlayer insulating film 8 and the first interlayer insulating film 5. The contact hole 12 is located just inside the window portion 14 of the metal wiring 7. A pixel electrode 13 made of ITO or the like is patterned on the second interlayer insulating film 8 and electrically connected to the drain region of the semiconductor thin film 2 via the contact hole 12 described above. At this time, the pixel electrode 12 can be prevented from being connected to the metal wiring 7. That is, the contact hole 12 is formed in the window 14 provided in the metal wiring 7 to connect the pixel electrode 13 existing in the upper layer and the semiconductor thin film 2 (first polysilicon) existing in the lower layer. With this configuration, it is not necessary to form a contact hole outside the metal wiring, and therefore, it is useful as a contact structure in multilayer wiring, and contributes to high definition and high density of the thin film semiconductor device. This can reduce the area occupied by the contacts. This contact structure can also be adopted when the pixel electrode 13 is connected to the second polysilicon instead of the first polysilicon, for example.

Finally, with reference to FIG. 10, an example of an active matrix type display device in which the thin film semiconductor device according to the present invention is incorporated as a drive substrate will be described. As shown in the figure, this display device is composed of a drive substrate 101 made of glass or the like, an opposite substrate 102 made of glass or the like, and an electro-optical material made of liquid crystal 103 or the like held between them. A pixel array section 104 and a drive circuit section are integrally formed on the drive substrate 101. The drive circuit section is divided into a vertical drive circuit 105 and a horizontal drive circuit 106. These drive circuits are composed of thin film transistors.
A terminal portion 107 for external connection is formed on the upper end of the peripheral portion of the drive substrate 101. Terminal part 107 is metal wiring 1
08 through the vertical drive circuit 105 and the horizontal drive circuit 10
Connected to 6. The pixel array section 104 includes a gate wiring 109 and a metal wiring 110 that intersect each other. A pixel electrode 111 and a thin film transistor 112 for driving the pixel electrode 111 are integrally formed at the intersection of the two wirings 109 and 110. On the other hand, a counter electrode and a color filter (not shown) are formed on the inner surface of the counter substrate 102.

As described above, the drive substrate 101 is formed by using a transparent insulating base material made of glass or the like, and a semiconductor thin film serving as an active layer of the thin film transistor 112 and a first interlayer insulating film are formed thereon. , Metal wiring 108, 110,
It has a laminated structure in which the second interlayer insulating film, the pixel electrode 111, and the protective film are sequentially stacked. As a characteristic feature, the metal wiring has a pattern in which the line width changes periodically along the longitudinal direction, and the narrow width portion and the wide width portion are alternately arranged and continuous.

[0022]

As described above, according to the present invention, the metal wiring has a pattern in which the line width changes periodically along the longitudinal direction, and the narrow width portion and the wide width portion are arranged alternately. It is done and is continuous. As a result, disconnection of the metal wiring made of aluminum or the like can be prevented, so that the image quality is improved when the thin film semiconductor device is used as a drive substrate of an active matrix type display device. In addition, stable display device production is possible. Furthermore, since the breakage of the metal wiring made of aluminum or the like can be prevented, the reliability of the display device can be secured for a long period of time.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view showing an embodiment of a thin film semiconductor device according to the present invention and a plan view of a pattern of metal wiring.

FIG. 2 is a graph showing a relationship between a wiring width and a wire breakage occurrence rate and a relationship between a wire length and a wire breakage occurrence rate.

FIG. 3 is a schematic plan view showing another example of the metal wiring pattern.

FIG. 4 is a schematic plan view showing another example of a metal wiring pattern.

FIG. 5 is a schematic plan view showing an example of a contact hole structure according to the present invention.

6 is a cross-sectional view of the contact hole structure shown in FIG.

FIG. 7 is a schematic plan view showing another example of the contact hole structure according to the present invention.

FIG. 8 is a schematic plan view showing another example of the contact hole structure according to the present invention.

9 is a cross-sectional view of the contact hole structure shown in FIG.

FIG. 10 is a schematic perspective view showing an example of an active matrix type display device using the thin film semiconductor device according to the present invention as a drive substrate.

FIG. 11 is a schematic perspective view showing an example of a conventional thin film semiconductor device.

FIG. 12 is a schematic plan view showing an example of a metal wiring pattern formed in a conventional thin film semiconductor device.

FIG. 13 is a schematic plan view showing a disconnection process of metal wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Semiconductor thin film 3 Thin film transistor 4 Gate electrode 5 First interlayer insulating film 7 Metal wiring 8 Second interlayer insulating film 9 Protective film 10 Narrow width part 11 Wide width part 12 Contact hole 13 Pixel electrode

Claims (5)

[Claims] 1. An insulating substrate, a semiconductor thin film formed on the insulating substrate, a thin film transistor integrated with the semiconductor thin film as an active layer, and a metal wiring patterned on the thin film transistor via an interlayer insulating film. A thin film semiconductor device including a protective film covering the metal wiring, wherein the metal wiring has a pattern in which a line width changes periodically along a longitudinal direction thereof, and a narrow width portion and a wide width portion are provided. A thin film semiconductor device characterized by being alternately arranged and continuous. 2. The thin film semiconductor device according to claim 1, wherein the line width of the narrow portion is set to 5 μm or less and the line width of the wide portion is set to 10 μm or more. 3. The line length of the narrow portion is set to 100 μm or less, the line length of the wide portion is set to 100 μm or less, and the total of both line lengths is set to 100 μm or less. The thin film semiconductor device according to claim 1. 4. The thin film semiconductor device according to claim 1, wherein the metal wiring is electrically connected to a wiring belonging to another layer through a contact hole formed in the wide portion. 5. An electro-optical material held between a driving substrate on which a pixel electrode, a thin film transistor and a metal wiring are formed, a counter substrate having at least a counter electrode, and both substrates bonded to each other with a predetermined gap. An active matrix display device comprising: a drive substrate, a transparent insulating film base material, a semiconductor thin film to be an active layer of the thin film transistor, a first interlayer insulating film,
The metal wiring has a laminated structure in which a second interlayer insulating film, the pixel electrode, and a protective film are sequentially stacked, and the metal wiring has a pattern in which a line width changes periodically along a longitudinal direction thereof. An active matrix type display device having a narrow width portion and a wide width portion which are alternately arranged and continuous.