JPH08204036A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE: To obtain a nonvolatile semiconductor memory device in which readout currents of a plurality of memory cells are made uniform, which reduces the distribution of threshold values of the memory cells and whose power-supply voltage is made low by a method wherein the plurality of memory cells constituting a NAND cell are formed in such a way that the capacity ratio of the memory cells becomes larger in the close order from contacts connected to a bit line. CONSTITUTION: The protruding width W of a memory cell M1 on the side close to a bit line BL is made larger than the protruding width of a memory cell M2, the protruding width of the memory cell M2 is made larger than the protruding width of a memory cell M3, and, in the same manner, a memory cell M8 has a smallest protruding width. As a result, the capatity ratio of the memory cells on the side of the bit line BL becomes higher than the capacity ratio of the memory cells on the side of a source line SL, and the readout currents of the memory cells on the side of the bit line BL can be made large. As a result, a reduction in an ON current due to a rise in the source voltage of the memory cell M1 by channel resistances of the seven memory cells M2 to M8 on the side of the source line SL with reference to the memory cell M1 can be offset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an electrically batch erase type semiconductor nonvolatile memory device.

[0002]

2. Description of the Related Art EEPROM (Electrically erasable /
Programmable read only memory (electrically erasable / rewritable read-only memory), which is a NAND cell type EEPROM capable of high integration as described in, for example, JP-A-1-173654. It has been known.

FIG. 4 shows a plan view of a conventional NAND type memory cell.

Referring to FIG. 4, a NAND type memory cell is a unit of a plurality of (for example, eight) memory cells M1 to M8 connected in series such that their sources and drains are shared by adjacent ones. And is connected to the bit line BL. The memory cell has a stack gate structure in which a floating gate and a control gate are stacked, and the memory cell array is formed in a P type N well formed in a P type substrate or an N type substrate.

Further, as shown in FIG. 4, the plurality of memory cells M1 to M8 have the same shape (the channel width, the channel length, the protruding width of the floating gate onto the field oxide film, and the like have the same dimensions). ing.

The drain side of the NAND type memory cell is connected to the bit line BL via the selection gate SG1, and the source side is connected to the source line (SL) which becomes the reference potential via the selection gate SG2.

The control gates of the plurality of memory cells M1 to M8 are continuously arranged in the row direction and arranged in word lines CG1 to CG.
It becomes 8.

Such NAND cells are arranged in a matrix to form a memory cell array.

Next, the read operation of the NAND type memory cell shown in FIG. 4 will be described with reference to Table 1.

For example, assume that the data in the memory cell M3 in the NAND memory cell shown in FIG. 3 is read.
In this case, the gate voltages SG1 and SG2 of the two selection transistors S1 and S2 are both set to 5V to turn on the selection transistors S1 and S2, and the control gates CG1, CG2, CG4, CG5, CG6 and CG of the non-selected memory cells.
7, CG8 is applied with an "H" level (for example, 5V) which is a voltage at which the memory cell is turned on even in the written state, and an "L" level (for example, 0V) is applied to the control gate CG3 of the selected memory cell M3. .

Then, the bit line BL connected to the selected memory cell M3 is set to "H" level (1 to 5V), and the other bit lines not connected to the selected memory cell M3 are set to 0V.

If electrons are stored in the floating gate of the selected memory cell M3, the threshold V _TH of the selected memory cell is high (for example, 3 V). If no electrons are stored, the threshold V _TH is negative. It is a voltage (0 V or less).

At the time of data reading, it is determined whether or not a current flows through the selected bit line BL depending on the state of the selected memory cell, so that the data value "0" or "1" of the memory cell M3 can be determined. It

[0014]

In the above-mentioned conventional NAND type EEPROM, if the memory cells M1 to M3 of eight stages connected in series have the same shape, the voltage applied to the control gate and the floating The capacity ratio, which is the ratio of the voltage applied to the gate, is common to a plurality of memory cells that form a NAND memory cell.

In such a NAND type memory cell, the read current becomes different depending on the distance from the bit line BL of the selected memory cell at the time of reading data.

That is, when the memory cell M1 in the first stage (bit line BL side) is selected and in the eighth stage (source line SL side).
The resistance value added to the source is different from that when the memory cell M8 of the first stage is selected.
A value of 1 results in a smaller read current.

This difference in read current causes the read current of the NAND type cell to fluctuate, and the distribution of the threshold voltage V _TH of each memory cell (thus, the characteristics of the memory cell) when viewed as the entire chip. It will widen the width. If the characteristics of the memory cell in the entire chip vary, it becomes difficult to reduce the power supply voltage.

The present invention has been made in view of the above problems, and the threshold voltage of a memory cell is set by aligning the read currents of a plurality of memory cells connected in series, which is one unit of a NAND type EEPROM. It is an object of the present invention to provide a semiconductor non-volatile memory device having a narrow distribution (reducing variations) and enabling a low power supply voltage.

[0019]

In order to achieve the above object, the present invention has a structure in which a floating gate and a control gate are stacked on a semiconductor substrate, and electrical rewriting is enabled by increasing or decreasing the charge in the floating gate. In a semiconductor non-volatile memory device having a memory cell array in which a plurality of memory cells are connected in series to form a NAND cell and arranged in a matrix, the plurality of memory cells forming the NAND cell are connected to a bit line. There is provided a semiconductor nonvolatile memory device, wherein the memory cells are formed such that the capacity ratio of the memory cells increases in the order of increasing distance from the contact.

In the present invention, the plurality of memory cells forming the NAND type cell may be formed such that the gate width becomes larger in an order closer to the contact connected to the bit line.

[0021]

According to the present invention, in a plurality of memory cells connected in series in a plurality of stages, which is one unit of a memory cell of a NAND type EEPROM, the gate width of the memory cells is changed from a large value to a small value in the order closer to the contact. Alternatively, by increasing the width of the floating gate over the field to increase the capacitance ratio, the on-current of the memory cell on the bit line side is increased and is equal to the read current of the memory cell closest to the source line. By designing the other seven memory cells so as to satisfy the above condition, it is possible to reduce the variation of the read current, reduce the distribution width of the threshold voltage of the entire chip, and reduce the current voltage.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

[0023]

First Embodiment A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a NAND according to the first embodiment of the present invention.
FIG. 2 is a plan view of the type cell, and FIG. 2 is a diagram showing an equivalent circuit of the NAND type cell of the EEPROM of the first embodiment of the present invention.

The NAND type memory cell according to this embodiment is
A plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and are connected to a bit line BL. The memory cell has a stack gate structure in which a floating gate and a control gate are stacked, and the memory cell array is formed in a P-type N well formed in a P-type substrate or an N-type substrate.

The drain side of the NAND cell has a select gate S
The source side is connected to the bit line BL via G1, and the source side is connected to the source line SL serving as a reference potential via the select gate SG2. The control gates of the memory cells M1 to M8 are continuously arranged in the row direction to form the word lines CG1 to CG8.

In the present embodiment, in the memory cell M1 of FIG. 1, the protrusion width indicated by w (that is, the protrusion width of the floating gate on the field oxide film) is closer to the side connected to the bit line BL. It changes from large to small one by one. That is, the memory cell M on the side closer to the bit line BL
The protrusion width of 1 is larger than that of the memory cell M2, and the protrusion width of the memory cell M2 is equal to that of the memory cell M3.
Memory cell M8 has a minimum protrusion width.

As a result, the capacity ratio of the memory cells on the bit line BL side becomes higher than the capacity ratio of the memory cells on the source side, and the read current of the memory cells on the bit line BL side can be increased. That is, when the capacity ratio of the memory cell is increased, the potential of the floating gate is increased when a predetermined potential is applied to the control gate during reading, and the gate voltage applied to the channel portion is increased. The on-current of 1 increases and the read current increases.

This increase in read current is caused by the memory cell M.
Therefore, the decrease in the on-current due to the increase in the source potential of the memory cell M1 due to the channel resistance of the seven memory cells M2 to M8 on the source line SL side with respect to 1 is offset.

At this time, the other 7 is set so as to have a read current equivalent to that of the memory cell M8 closest to the source line SL side.
By designing the value of w of one memory cell, it is possible to suppress the occurrence of variations in the read current in the NAND type cell.

[0030]

Second Embodiment A second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a plan view of a NAND cell according to the second embodiment of the present invention.

With reference to FIG. 3, the arrangement of the NAND type memory cells and the like are the same as those described in the first embodiment, and therefore description thereof is omitted. In the following, this embodiment and the first embodiment will be described. Only the differences from the example will be described.

In this embodiment, as shown in FIG. 3, the size of the channel width W of the memory cell is changed from the one closer to the side connected to the bit line BL to the larger one in order.
As a result, the read current of the memory cell on the bit line BL side can be increased.

This increase in the read current is caused by the channel resistance of the seven memory cells M2 to M8 on the source line SL side with respect to the memory cell M1 as described in the first embodiment. This offsets the decrease in on-current due to the increase in potential. At this time, the most source line S
By designing the values of the channel widths W of the other seven memory cells to be equal to the ON current of the memory cell M8 near the L side, it is possible to suppress the occurrence of variations in the read current in the NAND type cell.

[0034]

[Table 1]

[0035]

As described above, according to the present invention, N
In a memory cell in which a plurality of stages are connected in series, which is one unit of the memory cell of the AND-type EEPROM, read-out is performed by appropriately changing the protruding width of the floating gate on the field in consideration of the channel resistance of the memory cell. This is for controlling the variation of the current, and reduces the variation of the read current in the memory cells connected in series in multiple stages, which is one unit of the NAND type EEPROM, and as a result, the threshold distribution width of the entire chip can be reduced. It is possible to reduce the current and voltage by reducing the size.

According to the present invention, a NAND type EEPROM
In a plurality of memory cells connected in series, which is one unit of the memory cells of the above, the read current is controlled by changing the gate width, and the variation of the read current in the memory cells is reduced. As a result, the threshold of the entire chip is reduced. The width of the distribution of values is made small, and it is possible to achieve a lower current voltage.

[Brief description of drawings]

FIG. 1 is a plan view showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of an embodiment of the present invention.

FIG. 3 is a plan view showing the configuration of another embodiment of the present invention.

FIG. 4 is a plan view showing a configuration of a conventional example.

[Explanation of symbols]

 BL bit line SL source line M1 to M8 memory cells SG1 and SG2 selection gates CG1 to CG8 control gate (word line)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (2)

[Claims] 1. A NAND-type cell is formed by stacking a floating gate and a control gate on a semiconductor substrate, and serially connecting a plurality of electrically rewritable memory cells by increasing / decreasing an electric charge in the floating gate. In a semiconductor nonvolatile memory device having a memory cell array arranged in a matrix, the capacity ratio of the memory cells increases in the order in which the plurality of memory cells forming the NAND cell are closer to a contact connected to a bit line. A semiconductor nonvolatile memory device, which is formed as described above. 2. A NAND type cell is formed by stacking a floating gate and a control gate on a semiconductor substrate, and serially connecting a plurality of electrically rewritable memory cells by increasing / decreasing an electric charge in the floating gate. In the semiconductor non-volatile memory device having a memory cell array arranged in a matrix, the plurality of memory cells forming the NAND type cell are formed such that the gate width increases from the contact connected to the bit line in ascending order. A semiconductor nonvolatile memory device characterized by the above.