JPH0817853A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0817853A JPH0817853A JP6144292A JP14429294A JPH0817853A JP H0817853 A JPH0817853 A JP H0817853A JP 6144292 A JP6144292 A JP 6144292A JP 14429294 A JP14429294 A JP 14429294A JP H0817853 A JPH0817853 A JP H0817853A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit board
- resin
- main surface
- metal cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及びその製造
方法に関し、特にベアチップ実装構造及びその製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a bare chip mounting structure and its manufacturing method.
【０００２】[0002]
【従来の技術】従来のベアチップ実装構造を示す特開平
４−９１４４３号公報を示す図６を参照すると、セラミ
ックやエポキシ樹脂などからなる絶縁性の回路基板２の
主表上に形成された配線３０上に、バンプ３を介して、
半導体チップ特にＩＣチップ１がフリップチップ方式で
接続され、ＩＣチップ１を機械的及び化学的に保護する
ために、このＩＣチップ１の他に、バンプ３や回路基板
２の所要部分を、樹脂２２で封止した技術を示す第１の
従来例がある。2. Description of the Related Art Referring to FIG. 6 showing Japanese Patent Laid-Open No. 4-91443 showing a conventional bare chip mounting structure, a wiring 30 formed on a main surface of an insulating circuit board 2 made of ceramic or epoxy resin. On top, via bump 3,
A semiconductor chip, in particular, an IC chip 1 is connected by a flip chip method, and in order to protect the IC chip 1 mechanically and chemically, in addition to the IC chip 1, required portions of the bump 3 and the circuit board 2 are provided with a resin 22. There is a first conventional example showing a technique of sealing with.
【０００３】また、ワイヤボンディングを用いて、回路
基板にＩＣチップを実装した特公平３−１７２２０号公
報を示す図７を参照すると、凹部を形成した合成樹脂な
どにより製造された回路基板２の凹部にＩＣチップ１を
搭載し、ワイヤボンディングによって回路基板２の電極
とＩＣチップ１とを電気的に接続した後に樹脂枠２５を
所定位置に置いて、封止用樹脂２２をポッティングなど
の手法により供給する。ポッティング樹脂が未硬化の状
態にて、その上に金属キャップ７を搭載し、恒温槽中で
所定温度にて所定時間まで加熱する事により硬化させる
技術を示す第２の従来例がある。Further, referring to FIG. 7 showing Japanese Patent Publication No. 3-17220, in which an IC chip is mounted on a circuit board by using wire bonding, a concave portion of a circuit board 2 made of synthetic resin or the like having a concave portion is formed. After mounting the IC chip 1 on the substrate, electrically connecting the electrodes of the circuit board 2 and the IC chip 1 by wire bonding, the resin frame 25 is placed at a predetermined position, and the sealing resin 22 is supplied by a technique such as potting. To do. There is a second conventional example showing a technique in which the potting resin is uncured and the metal cap 7 is mounted on the potting resin and the potting resin is cured by heating at a predetermined temperature for a predetermined time in a constant temperature bath.
【０００４】また、フリップチップ方式で実装した場合
の封止方法を示す特開昭５８−１０３１４３号公報を示
す図８（ａ）乃至（ｄ）を参照すると、まず（ａ）に示
す樹脂通過穴２１を設けた回路基板２に、バンプ３を介
してＩＣチップ１をフリップチップ接続する。次いで、
封止樹脂２２をＩＣチップ１上から供給すると、回路基
板２との間にも順次流れこみ、充填されるようになり
（ｂ）、ここで更に、（ｃ）に示すように、樹脂ディス
ク２３を上方より押圧すると、ＩＣチップ１と回路基板
２との間隙に流れ込んだ封止樹脂２２は、回路基板２に
形成された樹脂通過穴２１より流出する。この時、間隙
の中に存在していた気泡も樹脂通過穴２１より排出され
る。封止樹脂２２を硬化させる前に、多孔質板材２４で
樹脂通過穴２１を塞げば多孔質板材２４に余分な封止樹
脂２２は吸収され、安定した樹脂封止状態が得られる
（ｄ）という技術の第３の従来例がある。Further, referring to FIGS. 8 (a) to 8 (d) showing Japanese Patent Laid-Open No. 58-103143, which shows a sealing method in the case of mounting by a flip chip method, first, a resin passage hole shown in (a) is shown. The IC chip 1 is flip-chip connected to the circuit board 2 provided with 21 via the bumps 3. Then
When the encapsulating resin 22 is supplied from above the IC chip 1, the encapsulating resin 22 also sequentially flows into and is filled with the circuit board 2 (b). Here, as shown in (c), the resin disk 23 is further filled. When is pressed from above, the sealing resin 22 that has flowed into the gap between the IC chip 1 and the circuit board 2 flows out from the resin passage hole 21 formed in the circuit board 2. At this time, the bubbles existing in the gap are also discharged from the resin passage hole 21. If the porous plate member 24 closes the resin passage hole 21 before the sealing resin 22 is cured, the porous plate member 24 absorbs the excess sealing resin 22 and a stable resin sealing state is obtained (d). There is a third conventional example of the technology.
【０００５】[0005]
【発明が解決しようとする課題】上記第１の従来例で
は、樹脂２２が金属キャップに比べて柔らかく、強度が
不充分であるかる、ＩＣに対する機械的保護が不足して
おり、また樹脂２２は金属と比べて熱伝導性が劣るた
め、放熱性が悪いという欠点がある。また、製造プロセ
ス上の問題点として、ポッティングによる封止方法では
粘度が高いと封止樹脂２２が回路基板２とＩＣチップ１
との間隙に流し込むことが困難であり、逆に粘度が低い
と樹脂２２が回路基板２の表面を伝わってＩＣチップ１
の周囲の広い部分に流れ出すという欠点がある。In the first conventional example described above, the resin 22 is softer than the metal cap and has insufficient strength, or lacks mechanical protection for the IC. Since the thermal conductivity is inferior to that of metal, there is a drawback that the heat dissipation is poor. Further, as a problem in the manufacturing process, when the viscosity is high in the sealing method by potting, the sealing resin 22 causes the circuit board 2 and the IC chip 1 to have a high viscosity.
It is difficult to pour into the gap between the IC chip 1 and the IC chip 1 and the resin 22 propagates on the surface of the circuit board 2 if the viscosity is low.
It has the drawback of flowing into a wide area around the.
【０００６】また上記第２の従来例では、フリップチッ
プ構造となっており、基板２とはボンディングワイヤを
介してチップ１と接続されているため、基板を通しての
放熱には限界がある。放熱は金属キャップ７を通してお
こなうことも大切であり、このためにはＩＣチップ１と
金属キャップ７との隙間を小さな値で再現性よくコント
ロールする必要があるが、この構造では無理である。ま
た、樹脂の流し込みのために樹脂枠２５を用いており、
構造上複雑で高価になると共に、実装面積も大きくなる
という欠点がある。The second conventional example has a flip-chip structure and is connected to the chip 1 through the bonding wires with the substrate 2, so that there is a limit to heat dissipation through the substrate. It is also important to radiate heat through the metal cap 7. For this purpose, it is necessary to control the gap between the IC chip 1 and the metal cap 7 with a small value with good reproducibility, but this structure is impossible. Further, the resin frame 25 is used for pouring the resin,
It is disadvantageous in that it is structurally complicated and expensive, and the mounting area is large.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置の構
成は、回路基板の主表面に形成された電極に、バンプを
介して、半導体チップの一主表面上の電極部分が固着さ
れ、少なくとも前記チップ，前記バンプ及び前記電極を
覆うように金属キャップを設け、前記キャップと前記回
路基板とで覆われた内部を樹脂で封止し、前記金属キャ
ップの内面に、前記チップの他の主表面と接触する突起
が形成されていることを特徴とする。According to the structure of a semiconductor device of the present invention, at least an electrode portion on one main surface of a semiconductor chip is fixed to an electrode formed on a main surface of a circuit board via bumps. A metal cap is provided so as to cover the chip, the bump, and the electrode, the inside covered with the cap and the circuit board is sealed with resin, and the other main surface of the chip is provided on the inner surface of the metal cap. It is characterized in that a protrusion is formed in contact with.
【０００８】本発明の第１の半導体装置の製造方法の構
成は、回路基板の主表面上の電極に、バンプを介して、
半導体チップの一主表面の電極部分を固着する工程と、
少なくとも前記電極、前記バンプ，及び前記チップを覆
うための液状の封止樹脂を、内面に突起を形成した金属
キャップ内に入れる工程と、前記チップが前記封止樹脂
と対向するように前記回路基板を反転する工程と、前記
回路基板と前記金属キャップとを互いに接近させ、前記
チップの他主表面が前記突起と接触した状態で前記封止
樹脂を硬化させる工程とを含むことを特徴とする。According to a first method of manufacturing a semiconductor device of the present invention, an electrode on a main surface of a circuit board is provided with bumps,
A step of fixing the electrode portion on the one main surface of the semiconductor chip,
A step of putting a liquid sealing resin for covering at least the electrodes, the bumps, and the chip into a metal cap having a protrusion formed on an inner surface thereof, and the circuit board so that the chip faces the sealing resin. And a step of bringing the circuit board and the metal cap close to each other and curing the sealing resin in a state where the other main surface of the chip is in contact with the protrusion.
【０００９】本発明の第２の半導体装置の製造方法の構
成は、回路基板の主表面の電極に、バンプを介して、半
導体チップの一主表面の電極部分を固着する工程と、内
面に突起が形成され、かつ貫通孔が形成された金属キャ
ップを、前記チップを覆うように位置させる工程と、前
記貫通穴から封止樹脂を注入して内空を埋め尽す工程
と、前記チップの他主表面と前記突起とを接触させた状
態で前記封止樹脂を硬化させる工程とを含むことを特徴
とする。According to a second method of manufacturing a semiconductor device of the present invention, a step of fixing an electrode portion on one main surface of a semiconductor chip to an electrode on the main surface of a circuit board via a bump and a protrusion on an inner surface. And a through hole is formed so as to cover the chip, a step of injecting a sealing resin from the through hole to fill the inner space, and another main part of the chip. And a step of curing the sealing resin in a state where the surface and the protrusion are in contact with each other.
【００１０】本発明の第３の半導体装置の構成は、貫通
孔が形成された回路基板の主表面の電極に、バンプを介
して、半導体チップの一主表面の電極部分を固着する工
程と、内面に突起が形成された金属キャップを前記チッ
プを覆うように位置させる工程と、前記貫通穴から封止
樹脂を注入して内空を埋め尽す工程と、前記チップの他
主表面と前記突起とを接触させた状態で前記封止樹脂を
硬化させる工程とを含むことを特徴とする。According to a third structure of the semiconductor device of the present invention, a step of fixing an electrode portion on one main surface of a semiconductor chip to an electrode on the main surface of a circuit board in which a through hole is formed via a bump, Positioning a metal cap having a protrusion formed on the inner surface so as to cover the chip, a step of injecting a sealing resin from the through hole to fill the inner space, the other main surface of the chip and the protrusion And a step of curing the sealing resin in a state of being in contact with.
【００１１】[0011]
【実施例】図１は本発明の第１の実施例のベアチップ実
装構造の半導体装置を示す断面図である。1 is a sectional view showing a semiconductor device having a bare chip mounting structure according to a first embodiment of the present invention.
【００１２】図１において、本実施例は、合成樹脂やセ
ラミック等からなる絶縁性の回路基板２の主表面に、電
極４とこの電極４に連続した所定のパターンの配線（図
示していない）とが形成され、この電極４とＩＣチップ
１の主表面上のバンプ３とがフリップチップ方式で接続
され、ＩＣチップ１の反対の主表面は３個の突起７（内
１個は図示せず）に接しており、この突起７の高さＨは
いずれも２０μｍ乃至２００μｍが最も好ましく、２０
μｍ乃至５００μｍであっても好ましい。この突起７
は、方形の金属キャップ６の内面にエンボス加工や圧縮
変形加工等により一体に形成されている。封止樹脂５
は、機械的及び化学的に保護するため、金属キャップ６
内を隙間なく埋め尽される。さらに、金属キャップ６の
端部と回路基板２の主表面とが対向する隙間にもこの封
止樹脂５で埋められる。即ち、金属キャップ６とＩＣチ
ップ１の一主表面との隙間や、ＩＣチップ１の他主表面
と回路基板２の主表面との隙間等にも、封止樹脂５が埋
められている。ここで、突起７がＩＣチップ１の一主表
面に当接した状態で、金属キャップ６の端部と回路基板
２の主表面とが当接しないように、例えば３００乃至１
２００μｍ程度の隙間があることが好ましい。In FIG. 1, in the present embodiment, an electrode 4 and a wiring of a predetermined pattern continuous to the electrode 4 (not shown) are formed on the main surface of an insulating circuit board 2 made of synthetic resin or ceramics. Are formed, and the electrodes 4 and the bumps 3 on the main surface of the IC chip 1 are connected by a flip chip method, and the opposite main surface of the IC chip 1 has three protrusions 7 (one of which is not shown). ), The height H of the protrusions 7 is most preferably 20 μm to 200 μm.
It is also preferable that the thickness is from μm to 500 μm. This protrusion 7
Are integrally formed on the inner surface of the rectangular metal cap 6 by embossing or compression deformation. Sealing resin 5
Is a metal cap 6 for mechanical and chemical protection.
The inside is completely filled. Further, the sealing resin 5 is also filled in the gap where the end of the metal cap 6 and the main surface of the circuit board 2 face each other. That is, the sealing resin 5 is also filled in a gap between the metal cap 6 and one main surface of the IC chip 1, a gap between the other main surface of the IC chip 1 and the main surface of the circuit board 2, and the like. Here, in a state where the protrusion 7 is in contact with one main surface of the IC chip 1, the end portion of the metal cap 6 and the main surface of the circuit board 2 are not in contact with each other, for example, 300 to 1
It is preferable that there is a gap of about 200 μm.
【００１３】封止樹脂５により、ＩＣチップ１，バンプ
３，電極４，及び回路基板２の主表面の一部の表面がす
べて被覆されるため、雰囲気中の湿気や化学物質などに
より、影響を受けることがなく、また外部からの衝撃を
弾力的に受けめて、ＩＣチップ１とこのチップ１の接続
部分とを破壊から守っている。これは、上記封止樹脂５
だけでなく、突起７や金属キャップ６の端部と回路基板
２の主表面との間の隙間に存在する封止樹脂等の構造上
からも、いえることである。また、金属キャップ６の内
面とＩＣチップ１の一主表面とが全面で接触しないよう
に突起７が形成され、しかもこの隙間が封止樹脂５で充
填されているため、ＩＣチップ１の発熱や雰囲気温度の
変動などにともなう熱膨張係数差に起因するストレスを
弾力的に受けとめており、この部分のはがれや破損など
を防ぐことができる。Since the IC chip 1, the bumps 3, the electrodes 4, and a part of the main surface of the circuit board 2 are entirely covered with the sealing resin 5, the influence of moisture and chemical substances in the atmosphere may have an effect. The IC chip 1 and the connecting portion of the chip 1 are protected from being destroyed by receiving no impact and elastically receiving an external impact. This is the above-mentioned sealing resin 5
This is not limited to the structure of the sealing resin or the like existing in the gap between the protrusion 7 or the end of the metal cap 6 and the main surface of the circuit board 2. Further, since the projection 7 is formed so that the inner surface of the metal cap 6 and the one main surface of the IC chip 1 do not come into contact with the entire surface, and the gap is filled with the sealing resin 5, heat generation of the IC chip 1 and The stress due to the difference in thermal expansion coefficient due to the fluctuation of the ambient temperature is elastically received, and peeling or damage of this portion can be prevented.
【００１４】金属キャップ６は凹型形状をしており、Ｉ
Ｃチップ１を覆うような形でかぶさっている。キャップ
６の側面と回路基板２の一主面との間に僅かの隙間があ
りこの隙間にも樹脂５が充填されている。金属キャップ
６は、アルミニウムもしくはアルミニウム合金を用いて
いるが、もちろん銅、銅合金、鉄、鉄合金などの他の金
属でもかまわない。軽く、丈夫で放熱性に優れているも
のが望ましい。本構造では、キャップ６の支持はＩＣチ
ップ１に一部が接触しているものの、大部分は封止樹脂
５で覆われていることに注意されたい。本実施例では、
３点の突起で接触しているが、この突起の数は１〜１０
程度であってもかまわない。本構造では、キャップ６か
らの応力がＩＣチップ１や基板２の一部に集中すること
なく、樹脂５の全体で支えている。従って、封止樹脂５
との接着力向上は重要である。このため、キャップの６
表面を、封止樹脂５との接着力を上げるために金属酸化
被膜等で覆うことも可能である。封止樹脂５の材料とし
ては、エポキシ系樹脂を用いており、例えばハイソール
社製ＦＰ４５１０、北陸塗料社製チップコート８４０
１、住友ベークライト社製ＣＲ−４０００Ｘ１、サンス
ター技研社製Ｅ−６１０２Ｅ１５、Ｅ−６１０２Ｆ１、
松下電工社製ＣＶ５１８３Ｓ、九州松下社製ＣＣＮ８１
０Ｄ、日本レック社製ＮＦ−５００Ｚ１、ＮＦ−５００
Ｚ２、信越化学社製セミコート１１５等を用いている。
もちろん必要に応じてシリコーン系や他の樹脂を用いる
ことも可能である。特に熱伝導性の優れたフィラー入り
の樹脂を用いることにより、放熱性を良くする事が出来
る。The metal cap 6 has a concave shape.
The C chip 1 is covered so as to cover it. There is a slight gap between the side surface of the cap 6 and one main surface of the circuit board 2, and this gap is also filled with the resin 5. The metal cap 6 is made of aluminum or aluminum alloy, but may be made of other metals such as copper, copper alloy, iron and iron alloy. Lightweight, durable, and excellent in heat dissipation are desirable. It should be noted that in this structure, although the support of the cap 6 is partially in contact with the IC chip 1, most of it is covered with the sealing resin 5. In this embodiment,
It is in contact with 3 points of protrusions, but the number of these protrusions is 1-10.
It may be a degree. In this structure, the stress from the cap 6 is supported by the entire resin 5 without being concentrated on a part of the IC chip 1 or the substrate 2. Therefore, the sealing resin 5
It is important to improve the adhesive strength with. Therefore, the cap 6
It is also possible to cover the surface with a metal oxide film or the like in order to increase the adhesive force with the sealing resin 5. An epoxy resin is used as the material of the sealing resin 5, and for example, FP4510 manufactured by Hisol Co., Ltd. and chip coat 840 manufactured by Hokuriku Paint Co.
1, CR-4000X1 manufactured by Sumitomo Bakelite Co., E-6102E15, E-6102F1, manufactured by Sunstar Giken Co., Ltd.
Matsushita Electric Works CV5183S, Kyushu Matsushita CCN81
0D, NF-500Z1, NF-500 manufactured by Nippon Lec Co., Ltd.
Z2, Shin-Etsu Chemical Co., Ltd. semi coat 115 and the like are used.
Of course, it is possible to use a silicone-based resin or another resin, if necessary. In particular, heat dissipation can be improved by using a resin containing a filler having excellent thermal conductivity.
【００１５】尚、回路基板２の主表面の電極４に連続し
た配線は、図示はしていないが、このキャップ６の外方
に導出され、回路基板２の側方に突出した外部リード
や、回路基板２を貫通した外部リード等に半田等を用い
て電気的に接続されている。Although not shown, the wiring continuous with the electrodes 4 on the main surface of the circuit board 2 is led out to the outside of the cap 6 and external leads protruding to the side of the circuit board 2, It is electrically connected to an external lead or the like penetrating the circuit board 2 by using solder or the like.
【００１６】また、上記突起７の数は、３個以上１０個
以下が、高さＨを一定に確保しつつ、機械的強度を保つ
上でより好ましいが、１個乃至２個でもよい。The number of the projections 7 is preferably 3 or more and 10 or less in order to keep the height H constant and to maintain the mechanical strength, but it may be 1 or 2.
【００１７】図２は本発明の第２の実施例のベアチップ
実装構造の半導体装置を示す断面図である。図２におい
て、本実施例は、回路基板２を貫通する貫通孔８がほぼ
中央に形成され、この孔８内に封止樹脂５が入っている
こと以外は、図１の実施例と共通するため、共通する部
分の説明を省く。回路基板２に設けた貫通孔８は、ＩＣ
チップ１を封止する際の樹脂５の流れ込み性を向上する
ための空気抜きであり、これにより気泡の発生を防ぐこ
とができる。また、貫通孔８は封止樹脂の注入口として
利用することもできる。この貫通孔８は、封止樹脂５の
粘性やＩＣチップ１の大きさに応じて、適宜複数で用い
られることもある。FIG. 2 is a sectional view showing a semiconductor device having a bare chip mounting structure according to a second embodiment of the present invention. In FIG. 2, this embodiment is the same as the embodiment of FIG. 1 except that a through hole 8 penetrating the circuit board 2 is formed substantially at the center and the sealing resin 5 is contained in this hole 8. Therefore, the description of the common part is omitted. The through hole 8 provided in the circuit board 2 is an IC
This is an air vent for improving the flow-in property of the resin 5 when the chip 1 is sealed, which can prevent the generation of bubbles. The through hole 8 can also be used as an injection port for the sealing resin. A plurality of through holes 8 may be appropriately used depending on the viscosity of the sealing resin 5 and the size of the IC chip 1.
【００１８】図３は本発明は第３の実施例のベアチップ
実装構造の半導体装置を示す断面図である。図３におい
て、本実施例は、金属キャップ６のほぼ中央に貫通孔９
が形成されていること以外図１の実施例と共通するた
め、この共通する部分は、共通の参照数字で図示するに
とどめ、説明を省略する。本実施例で金属キャップ６に
形成した貫通孔９はＩＣチップ１を封止する際の樹脂の
流れ込み性を向上するための空気抜きであり、これで気
泡の発生を防ぐことができる。また貫通孔８は封止樹脂
の注入口として利用することもできる。この貫通孔９
も、必要に応じて、複数設けられることもある。FIG. 3 is a sectional view showing a semiconductor device having a bare chip mounting structure according to a third embodiment of the present invention. In FIG. 3, in the present embodiment, a through hole 9 is formed at approximately the center of the metal cap 6.
Since it is common to the embodiment of FIG. 1 except that the parts are formed, the common parts are shown by common reference numerals, and the description thereof will be omitted. The through-hole 9 formed in the metal cap 6 in this embodiment is an air vent for improving the flowability of the resin when the IC chip 1 is sealed, and this can prevent the generation of bubbles. The through hole 8 can also be used as an injection port for the sealing resin. This through hole 9
Also, a plurality of them may be provided as necessary.
【００１９】次に、本発明の第４の実施例の半導体装置
として、図２の第２の実施例と図３の第３の実施例とを
組み合わせた構成があり、本実施例によれば、製造方法
がより容易となる。Next, as a semiconductor device according to a fourth embodiment of the present invention, there is a configuration in which the second embodiment of FIG. 2 and the third embodiment of FIG. 3 are combined, and according to this embodiment. The manufacturing method becomes easier.
【００２０】本実施例を図２，図３を用いて説明する
と、回路基板２及び金属キャップ６に設けた貫通孔８，
９は、ＩＣチップ１を封止する際の樹脂の流れ込み性を
向上するための空気抜きであり、気泡の発生を防ぐこと
ができる。また貫通孔８および貫通孔９は封止樹脂の注
入口として利用することもできる。This embodiment will be described with reference to FIGS. 2 and 3. Through holes 8 formed in the circuit board 2 and the metal cap 6,
Reference numeral 9 is an air vent for improving the flowability of the resin when the IC chip 1 is sealed, and can prevent the generation of bubbles. Further, the through hole 8 and the through hole 9 can also be used as an injection port for the sealing resin.
【００２１】次に、上記第１，第２の実施例のベアチッ
プ実装構造の製造方法の第１の実施例を、図４（ａ）乃
至（ｃ）を用いて説明する。本実施例の製造方法は、ま
ず、図４（ａ）において、回路基板２上に形成された電
極４のパターンにバンプ３を介してＩＣチップ１をフリ
ップチップ接続する。次いで図４（ｂ）に示すように、
ＩＣチップ１を接続した回路基板２を上下逆転させると
ともに、適量の封止樹脂５を満たした三つの突起７を内
側の底面に形成した金属キャップ６の上に配置する。金
属キャップ６ならびに回路基板２を５０〜７０℃に加熱
する事により、封止樹脂５の流動性を増加させつつ、金
属キャップ６に形成した三つの突起７均一に樹脂５がＩ
Ｃチップ１の裏面に接触するように静かに下降させる。
この金属キャップ６は、端部が回路基板２より１ｍｍ程
度浮いた状態となるように設計しており、この間隙が空
気抜きとなって封止樹脂５は毛管現象によりＩＣチップ
１と回路基板２の間隙に充填される。充填が完了したな
らば、図４（ｃ）に示すように、封止樹脂５の硬化温度
に設定された恒温槽中にて加熱、硬化させてベアチップ
実装製品を得る。図４（ｃ）で封止樹脂５を硬化させる
ときは、必要に応じて金属キャップ６を回路基板２の方
向へ押圧しても良い。本実施例において、金属キャップ
６、回路基板２の一方又は両方に貫通孔を設けてもよ
く、その場合は樹脂を充填するときの空気抜きとなるの
で金属キャップ６の一端は回路基板２と接触する必要は
ない。Next, a first embodiment of the bare chip mounting structure manufacturing method of the first and second embodiments will be described with reference to FIGS. 4 (a) to 4 (c). In the manufacturing method of this embodiment, first, in FIG. 4A, the IC chip 1 is flip-chip connected to the pattern of the electrodes 4 formed on the circuit board 2 via the bumps 3. Then, as shown in FIG.
The circuit board 2 to which the IC chip 1 is connected is turned upside down, and three protrusions 7 filled with an appropriate amount of the sealing resin 5 are placed on the metal cap 6 formed on the inner bottom surface. By heating the metal cap 6 and the circuit board 2 to 50 to 70 ° C., the fluidity of the sealing resin 5 is increased and the three protrusions 7 formed on the metal cap 6 are uniformly coated with the resin 5.
Gently lower it so that it contacts the back surface of C chip 1.
The metal cap 6 is designed so that the end portion thereof floats above the circuit board 2 by about 1 mm, and this gap serves as an air vent so that the sealing resin 5 is separated from the IC chip 1 and the circuit board 2 by a capillary phenomenon. The gap is filled. When the filling is completed, as shown in FIG. 4C, a bare chip mounted product is obtained by heating and curing in a thermostatic chamber set to the curing temperature of the sealing resin 5. When the sealing resin 5 is cured in FIG. 4C, the metal cap 6 may be pressed toward the circuit board 2 if necessary. In the present embodiment, one or both of the metal cap 6 and the circuit board 2 may be provided with a through hole. In that case, one end of the metal cap 6 contacts the circuit board 2 because air is released when the resin is filled. No need.
【００２２】尚、上記第３，第４の実施例に、図４の製
造方法を適用する場合には、金属キャップ６の貫通孔９
から封止樹脂５が漏れないように、この貫通孔を金属シ
ールで軽く封止しておくか、または封止樹脂５の粘度で
は滴下しない程の小さい直径の貫通孔としておけばよ
い。When the manufacturing method of FIG. 4 is applied to the third and fourth embodiments, the through hole 9 of the metal cap 6 is used.
This through hole may be lightly sealed with a metal seal so that the sealing resin 5 does not leak from it, or the through hole may have a diameter that is small enough not to drop due to the viscosity of the sealing resin 5.
【００２３】図５（ａ）乃至（ｄ）は、上記第３，第４
の実施例のベアチップ実装構造を対象とした製造方法の
第２の実施例を示す断面図である。図５（ａ）におい
て、本実施例の製造方法では、回路基板２上に形成され
た電極４パターンにバンプ３を介してＩＣチップ１をフ
リップチップ接続する。次いで図５（ａ）に示すよう
に、ＩＣチップ１の一側面に封止樹脂５をＩＣチップと
回路基板２の間隙を充填するだけの必要量を供給し、５
０〜７０℃に加熱する事により流動性を増加させ毛管現
象によって封止する（図５（ｂ））。さらに封止樹脂５
によって全体を覆うため、三つの突起７を形成した金属
キャップ６をＩＣチップ１に位置決めし、三つの突起７
が均一にＩＣチップ１の裏面に接触するように下降さ
せ、封止樹脂５をディスペンサ１０より吐出、金属キャ
ップ６へ注入する。この金属キャップ６は一端が回路基
板２より１ｍｍ程度浮いた状態となるように設計してお
り、この間隙が空気抜きとなって封止樹脂５は毛管現象
により金属キャップ６内に充填される（図５（ｃ））。
所定量の封止樹脂５が注入完了した後、樹脂の硬化温度
に設定された恒温槽中にて加熱、硬化させてベアチップ
実装製品を得る（図５（ｄ））。図５（ｄ）で封止樹脂
５を硬化させるときは、必要に応じて金属キャップ６を
回路基板２の方向へ押圧しても良い。FIGS. 5 (a) to 5 (d) show the above third and fourth parts.
FIG. 5 is a cross-sectional view showing a second embodiment of the manufacturing method for the bare chip mounting structure of the embodiment. In FIG. 5A, in the manufacturing method of this embodiment, the IC chip 1 is flip-chip connected to the pattern of the electrodes 4 formed on the circuit board 2 via the bumps 3. Next, as shown in FIG. 5A, the sealing resin 5 is supplied to one side surface of the IC chip 1 in an amount necessary to fill the gap between the IC chip and the circuit board 2, and
The fluidity is increased by heating to 0 to 70 ° C. and sealing is performed by a capillary phenomenon (FIG. 5 (b)). Further sealing resin 5
The metal cap 6 having the three protrusions 7 is positioned on the IC chip 1 in order to cover the whole with the three protrusions 7.
Is uniformly contacted with the back surface of the IC chip 1, and the sealing resin 5 is discharged from the dispenser 10 and injected into the metal cap 6. The metal cap 6 is designed so that one end of the metal cap 6 floats above the circuit board 2 by about 1 mm, and this gap serves as an air vent so that the sealing resin 5 is filled in the metal cap 6 by a capillary phenomenon (see FIG. 5 (c)).
After the injection of the predetermined amount of the sealing resin 5 is completed, it is heated and cured in a thermostatic bath set to the curing temperature of the resin to obtain a bare chip mounted product (FIG. 5 (d)). When the sealing resin 5 is cured in FIG. 5D, the metal cap 6 may be pressed toward the circuit board 2 if necessary.
【００２４】本実施において回路基板２にも、貫通孔を
設けてもよく、その場合は樹脂を充填するときの空気抜
きとなるので、金属キャップ６の端部は回路基板２と接
触する必要はない。この場合は、特に回路基板２とＩＣ
チップ１との間に封止樹脂５を流し込む工程（図５の
（ｂ））を省き、（ｃ）の工程により一括して封止樹脂
５を流し込んでもよい。In the present embodiment, the circuit board 2 may also be provided with a through hole. In this case, air is released when the resin is filled, so that the end of the metal cap 6 does not need to contact the circuit board 2. . In this case, especially the circuit board 2 and the IC
The step of pouring the sealing resin 5 into the chip 1 ((b) of FIG. 5) may be omitted, and the sealing resin 5 may be collectively poured in the step of (c).
【００２５】また、上記工程で図５（ｂ）の最初の封止
樹脂を省略してもよく、回路基板２の貫通孔から封止樹
脂を注入してもよく、この場合は金属キャップにも貫通
孔が形成されていなくともよいが、形成されていること
がより好ましく、空気が抜けると共に樹脂が流入して、
気泡のない封止が行なわれる。これを、本発明の製造方
法の第３の実施例とする。In the above process, the first sealing resin shown in FIG. 5B may be omitted, or the sealing resin may be injected through the through hole of the circuit board 2. In this case, the metal cap may be also injected. The through hole may not be formed, but it is more preferable that the through hole is formed.
A bubble-free seal is provided. This is a third embodiment of the manufacturing method of the present invention.
【００２６】以上本発明のベアチップ実装構造は、回路
基板２上のＩＣベアチップを覆うように金属キャップ６
がかぶせられており、ＩＣと金属キャップ６のギャップ
は金属キャップ６上の突起がＩＣ裏面に接触することに
より、コントロールされている。回路基板２と金属キャ
ップ６で囲まれた空間は封止樹脂５が充填されている。
樹脂５の充填のために金属キャップ６および基板２のど
ちらかもしくは両方にひとつもしくは複数の貫通孔があ
ってよい。このような金属キャップ６と封止樹脂５を用
いた実装構造の製造方法として大きく分類して二つの方
法がある。第一の方法は金属キャップに液状の封止樹脂
をあらかじめ満たしておき、ここに回路基板に搭載され
たＩＣを浸すようにしてから硬化させる方法である。第
二の方法は回路基板上に金属キャップをかぶせてからキ
ャップもしくは基板の貫通孔から樹脂を流し込み、それ
から硬化させる方法である。As described above, in the bare chip mounting structure of the present invention, the metal cap 6 covers the IC bare chip on the circuit board 2.
And the gap between the IC and the metal cap 6 is controlled by the protrusion on the metal cap 6 contacting the back surface of the IC. The space surrounded by the circuit board 2 and the metal cap 6 is filled with the sealing resin 5.
There may be one or more through holes in either or both of the metal cap 6 and the substrate 2 for the filling of the resin 5. There are roughly two methods of manufacturing a mounting structure using the metal cap 6 and the sealing resin 5. The first method is to fill a metal cap with a liquid sealing resin in advance, immerse the IC mounted on the circuit board therein, and then cure the IC. The second method is to cover the circuit board with a metal cap, pour resin through the through hole of the cap or the board, and then cure the resin.
【００２７】[0027]
【発明の効果】以上の通り、本発明によれば、前記課題
が達成され、次の効果が得られる。 （１）従来の樹脂の広範囲にわたる流れだしを防ぐこと
で、実装密度を向上させている。 （２）封止樹脂流し込み時における気泡の発生を防ぎ歩
留まりを向上させている。 （３）ＩＣチップを機械的衝撃から保護している。 （４）ＩＣチップを湿潤による腐食などからも保護して
いる。 （５）熱ストレスで、キャップ等がはがれることがな
い。 （６）突起と、ＩＣチップ−キャップ間の樹脂層とを設
けることにより、機械的に強く、放熱効果が一定とな
る。As described above, according to the present invention, the above problems can be achieved and the following effects can be obtained. (1) The packaging density is improved by preventing the conventional resin from flowing out over a wide range. (2) Bubbles are prevented from being generated when the sealing resin is poured, and the yield is improved. (3) The IC chip is protected from mechanical shock. (4) It also protects the IC chip from corrosion due to wetting. (5) Caps and the like will not come off due to heat stress. (6) By providing the protrusion and the resin layer between the IC chip and the cap, it is mechanically strong and the heat dissipation effect becomes constant.
【００２８】以上により、信頼性の高い半導体装置とそ
の製造方法が得られる。As described above, a highly reliable semiconductor device and its manufacturing method can be obtained.
【図１】本発明の第１の実施例の半導体装置を示す断面
図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施例の半導体装置を示す断面
図である。FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図３】本発明の第３の実施例の半導体装置を示す断面
図である。FIG. 3 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
【図４】（ａ）乃至（ｃ）は第１，第２の実施例を対象
とする製造方法の第１の実施例を工程順に示す断面図で
ある。4 (a) to 4 (c) are cross-sectional views showing, in the order of steps, a first embodiment of a manufacturing method targeting the first and second embodiments.
【図５】（ａ）乃至（ｄ）は本発明の第３，第４の実施
例を対象とする製造方法の第２の実施例を工程順に示す
断面図である。5 (a) to 5 (d) are cross-sectional views showing, in the order of steps, a second embodiment of the manufacturing method targeted for the third and fourth embodiments of the present invention.
【図６】第１の従来例を示す断面図である。FIG. 6 is a cross-sectional view showing a first conventional example.
【図７】第２の従来例を示す断面図である。FIG. 7 is a cross-sectional view showing a second conventional example.
【図８】（ａ）乃至（ｄ）は第３の従来例を工程順に示
す断面図である。8A to 8D are cross-sectional views showing a third conventional example in the order of steps.
１ ＩＣチップ ２ 回路基板 ３ バンプ ４ 電極 ５ 封止樹脂 ６ 金属キャップ ７ 突起 ８ 貫通孔 ９ 貫通孔 １０ ディスペンサ ２１ 樹脂通過穴 ２２ 封止樹脂 ２３ 樹脂ディスク ２４ 多孔質板材 ２５ 樹脂枠 ２７ 金属層 ２８ 配線層 1 IC Chip 2 Circuit Board 3 Bump 4 Electrode 5 Sealing Resin 6 Metal Cap 7 Protrusion 8 Through Hole 9 Through Hole 10 Dispenser 21 Resin Passing Hole 22 Sealing Resin 23 Resin Disk 24 Porous Plate Material 25 Resin Frame 27 Metal Layer 28 Wiring layer
Claims (7)
バンプを介して、半導体チップの一主表面上の電極部分
が固着され、少なくとも前記チップ，前記バンプ、及び
前記電極を覆うように金属キャップを設け、前記キャッ
プと前記回路基板とで覆われた内部を樹脂で封止してな
る半導体装置において、前記金属キャップの内面に、前
記チップの他の主表面と接触する突起が形成されている
ことを特徴とする半導体装置。1. An electrode formed on a main surface of a circuit board,
An electrode portion on one main surface of a semiconductor chip is fixed via a bump, a metal cap is provided so as to cover at least the chip, the bump, and the electrode, and the inside covered with the cap and the circuit board. A semiconductor device in which the above is sealed with a resin, wherein a protrusion that comes into contact with the other main surface of the chip is formed on the inner surface of the metal cap.
部分に、貫通孔が形成されている請求項１記載の半導体
装置。2. The semiconductor device according to claim 1, wherein the circuit board has a through hole formed in a portion facing the chip.
した部分に、貫通孔が形成されている請求項１及び２記
載の半導体装置。3. The semiconductor device according to claim 1, wherein the metal cap has a through hole formed in a portion facing the chip.
介して、半導体チップの一主表面の電極部分を固着する
工程と、少なくとも前記電極、前記バンプ，及び前記チ
ップを覆うための液状の封止樹脂を、内面に突起を形成
した金属キャップ内に入れる工程と、前記チップが前記
封止樹脂と対向するように前記回路基板を反転する工程
と、前記回路基板と前記金属キャップとを互いに接近さ
せ、前記チップの他主表面が前記突起と接触した状態で
前記封止樹脂を硬化させる工程とを含むことを特徴とす
る半導体装置の製造方法。4. A step of fixing an electrode portion on one main surface of a semiconductor chip to an electrode on the main surface of a circuit board via a bump, and a liquid for covering at least the electrode, the bump and the chip. The step of placing the sealing resin of 1. into a metal cap having a protrusion formed on the inner surface thereof, the step of reversing the circuit board so that the chip faces the sealing resin, and the circuit board and the metal cap. A step of bringing the chips closer to each other and curing the sealing resin in a state where the other main surface of the chip is in contact with the protrusion.
して、半導体チップの一主表面の電極部分を固着する工
程と、内面に突起が形成され、かつ貫通孔が形成された
金属キャップを、前記チップを覆うように位置させる工
程と、前記貫通穴から封止樹脂を注入して内空を埋め尽
す工程と、前記チップの他主表面と前記突起とを接触さ
せた状態で前記封止樹脂を硬化させる工程とを含むこと
を特徴とする半導体装置の製造方法。。5. A step of fixing an electrode portion on one main surface of a semiconductor chip to an electrode on the main surface of a circuit board via a bump, and a metal cap having a protrusion formed on the inner surface and a through hole. The step of positioning so as to cover the chip, the step of injecting a sealing resin from the through hole to fill the inner space, and the sealing while the other main surface of the chip is in contact with the protrusion. And a step of curing the stop resin. .
電極に、バンプを介して、半導体チップの一主表面の電
極部分を固着する工程と、内面に突起が形成された金属
キャップを、前記チップを覆うように位置させる工程
と、前記貫通穴から封止樹脂を注入して内空を埋め尽す
工程と、前記チップの他主表面と前記突起とを接触させ
た状態で前記封止樹脂を硬化させる工程とを含むことを
特徴とする半導体装置の製造方法。6. A step of fixing an electrode portion on one main surface of a semiconductor chip to an electrode on the main surface of a circuit board having a through hole formed thereon via a bump, and a metal cap having a projection formed on an inner surface thereof. A step of positioning so as to cover the chip, a step of injecting a sealing resin from the through hole to fill the inner space, and the sealing while the other main surface of the chip is in contact with the protrusion A method of manufacturing a semiconductor device, comprising the step of curing a resin.
ように位置させる工程の前の工程において、少なくとも
前記電極，前記バンプ，及び前記チップの一主表面を覆
うように、前記回路基板上に液状の封止樹脂を滴下する
工程を有する請求項５又は６記載の半導体装置の製造方
法。7. The liquid on the circuit board so as to cover at least the electrodes, the bumps, and one main surface of the chip in a step before the step of positioning the metal cap so as to cover the chip. 7. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of dropping the sealing resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6144292A JP2536456B2 (en) | 1994-06-27 | 1994-06-27 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6144292A JP2536456B2 (en) | 1994-06-27 | 1994-06-27 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0817853A true JPH0817853A (en) | 1996-01-19 |
| JP2536456B2 JP2536456B2 (en) | 1996-09-18 |
Family
ID=15358681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6144292A Expired - Fee Related JP2536456B2 (en) | 1994-06-27 | 1994-06-27 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536456B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270604A (en) * | 1997-03-25 | 1998-10-09 | Mitsumi Electric Co Ltd | Electronic component module |
| JPH10303689A (en) * | 1997-04-25 | 1998-11-13 | Hitachi Media Electron:Kk | Surface acoustic wave device and method of manufacturing the same |
| JPH11340652A (en) * | 1998-05-28 | 1999-12-10 | Shin Etsu Chem Co Ltd | Method for bonding/fixing box incorporating part to be potted to base material and box storing part to be potted |
| JP2000151347A (en) * | 1998-11-06 | 2000-05-30 | Hitachi Media Electoronics Co Ltd | Surface mount type surface acoustic wave filter |
| CN1101063C (en) * | 1997-10-24 | 2003-02-05 | 日本电气株式会社 | Semiconductor device |
| US6826053B2 (en) | 2002-04-05 | 2004-11-30 | Murata Manufacturing Co., Ltd | Electronic device |
| JP2010251527A (en) * | 2009-04-16 | 2010-11-04 | Panasonic Corp | Electronic component and method for manufacturing electronic component |
| JP2011146415A (en) * | 2010-01-12 | 2011-07-28 | Renesas Electronics Corp | Semiconductor apparatus and method of manufacturing semiconductor apparatus |
| WO2017175274A1 (en) * | 2016-04-04 | 2017-10-12 | 株式会社日立製作所 | Sealing structure and method for manufacturing same |
-
1994
- 1994-06-27 JP JP6144292A patent/JP2536456B2/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270604A (en) * | 1997-03-25 | 1998-10-09 | Mitsumi Electric Co Ltd | Electronic component module |
| JPH10303689A (en) * | 1997-04-25 | 1998-11-13 | Hitachi Media Electron:Kk | Surface acoustic wave device and method of manufacturing the same |
| CN1101063C (en) * | 1997-10-24 | 2003-02-05 | 日本电气株式会社 | Semiconductor device |
| JPH11340652A (en) * | 1998-05-28 | 1999-12-10 | Shin Etsu Chem Co Ltd | Method for bonding/fixing box incorporating part to be potted to base material and box storing part to be potted |
| JP2000151347A (en) * | 1998-11-06 | 2000-05-30 | Hitachi Media Electoronics Co Ltd | Surface mount type surface acoustic wave filter |
| US6826053B2 (en) | 2002-04-05 | 2004-11-30 | Murata Manufacturing Co., Ltd | Electronic device |
| JP2010251527A (en) * | 2009-04-16 | 2010-11-04 | Panasonic Corp | Electronic component and method for manufacturing electronic component |
| JP2011146415A (en) * | 2010-01-12 | 2011-07-28 | Renesas Electronics Corp | Semiconductor apparatus and method of manufacturing semiconductor apparatus |
| US8519529B2 (en) | 2010-01-12 | 2013-08-27 | Renesas Electronics Corporation | Semiconductor package with lid bonded on wiring board and method of manufacturing the same |
| WO2017175274A1 (en) * | 2016-04-04 | 2017-10-12 | 株式会社日立製作所 | Sealing structure and method for manufacturing same |
| JPWO2017175274A1 (en) * | 2016-04-04 | 2018-11-08 | 株式会社日立製作所 | Sealing structure and manufacturing method thereof |
| US11244877B2 (en) | 2016-04-04 | 2022-02-08 | Hitachi, Ltd. | Sealing structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2536456B2 (en) | 1996-09-18 |
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