JPH0817358B2 - Frame phase synchronization circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frame phase synchronizing circuit for synchronizing the phases of a plurality of types of frames, and particularly to optimizing the phase between frames at power-on and recovery of input signal loss. The present invention relates to a frame phase synchronization circuit that can be used.

[Prior Art] A conventional frame phase synchronizing circuit includes a digital synchronizing circuit as described in Japanese Patent Application Laid-Open No. 57-168549.
The phase relationship of the frame created from the output clock of was undefined.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, no consideration is given to the fact that the phase between frames becomes indefinite when the power is turned on and when the input signal is recovered, and the PLL is normal. There is a problem in that frame synchronization is lost, and there is a problem that if N PLLs are out of synchronization, N times more likely to occur.

An object of the present invention is to provide a frame phase synchronizing circuit capable of preventing the frame from being out of sync even when the circuit is normal by setting the phase relationship between frames optimally at power-on and recovery of input signal loss. Especially.

[Means for Solving the Problems] The above object is to provide a frame phase synchronization circuit including a window creation circuit for creating a window of a phase error standard and a phase comparison circuit for comparing an input frame with the window when power is turned on. And a frame phase synchronization circuit provided with a selector circuit for switching the load signal of the counter in the window creating circuit from the frame created from the PLL output clock to the input frame when the input signal is recovered.

[Operation] The frame phase synchronization circuit uses the frame created from the input clock and the PLL output clock because the initial value of the counter in the window creation circuit is undefined if the selector circuit is not present when the power is turned on and when the input signal is restored. The phase relationship with the created frame (or window mask) is indefinite and the frame phase synchronization is lost due to fluctuations in the PLL drift. On the other hand, when the power is turned on or the input signal is recovered, the selector circuit above the PLL output clock Since the counter in the window creation circuit is loaded by switching from the created frame to the frame created from the input clock, it is possible to match the phase of the frame created from the input clock with the frame created from the PLL output clock, Therefore, frame phase synchronization is lost during operation. Can be prevented.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing an embodiment of a frame phase synchronizing circuit according to the present invention. In FIG. 1, 1 is a frame creation circuit, 2 is a PLL, 3 is a frame phase synchronization circuit,
4 is a gate, 5 is a selector circuit, 6 is a WIND (window) creation circuit, 7 is a counter, 8 is WIND (window)
Mask waveform, 9 is phase comparator, 10 is RESET signal, CLK1 is input clock, CLK2 is output clock,
FP1 is an input frame, FP2 is an output frame, POR is a power-on reset signal, and REC is an input signal disconnection detection signal.

The input frame FP1 is made by the frame making circuit 1 from the input clock CLK1 shown in FIG. The output frame FP2 is made by the counter 7 of the WIND making circuit 6 from the output clock CLK2 of the PLL2 which receives the input clock CLK1. Also counter 7
A WIND (waveform) 8 of a phase error standard for monitoring the phase difference between frames is created from each output of. The WIND8 and the input frame FP1 are compared by the phase comparison circuit 9, and if the phase difference between the frames is below the standard, the RESET signal 10 is sent to the selector circuit 5. In the steady state, the selector circuit 5 selects the RESET signal 10.
As a result, when the phase difference between frames falls below the standard in a steady state, the counter 7 is reloaded by the RESET signal output from the selector circuit 5. If the phase difference between the frames is within the standard, the RESET signal 10 does not come and the counter 7 runs by itself. According to the present invention, the selector circuit 5 selects the input frame FP1 by inputting the power-on reset signal P0R and the input signal disconnection detection signal REC when the power is turned on and when the input signal disconnection is recovered.

FIG. 2 is a time chart of the WIND mask and the input frame FP1 showing the operation of FIG. First, in the conventional circuit without the selector circuit 5 shown in FIG. 1, since the initial value of the counter 7 of the WIND creating circuit 6 is undefined at the time of power-on and recovery of input signal loss, the frame FP1 created from the input clock CLK1 Frame created from PLL output clock CLK2
The phase relationship with FP2 (or WIND mask 8) is undefined. Here, the phase relationship between WIND8 and the input frame FP1 in FIG. 2 is stochastically small as in the case. Input frame FP1 is WIND mask 8 like a case
If not, the counter 7 is reloaded to enter the case, and if PLL2 is normal, the frame synchronization is not lost. Since this operation is completed immediately after the power is turned on, there is no problem. If the input frame FP1 is in the WIND mask 8 as in the case, W
Since it is in the IND mask 8, it operates as it is, but the phase margin is small. Therefore, the drift fluctuation of the PLL2 due to the temperature fluctuation or the power fluctuation (even the drift fluctuation within the standard) causes the input frame FP1 to deviate from the WIND mask 8 and cause the frame phase synchronization to be lost. The timing of this occurrence is indefinite, and a malfunction such as a code error occurs in the entire device during operation. On the other hand, in the circuit of this embodiment in which the selector circuit 5 is provided, the selector circuit 5 selects the frame FP1 created from the input clock CLK1 when the power is turned on and when the input signal is recovered, and the counter of the WIND creating circuit 6 is thereby selected. Since 7 is loaded, the frame created from the input clock CLK1
The phase of frame FP2 created from FP1 and PLL output clock CLK2 can be matched. Thus, even when the power is turned on and the input signal is recovered, the output of the counter 7 does not become indefinite, and it is possible to prevent the situation of the case of FIG.
Therefore, it is possible to prevent the frame phase synchronization from being deviated during the operation to cause a malfunction such as a code error in the entire device.

[Effects of the Invention] According to the present invention, the phase between frames can be optimally set when the power is turned on and when the input signal is recovered, so that it is possible to prevent a malfunction such as a code error from occurring in the entire device during operation. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the frame phase synchronizing circuit according to the present invention, and FIG. 2 is a time chart showing the operation of FIG. 1 ... frame creating circuit, 2 ... PLL, 3 ... frame phase synchronizing circuit, 4 ... gate, 5 ... selector circuit, 6
...... WIND (window) creation circuit, 7 ... Counter, 8
...... WIND waveform, 9 ...... Phase comparison circuit, 10 ...... RESET signal.

Claims (1)

[Claims] 1. A frame phase synchronizing circuit comprising a window creating circuit for creating a window of a phase error standard and a phase comparing circuit for comparing an input frame with the window. A frame phase synchronization circuit characterized by comprising a selector circuit for switching a load signal of a generating circuit from a frame generated from a PLL output clock to an input frame.