JPH08265150A - Phase locked loop oscillation circuit - Google Patents

Abstract

PURPOSE: To reduce the time up to phase locking when a phase comparator and a frequency divider transit from the off-state into the on-state. CONSTITUTION: In the initial state when a frequency divider C and a phase comparator A being peripheral circuits arise from the off-state into the on-state when a variable frequency oscillator B is in the on-state and the peripheral circuits are in the on/off intermittent state, a leading control signal 6 rises at an input of a phase initializing circuit D and an input clock signal 1 rises, then the circuit D provides an output of a signal 5 to reset the frequency divider C at a leading edge of the signal 1. Then, the frequency divider C outputs a comparison clock signal 2 reset by the signal 5. In this case, the phases of the signals 1, 2 are made coincident. When the phases of the signals 1, 2 are coincident, a phase comparison rising signal 7 is outputted from a rising control circuit E having received the control signal 6 to activate the phase comparator A which starts phase comparison.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is also referred to as a phase locked oscillator circuit (PLL circuit) used in the field of digital mobile communication.
Same as below), operating the variable frequency oscillator in the standby state, only the peripheral circuits (frequency divider, phase comparator),
In particular, the present invention relates to a PLL circuit used in an intermittent operation that turns on and off, and particularly to a PLL circuit that shortens the time until phase synchronization.

[0002]

2. Description of the Related Art A conventional phase-locked oscillator circuit detects the phase difference between an input clock signal 1 and a comparison clock signal 2 from a frequency divider C for dividing an output clock signal 4 as shown in FIG. It comprises a phase comparator A for comparing and outputting an output control signal 3 showing the phase difference, and a variable frequency oscillator B for varying the output frequency by the output control signal 3.

In the conventional phase-locked oscillator circuit having such a configuration, when the frequency of the output clock signal 4 from the variable frequency oscillator B decreases, the phase of the comparison clock signal 2 output from the frequency divider C becomes the input clock signal 1. , The output control signal 3 of the phase comparator A operates to increase the frequency of the output clock signal 4 of the variable frequency oscillator B. Further, when the frequency of the output clock signal 4 rises, the phase of the comparison clock signal 2 leads the phase of the input clock signal 1,
The output control signal 3 of the phase comparator A operates so as to reduce the frequency of the output clock signal 4 of the variable frequency oscillator B. Thus, as a result, the output clock signal 4 is synchronized with the input clock signal 1.

This conventional phase-locked oscillator circuit has a problem that the variable frequency oscillator B is not in a normal state immediately after the power supply to the entire circuit is turned on, and an abnormal frequency is output. Even in the normal state, since the phase relationship between the input clock signal 1 and the comparison clock signal 2 is indefinite, it takes time until the phase synchronization occurs, and it takes time to obtain the output clock signal 4 synchronized with the input clock signal 1. is there.

In order to shorten the synchronization time after the variable frequency oscillator B is in the normal state, a phase locked oscillator circuit as disclosed in Japanese Patent Laid-Open No. 4-165819 has been proposed. That is, as shown in FIG. 7, the variable frequency oscillator B has an abnormal frequency immediately after the power supply to the entire circuit is turned on, but thereafter, when the frequency becomes a normal frequency, this is detected by the normal state detection circuit F, It is described that the subsequent phase synchronization time is shortened by the phase initialization circuit D.

[0006]

In the conventional phase-locked oscillator circuit (FIG. 6), the variable frequency oscillator B is not in a normal state immediately after the circuit is turned on, and an abnormal frequency is output. There is. This also applies to the configuration of FIG. 7. In order to solve this problem, there is a method of operating the variable frequency oscillator B in a standby state in an on state and repeating the intermittent operation in which only the peripheral circuits are turned on and off. There was a problem that time was required until phase synchronization at the time of transition. That is, even if the frequency of the output clock signal 4 matches the frequency of the input clock signal 1 when the variable frequency oscillator B is on, the phase does not match and the phase comparator A
Therefore, the frequency of the output clock signal 4 changes until the phases match and it takes time to synchronize. Further, since the phase comparator A operates in a state where the phases do not match, there is a problem that the output frequency of the variable frequency oscillator B excessively changes.

Therefore, an object of the present invention is to provide a phase-locked oscillator circuit that solves the above problems.

[0008]

In order to achieve the above object, the invention according to claim 1 provides a phase for phase comparison between an input clock signal and a comparison clock signal from a frequency divider for dividing an output clock signal. In a phase-locked oscillator circuit having a comparator and a variable frequency oscillator that frequency-controls the output clock signal in response to a signal generated by the phase comparator, A phase initialization circuit that initializes the phases simultaneously; and a startup control circuit that starts the operation of the phase comparator after the phase of the input clock signal and the phase of the comparison clock signal match. To do.

According to a second aspect of the invention, in the first aspect, the phase initialization circuit and the rise control circuit operate based on the same control signal.

[0010]

According to the present invention, when the variable frequency oscillator is operated in the standby state and the PLL circuit is operated by the intermittent operation in which only the peripheral circuits are turned on and off, the phase comparator is used after the input clock signal and the comparison clock signal are in phase with each other. Is operated, it is possible to shorten the time required for phase synchronization when the phase comparator and the frequency divider shift from the off state to the on state.
Further, when the phase of the input clock signal is different from that of the comparison clock signal by the start-up control circuit, the output frequency of the variable frequency oscillator is stable because phase comparison is not performed.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 4 shows a timing chart of signals in each part of the same figure. As shown in FIG. 1, in the steady state, the phase comparator A performs phase comparison between the input clock signal 1 and the comparison clock signal 2 from the frequency divider C that divides the output clock signal 4 and outputs the output control signal. 3 and the variable frequency oscillator B controls the frequency of the output clock signal 4 in response to the output control signal 3. D is a phase initialization circuit, and E is a start-up control circuit.

Referring to FIG. 4, in the present embodiment, when the variable frequency oscillator B is on and the peripheral circuit is on / off intermittently operating, the frequency divider C and the phase comparator A of the peripheral circuit are off. In the initial state of rising from the on state,
First, on the input side of the phase initialization circuit D, when the rising control signal 6 rises and then the input clock signal 1 rises, the phase initialization circuit D resets the frequency divider C at the rising edge of the input clock signal 1. Reset signal 5 is output. Then, the frequency divider C outputs the comparison clock signal 2 reset by the reset signal 5. At this time, the phases of the input clock signal 1 and the comparison clock signal 2 match. After the phases of the input clock signal 1 and the comparison clock signal 2 coincide with each other, the phase-control start-up signal 7 is output from the start-up control circuit E in which the start-up control signal 6 has been input, which turns on the phase comparator A. Start phase comparison. The start-up control circuit E is functionally a delay circuit, and an example of a specific circuit is shown as a block diagram in FIG.
Shown in It consists of two flip-flops.

As described above, since the phase comparator A operates after the phases of the input clock signal 1 and the comparison clock signal 2 match, a stable output clock signal can be obtained and the time until synchronization can be shortened. The time until this synchronization is determined by the time from the rise of the rise control signal 6 to the rise of the phase comparison rise signal 7 in the timing chart of FIG. That is, the startup control circuit E
By arbitrarily setting the delay amount (time) of, the time until the above synchronization can be set.

A concrete example of the phase initialization circuit D is shown in FIG.
This circuit is a latch circuit with set and reset 21.
And an AND gate 22, a delay circuit 23, and an inverter gate 24. The rising control signal 6 cancels the setting of the latch circuit 21, and the next input clock signal 1
The AND gate 22 outputs a signal (reset signal 5) for resetting the frequency divider C in response to the rising edge of. After that, the delay circuit 23 and the inverter gate 24 reset the latch circuit 21, and the reset signal 5 becomes a pulse signal. As another circuit of the phase initialization circuit D, FIG.
There is also a circuit that is configured by using an output clock signal 4 and a flip-flop 31 with a set instead of the delay circuit as shown in FIG. In FIG. 3, first, the setting of the flip-flop 31 is released by the rising control signal 6, and the AND gate 32 outputs the reset signal 5 for the time sampled by the output clock signal 4 by the next rising of the input clock signal 1. To do.

[0016]

As described above, according to the present invention,
It is possible to shorten the time required for the phase synchronization of the phase locked oscillator circuit when the phase comparator and the frequency divider shift from the off state to the on state.

Further, according to the present invention, when the variable frequency oscillator is in the intermittent operation, the frequency of the output clock signal matches the frequency of the input clock signal, but the phase does not match. Since there is no change in frequency, a stable oscillation frequency output can be obtained even during intermittent operation.

Further, according to the present invention, since the time until the synchronization is short and stable, the idle time can be lengthened and the current consumption of the entire phase-locked oscillator circuit can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a specific example of a phase initialization circuit.

FIG. 3 is a block diagram of another specific example of the same phase initialization circuit.

FIG. 4 is a diagram showing a timing chart of signals in each unit of the present embodiment.

FIG. 5 is a specific block diagram of a startup control circuit.

FIG. 6 is a block diagram of a conventional phase locked oscillator circuit.

FIG. 7 is a block diagram of another conventional phase locked oscillator circuit.

[Explanation of symbols]

 A phase comparator B variable frequency oscillator C frequency divider D phase initialization circuit E startup control circuit

Claims (2)

[Claims] 1. A phase comparator for phase-comparing an input clock signal and a comparison clock signal from a frequency divider for dividing the output clock signal, and the output clock in response to a signal generated by the phase comparator. In a phase-locked oscillation circuit having a variable frequency oscillator for frequency-controlling a signal, a phase initialization circuit for simultaneously initializing the phases of the input clock signal and the comparison clock of the phase comparator, and the phase of the input clock signal And a start-up control circuit for starting the operation of the phase comparator after the phase of the comparison clock signal matches. 2. The phase-locked oscillator circuit according to claim 1, wherein the phase initialization circuit and the startup control circuit operate based on the same control signal.