JPH08172168A - Ferroelectric nonvolatile storage device - Google Patents

Abstract

PURPOSE: To improve reliability and productivity of a wiring, by increasing the width of a wiring constituted of a conducting layer except a lower part electrode of a ferroelectric capacitor. CONSTITUTION: A Pt/TiN film 44 forming a storage node electrode 14 of a ferroelectric capacitor 12 is stretched from the ferroelectric capacitor 12 and made a wiring 42 connecting the storage node electrode 14 with a diffusion layer 25. Thereby, the margin at the time of performing layout of a bit line 16 by using an Al film 41 is large, as compared with, e.g. the structure wherein the Al film 41 is used as the wiring 42 in a memory cell 11, and the width of the bit line 16 can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric non-volatile memory device in which a memory cell is formed by using a ferroelectric capacitor.

[0002]

2. Description of the Related Art FIG. 2 shows an equivalent circuit of a memory cell in a ferroelectric nonvolatile memory device using a ferroelectric capacitor. The memory cell 11 includes a ferroelectric capacitor 12 and an access transistor 13. It consists of and. In the ferroelectric capacitor 12, the electrode on the side of the access transistor 13 is the storage node electrode 14, and the electrode on the side opposite to the access transistor 13 is the plate electrode 15.

A bit line 16 is connected to the source / drain of the access transistor 13 on the side opposite to the ferroelectric capacitor 12, and the word line 17 serves as the gate electrode of the access transistor 13.

FIG. 3 shows a first conventional example of the memory cell 11 shown in FIG. 2 (for example, Microelectronic Engi
neering 19 (1992) 245-252). In this first conventional example, S
The SiO ₂ film 22 is formed in the element isolation region of the i substrate 21, and the SiO ₂ film 23 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 22.

A word line 17 is formed of a polycrystalline Si film 24 on the SiO ₂ films 23 and 22, and diffusion layers 25 and 26 which are the source / drain of the access transistor 13 are formed.
Are formed in the element active regions on both sides of the polycrystalline Si film 24. The polycrystalline Si film 24 and the like are covered with the interlayer insulating film 27, and the plate electrode 15 is formed on the interlayer insulating film 27 with the Pt film 31.

On the Pt film 31, a ferroelectric thin film P
The ZT thin film 32 and the Pt film 33 are processed into the pattern of the storage node electrode 14 to form the ferroelectric capacitor 12. The ferroelectric capacitor 12 and the like are covered with the interlayer insulating film 34, and contact holes 35 to 37 reaching the diffusion layers 25 and 26 and the Pt film 33 are opened in the interlayer insulating films 34 and 27.

With the Al film 41 on the interlayer insulating film 34, the bit line 16 connected to the diffusion layer 26 through the contact hole 36.
And the diffusion layer 25 and Pt through the contact holes 35 and 37.
A wiring 42 that connects the film 33 is formed. Al
The film 41 and the like are covered with a surface protective film (not shown) and the like.

FIG. 4 shows a second conventional example of the memory cell 11 shown in FIG. 2 (for example, Microelectronic Engi
neering 19 (1992) 245-252). In the second conventional example, the polycrystalline Si film 24 and the like are covered with a flat interlayer insulating film 27, and a contact hole 35 reaching the diffusion layer 25 is opened in the interlayer insulating film 27.

The contact hole 35 is filled with a plug 43, and the Pt film 31 connected to the plug 43 forms the storage node electrode 14. On the Pt film 31 and the interlayer insulating film 27, the PZT thin film 32 and the Pt film 33, which are ferroelectric thin films, are processed into the pattern of the plate electrode 15 to form the ferroelectric capacitors 12.

The ferroelectric capacitor 12 and the like are formed by the interlayer insulating film 3
Contact hole 3 which is covered with 4 and reaches diffusion layer 26
6 is opened in the interlayer insulating films 34 and 27. And
The Al film 41 on the interlayer insulating film 34 forms the bit line 16 connected to the diffusion layer 26 via the contact hole 36. The Al film 41 and the like are covered with a surface protective film (not shown) and the like.

[0011]

However, in the first conventional example shown in FIG. 3, the Al film 41 is used to form the bit line 16 and the wiring 4.
Since both of them are formed, the margin when laying out this Al film 41 is small, and it is necessary to narrow the width of the bit line 16 and the like. Therefore, the bit line 16 and the like are not necessarily high in reliability and workability against electromigration, stress migration and the like.

Further, in the first conventional example, it is necessary to etch the contact hole 37 for connecting the diffusion layer 25 and the Pt film 33 with the wiring 42, and stress in the Pt film 33 due to hydrogen in the etching atmosphere. Occurs and this stress is P
It fixes the domain of the ZT thin film 32 and acts so as not to cause polarization (eg, 1994 Symposium on VLSI Techn
ology Digest of Technical Papers 55-56).

That is, the ferroelectric capacitor 12 is damaged by the etching for opening the contact hole 37, the polarization amount of the ferroelectric capacitor 12 is reduced, and the memory retention characteristic is deteriorated. There is.

On the other hand, in the second conventional example shown in FIG. 4, since the ferroelectric capacitor 12 is flat, the leak current in the ferroelectric capacitor 12 is small, the polarization characteristic is stable, and the memory retention characteristic is good. Are better. However, in order to flatten the ferroelectric capacitor 12, it is necessary to form the flat interlayer insulating film 27 and fill the contact hole 35 with the plug 43, so that the number of manufacturing steps is large and the manufacturing cost is high.

[0015]

A ferroelectric non-volatile memory device according to a first aspect of the present invention is a capacitor insulating film 3 made of a ferroelectric substance.
In a ferroelectric non-volatile memory device in which a memory cell 11 is constructed using a ferroelectric capacitor 12 having a ferroelectric capacitor 12, the conductive layer 44 forming the lower electrode 14 of the ferroelectric capacitor 12 is It is characterized in that it extends from the body capacitor 12 to form a wiring 42 in the memory cell 11.

According to another aspect of the ferroelectric non-volatile memory device of the present invention,
The ferroelectric non-volatile memory device according to claim 1, wherein the access transistor 13 constituting the memory cell 11 is formed.
The wiring 42 connects the diffusion layer 25 and the lower electrode 14 of FIG.

A ferroelectric non-volatile memory device according to a third aspect is
The ferroelectric non-volatile memory device according to claim 1 or 2, wherein the contact hole 35 connecting the diffusion layer 25 of the access transistor 13 constituting the memory cell 11 and the lower electrode 14 has the ferroelectric substance. Capacitor 12
It is characterized in that it is provided in a region other than.

A ferroelectric non-volatile memory device according to a fourth aspect is
The ferroelectric non-volatile memory device according to claim 1, wherein a contact hole 45 for the upper electrode 15 of the ferroelectric capacitor 12 is provided in a region other than the ferroelectric capacitor 12. I am trying.

[0019]

According to the ferroelectric non-volatile memory device of the present invention, the conductive layer 44 forming the lower electrode 14 of the ferroelectric capacitor 12 extends from the ferroelectric capacitor 12 and the wiring in the memory cell 11 is formed. Since it is also 42, the lower electrode 1
The conductive layer 41 other than the lower electrode 14 is different from the structure in which the conductive layer 41 other than 4 is the wiring 42 in the memory cell 11.
There is a large margin when laying out, and the width of the wiring 16 formed of the conductive layer 41 other than the lower electrode 14 can be widened.

According to another aspect of the ferroelectric non-volatile memory device of the present invention, the wiring 42 formed of the conductive layer 44 forming the lower electrode 14 of the ferroelectric capacitor 12 has the lower electrode 14 and the diffusion layer 25 of the access transistor 13. The wiring 4 formed of the conductive layer 41 other than the lower electrode 14 is connected to
It is not necessary to provide the contact hole 37 for connecting the electrode 14 of the ferroelectric capacitor 12 and the diffusion layer 25 of the access transistor 13 to the electrode 14 of the ferroelectric capacitor 12 in 2 and the contact hole 37 is opened. The ferroelectric capacitor 12 is not damaged by the etching for removing.

In the ferroelectric non-volatile memory device according to a third aspect of the present invention, the contact hole 35 connecting the diffusion layer 25 of the access transistor 13 and the lower electrode 14 of the ferroelectric capacitor 12 is provided in a region other than the ferroelectric capacitor 12. Since it is provided in the region, it is not necessary to fill the contact hole 35 with the plug 43 in order to flatten the ferroelectric capacitor 12, and the semiconductor of the diffusion layer 25 influences the ferroelectric capacitor 12 via the lower electrode 14. Can be prevented.

In the ferroelectric non-volatile memory device of the fourth aspect, the contact hole 45 for the upper electrode 15 of the ferroelectric capacitor 12 is provided in a region other than the ferroelectric capacitor 12, so that the contact hole 45 is formed. Damage caused by etching to form the ferroelectric capacitor 12
Does not occur in

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In addition, in the embodiment shown in FIG. 1, the components corresponding to the first and second conventional examples shown in FIGS.

The memory cell 11 in this embodiment is also shown in FIG.
It has the equivalent circuit shown in. In order to manufacture this embodiment, first, SiO _{2 is formed in} the element isolation region of the Si substrate 21.
The film 22 is formed, and the SiO ₂ film 23 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 22.

After that, the word line 17 is formed of the polycrystalline Si film 24 on the SiO ₂ films 23 and 22, and the diffusion layers 25 and 26 which are the source / drain of the access transistor 13 are formed on both sides of the polycrystalline Si film 24. Form in the active region. Then, the polycrystalline Si film 24 and the like are covered with the interlayer insulating film 27, and the contact hole 35 reaching the diffusion layer 25 is opened in the interlayer insulating film 27 and the like.

Next, a Pt / TiN film 4 in which a Pt film having a film thickness of 200 nm is laminated on a TiN film having a film thickness of 100 nm
4 is processed into a pattern that spreads from above the SiO ₂ film 22 to above the contact hole 35. And the film thickness is 300n
m PZT thin film 32 and Pt film 33 having a thickness of 200 nm
Are laminated, and these are processed into the pattern of the plate electrode 15. A ferroelectric thin film other than the PZT thin film 32 may be used.

Therefore, the ferroelectric capacitor 1 is formed in the overlapping portion of the Pt / TiN film 44 and the PZT thin film 32 and the Pt film 33.
2 is formed, and in the Pt / TiN film 44, the portion of the ferroelectric capacitor 12 becomes the storage node electrode 14, and the portion other than the ferroelectric capacitor 12 becomes the storage node electrode 14.
Becomes a wiring 42 for connecting the diffusion layer 25 and the diffusion layer 25. FIG.
As is clear from the above, the ferroelectric capacitor 12 is not formed on the contact hole 35.

Thereafter, the ferroelectric capacitor 12 and the like are covered with the interlayer insulating film 34, and the contact hole 3 reaching the diffusion layer 26 is formed.
6 and a contact hole 45 reaching the Pt film 33 in regions other than the ferroelectric capacitor 12 are opened in the interlayer insulating films 34 and 27. Then, the Al film 41 on the interlayer insulating film 34 forms the bit line 16 connected to the diffusion layer 26 via the contact hole 36 and the wiring 46 connected to the Pt film 33 via the contact hole 45. Further, the Al film 41 and the like are covered with a surface protective film (not shown) and the like.

In the above embodiments, the storage node electrode 1
Although the wiring 42 connecting 4 and the diffusion layer 25 is formed of the Pt / TiN film 44, the wiring connecting the region other than the diffusion layer 25 and the storage node electrode 14 is formed of the Pt / TiN film 44. Good.

[0030]

According to the ferroelectric non-volatile memory device of the present invention, the conductive layer other than the lower electrode is different from the structure in which the conductive layer other than the lower electrode of the ferroelectric capacitor is the wiring in the memory cell. Since there is a large margin in laying out the wiring and the width of the wiring formed of the conductive layer other than the lower electrode can be widened, the reliability and workability of this wiring can be improved.

In the ferroelectric non-volatile memory device of the second and fourth aspects, since the ferroelectric capacitor is not damaged by the etching for forming the contact hole, the polarization amount of the ferroelectric capacitor does not decrease. , Excellent memory retention characteristics.

In the ferroelectric non-volatile memory device according to a third aspect of the present invention, it is not necessary to fill the contact hole with a plug in order to flatten the ferroelectric capacitor, and the semiconductor of the diffusion layer is provided with the lower electrode through the ferroelectric capacitor. It is also possible to prevent the influence of the above, so that the manufacturing cost is low and the reliability is high.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, in which (a) is a side sectional view taken along the line AA of (b), (b).
Is a plan view.

FIG. 2 is an equivalent circuit diagram of a memory cell in a ferroelectric nonvolatile memory device to which the invention of the present application can be applied.

FIG. 3 shows a first conventional example of the invention of the present application, (a)
Is a side sectional view taken along the line A-A in FIG.
(B) is a plan view.

FIG. 4 shows a second conventional example of the invention of the present application, (a)
Is a side sectional view taken along the line A-A in FIG.
(B) is a plan view.

[Explanation of symbols]

11 Memory Cell 12 Ferroelectric Capacitor 13 Access Transistor 14 Storage Node Electrode 15 Plate Electrode 22 SiO ₂ Film 25 Diffusion Layer 32 PZT Thin Film 35 Contact Hole 42 Wiring 44 Pt / TiN Film 45 Contact Hole

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (4)

[Claims] 1. A ferroelectric non-volatile memory device in which a memory cell is formed by using a ferroelectric capacitor having a capacitor insulating film made of a ferroelectric substance, wherein a lower electrode of the ferroelectric capacitor is formed. A ferroelectric non-volatile memory device, wherein a conductive layer extending from the ferroelectric capacitor is a wiring in the memory cell. 2. The ferroelectric non-volatile memory device according to claim 1, wherein the wiring connects the diffusion layer of the access transistor forming the memory cell and the lower electrode. 3. A contact hole connecting a diffusion layer of an access transistor forming the memory cell and the lower electrode is formed in a region other than the ferroelectric capacitor. Item 3. A ferroelectric non-volatile memory device according to item 1 or 2. 4. The ferroelectric according to claim 1, wherein a contact hole for the upper electrode of the ferroelectric capacitor is provided in a region other than the ferroelectric capacitor. Non-volatile storage device.