JPH08203872A - Formation of contact hole and semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a method for forming contact holes of different depth in order to protect the interconnection layer on the bottom of the contact hole against etching damage and a semiconductor device having contact holes thus formed. CONSTITUTION: Etching resistant etching stopper films 104, 105, 109, 114 are formed of interlayer insulation films 6, 10, 11 on a plurality of interconnection layers 4, 5, 14, 9a. The etching stopper films 104, 105, 109, 114 are then etched until the etching stopper film is reached to make contact holes 12a-12d of different depth simultaneously and then the etching stopper film is removed. The etching stopper film is formed thicker for a shallower contact hole being made thereon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole by microfabrication in a semiconductor substrate having a plurality of wiring layers and an interlayer insulating film therebetween, and a semiconductor having the contact hole formed by the method. It relates to the device.

[0002]

2. Description of the Related Art FIGS. 4A to 4F are cross-sectional views of a conventional stacked capacitor DRAM in the word line direction, in which an interlayer insulating film is formed above a transistor cell already formed on a semiconductor substrate. FIG. 6 is a diagram showing a method of forming a capacitor cell and a contact hole that are formed as described above. In the figure, 1 is a silicon substrate which is a semiconductor substrate, 2 is an element isolation region formed on the silicon substrate 1, 3 is a transistor element region formed between the element isolation regions 2, 4 is a memory cell transistor in a memory cell The word line (wiring layer) 5 which is also used as the gate electrode of 5 is a bit line (wiring layer) above the word line 4 and orthogonal to the word line 4, and 6 is for insulating the word line 4 and the bit line 5 from each other. One interlayer insulating film,
Reference numeral 7 is a capacitor lower electrode layer, 7a is a capacitor lower electrode, 8 is a capacitor insulating film, 9 is a capacitor upper electrode layer, 9a is a capacitor upper electrode (wiring layer), 10 is a first insulating layer for insulating the bit line 5 from the capacitor lower electrode 7a. Second interlayer insulating film, 11 is third interlayer insulating film, 12a, 12b, 1
Reference numeral 2c is a contact hole, 13a, 13b and 13c are wirings, 50 is a memory cell region in which transistor cells and capacitor cells are formed, and 60 is a peripheral circuit region adjacent to the memory cell region 50. The first to third interlayer insulating films 6, 10 and 11 are formed of a silicon oxide film or the like.

Next, the operation will be described. The method of forming the capacitor cell and the contact hole is as follows. Transistor cells are formed on the silicon substrate 1, and the second interlayer insulating film 10 is formed on the transistor cells.
0 and the peripheral circuit region 60. First, the capacitor lower electrode layer 7 made of polysilicon is formed on the entire surface of the second interlayer insulating film 10 (FIG. 4).
(A)).

Next, a resist pattern (not shown) is formed on the capacitor lower electrode layer 7, the capacitor lower electrode layer 7 is etched by using this resist pattern as a mask, and the capacitor lower electrode is formed in the memory cell region 50. 7a
Are formed (FIG. 4B).

Further, a capacitor insulating film 8 and a capacitor upper electrode layer 9 are sequentially formed on the entire surface (FIG. 4).
(C)). The material of the capacitor insulating film 8 is Si _x N _y O _z.
From the relationship between the relative permittivity (about 7.5) and the required capacitance, the thickness of the capacitor insulating film 8 is 40 to 20.
Set to 0 angstrom. Like the capacitor lower electrode layer 7, the capacitor upper electrode layer 9 is made of polysilicon and has a thickness of 500 to 50,000 angstroms.

A resist pattern (not shown) is formed on the capacitor upper electrode layer 9, and the capacitor upper electrode layer 9 is etched by using this resist pattern as a mask to remove the capacitor upper electrode layer 9 in the peripheral circuit region 60. hand,
A capacitor upper electrode 9a is formed (FIG. 4 (d)). In this case, since the capacitor insulating film 8 is as thin as 40 to 200 angstrom as described above with the miniaturization and large capacity of the DRAM, the capacitor insulating film 8 is also etched when the capacitor upper electrode layer 9 is etched.

Next, a third interlayer insulating film 11 made of a silicon oxide film is formed on the entire surface and is etched by using a resist pattern (not shown) formed thereon as a mask to form contact holes 12a, 12b, 12c. Are formed (FIG. 4E). That is, the contact hole 12a is formed by etching through the third interlayer insulating film 11 until reaching the capacitor upper electrode 9a.
b further penetrates the second interlayer insulating film 10 and passes through the bit line 5
Contact hole 12c is further etched to reach the word line 4 through the first interlayer insulating film 6, and other contact holes (not shown) are further formed. Etching is performed until the source / drain regions (not shown) of the silicon substrate 1 are reached. At this time, since the contact holes 12a, 12b, 12c have different depths, the surface of the capacitor upper electrode 9a is deeper even after the shallowest contact hole 12a reaches the capacitor upper electrode 9a. Exposed to over-etch due to apertures such as 12c. The surfaces of the bit lines 5 and the word lines 4 in the contact holes 12b and 12c are similarly exposed to overetching.

Finally, the contact holes 12a, 12
The wiring 13 is formed on the third interlayer insulating film 11 including b and 12c.
a, 13b, 13c are formed respectively (see FIG. 4).
(F)).

[0009]

Since the conventional contact hole forming method and semiconductor device are constructed as described above, the contact holes 12a, 12 having different depths are formed.
When the holes b, 12c are opened by etching, the shallower contact holes 12a, 12b, 12c are formed at the bottom of the shallower contact holes 12a, 12b, 12c because of the deeper contact holes 12b, 12c. There was a problem that the capacitor upper electrode 9a, the bit line 5 and the word line 4 in the above were exposed to over-etching.

The present invention has been made in order to solve the above-mentioned problems, and when a contact hole having a different depth is opened by etching, etching damage of the wiring layer at the bottom of the contact hole is prevented. An object of the present invention is to obtain a method for forming a contact hole and a semiconductor device having a contact hole formed by the method.

[0011]

According to a first aspect of the present invention, there is provided a method of forming a contact hole, wherein an etching stopper film having an etching resistance higher than that of an interlayer insulating film is formed on each of a plurality of wiring layers, and each etching is performed. The etching stopper film is removed after a plurality of contact holes having different depths are formed by etching until reaching the stopper film.

In the method of forming a contact hole according to the second aspect of the present invention, the etching stopper film is made thicker as the contact hole formed thereon is shallower.

A semiconductor device according to a third aspect of the present invention has a contact hole formed by the method of forming a contact hole according to the first aspect.

[0014]

According to the method of forming a contact hole in the first aspect of the invention, when a plurality of contact holes having different depths are formed by etching, the etching stops when reaching the etching stopper film formed on the wiring layer, Do not overetch the wiring layer.

In the method of forming the contact hole according to the second aspect of the present invention, the etching stopper film corresponding to the shallow contact hole is exposed to etching longer than necessary, but since the film thickness is large, the wiring layer is not over-etched.

In the semiconductor device according to the third aspect of the present invention, the etching is stopped up to the etching stopper film on the wiring layer, and the wiring layer is not over-etched.

[0017]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1A to 1F are sectional views in the word line direction of a stacked capacitor type DRAM according to a first embodiment of the present invention, showing a method of forming a contact hole in a semiconductor substrate in which transistor cells and capacitor cells are formed. FIG. The corresponding parts shown in FIGS. 4 (a) to 4 (f), which are prior arts, are designated by the same reference numerals, and the description thereof will be omitted.
In the figure, 12a to 12d are contact holes, 13
Is a conductor film, 13a to 13d are wirings, 14 is a source / drain region (wiring layer) of a transistor in the peripheral circuit region 60, 15 is a resist, 104 is a word line etching stopper formed on the word line 4, and 105 Is a bit line etching stopper formed on the bit line 5, 109
Is a capacitor upper electrode etching stopper formed on the capacitor upper electrode 9a, 114 is a source / drain region etching stopper formed on the source / drain region 14, and 150a to 150d are etching stopper removing portions. The bit line 5 and the capacitor lower electrode 7a are electrically connected to the source / drain regions 14 of the memory cell transistor through contact holes (not shown).

The source / drain region etching stopper 114, the word line etching stopper 104, the bit line etching stopper 105, and the capacitor upper electrode etching stopper 109 are thicker than the upper layer etching stopper. That is, the source / drain region etching stopper 114 has the smallest film thickness, the word line etching stopper 104 and the bit line etching stopper 105 have the largest film thickness, and the capacitor upper electrode etching stopper 109 has the largest film thickness.

Next, the operation will be described. Transistor cells and capacitor cells are formed, and the source / drain region etching stopper 114, the word line etching stopper 104, and the word line etching stopper 104 are formed on the source / drain region 14, the word line 4, the bit line 5, and the capacitor upper electrode 9a, respectively.
A third interlayer insulating film 11 is formed on the entire surface of the semiconductor substrate (FIG. 1A) on which the bit line etching stopper 105 and the capacitor upper electrode etching stopper 109 are formed, and photolithography is performed (FIG. 1B). ).

Etching is performed using the resist 15 as a mask to open a hole in the interlayer insulating film 11. The opening penetrates the third interlayer insulating film 11 and reaches the capacitor upper electrode etching stopper 109 to form a contact hole 12a. Further, etching is advanced to penetrate the second interlayer insulating film 10 and a bit line etching stopper. A contact hole 12b is formed by reaching 105, a contact hole 12c is formed by penetrating the interlayer insulating film 6 and reaching the word line etching stopper 104, and a source / drain region etching stopper 114 is further reached. Holes 12d are formed (Fig. 1
(C)). At this time, even after the capacitor upper electrode etching stopper 109 is opened to the surface thereof and the contact hole 12a is formed, it is overetched until the opening reaches the source / drain region etching stopper 114 and the contact hole 12d is formed. Capacitor upper electrode etching stopper 1 as it is exposed to etching
The film thickness of 09 is the largest. For the same reason, the bit line etching stopper 105 has a larger film thickness than the word line etching stopper 104.
04 is a source / drain region etching stopper 114
The film thickness is thicker. Such an etching stopper 11
The surfaces of the source / drain region 14, the word line 4, the bit line 5 and the capacitor upper electrode 9a are not over-etched by 4, 104, 105 and 109.

Etching stoppers 109, 1 by dry etching, sputtering or the like using the resist 15 or the first to third interlayer insulating films 6, 10, 11 as masks.
05, 104, 114 are removed, and etching stopper removal portions 150a, 150b, 150c, 150d are removed.
Is formed. As a result, the capacitor upper electrode 9a, the bit line 5, the word line 4, and the source / drain region 14 under the etching stopper are exposed (FIG. 1D). In the step of removing the etching stopper, if the film thickness of the etching stopper varies, it may be exposed to over-etching due to the difference in the film thickness. It is desirable that the etching stoppers have the same film thickness.

A conductor film 13 to be an upper wiring is formed on the entire surface (FIG. 1E), and is processed using a resist as a mask to form wirings 13a, 13d, 13c and 13d (FIG. 1).
(F)).

Through the above steps, a high quality connection between the upper wiring and the lower wiring can be obtained.

Embodiment 2 FIG. 2 is a sectional view showing a method of removing an etching stopper according to Embodiment 2 of the present invention.
1 corresponding to those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In the figure, an etching stopper 114,
The portions 104, 105 and 109 are removed by wet etching. Since it is wet etching, the resist 15 shown in FIG. 1B is unnecessary. Further, since it is removed by wet etching, there is no plasma damage to the source / drain region 14, the word line 4, the bit line 5 and the capacitor upper electrode 9a. Therefore, the contact holes 12a, 1
Etching stopper 11 after opening 2b, 12c, 12d
When excluding 4, 104, 105 and 109, it is not necessary to take care so that the film thicknesses of these etching stoppers are equal in order to prevent overetching.

Through the above steps, a high quality connection between the upper wiring and the lower wiring can be obtained.

Embodiment 3 FIG. 3 (a) and 3 (b) are sectional views in the bit line direction of a transistor according to a third embodiment of the present invention, which shows a method of forming a source / drain region etching stopper. 1 corresponding to those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted. In the figure, 31 is a gate oxide film, 32 is a gate electrode overlay film formed on the word line 4 which is a gate electrode, and 33 is a sidewall. The gate electrode overlay film 32 is a film having the same etching characteristics as the etching stopper.

A source / drain region etching stopper 11 is formed on the entire surface of the transistor shown in FIG.
4 is formed (FIG. 3B).

Here, the film thickness of the source / drain region etching stopper 114 is the film thickness C. The film thickness of the word line etching stopper 104 shown in FIG.
It is the sum of the film thickness A of the gate electrode overlay film 32 corresponding to the etching stopper shown in (b) and the film thickness B of the source / drain region etching stopper 114.

Thereafter, in the same manner as in Example 1, the first interlayer insulating film 6, the bit line 5 and the bit line etching stopper 105, the second interlayer insulating film 10, the capacitor lower electrode 7a, the insulating film 8 and the capacitor upper part. By sequentially forming the electrode 9a and the capacitor upper electrode etching stopper 109, a semiconductor device having a structure similar to that of FIG. 1A is obtained.

In FIG. 1A, the word line etching stopper 104, the bit line etching stopper 105,
The capacitor upper electrode etching stopper 109 is formed using the same mask when processing the wiring layers of the word line, the bit line and the capacitor upper electrode, respectively, using the mask. Source / drain region etching stopper 11
No mask is required, although only 4 is not formed with the same mask.

Through the above steps, it is possible to obtain a high quality connection between the upper wiring and the lower wiring without increasing the number of masks.

[0033]

As described above, according to the first aspect of the invention, the etching stopper films are formed on the plurality of wiring layers, and the contact holes are formed by etching until the etching stopper films are reached. Since it is configured, the etching is stopped by the etching stopper film, and there is an effect that the etching damage of the wiring layer can be prevented.

According to the second aspect of the present invention, the film thickness of the etching stopper film is thicker as the contact hole formed thereon is shallower. Therefore, the shallower the contact hole is, the longer it is exposed to etching, but the film thickness is longer. Since the thickness is thick, there is an effect that the etching damage of the wiring layer can be more surely prevented.

According to the third aspect of the present invention, since the etching is stopped up to the etching stopper film on the wiring layer, there is an effect that the wiring layer is not damaged by etching.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method of forming a contact hole according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a method of removing an etching stopper according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a method of forming a source / drain region etching stopper according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a conventional method of forming a contact hole.

[Explanation of symbols]

1 silicon substrate (semiconductor substrate), 4 word lines (wiring layer), 5 bit lines (wiring layer), 6 first interlayer insulating film, 9a capacitor upper electrode (wiring layer), 10 second interlayer insulating film, 12a ~ 12d contact hole, 14
Source / drain region (wiring layer), 104 word line etching stopper, 105 bit line etching stopper, 109 capacitor upper electrode etching stopper, 114 source / drain region etching stopper.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8242 H01L 21/90 B 7735-4M 27/10 681 A 7735-4M 681 B

Claims (3)

[Claims] 1. A method for forming a contact hole in a semiconductor substrate having a plurality of wiring layers and an interlayer insulating film between the plurality of wiring layers, wherein the plurality of wiring layers have etching resistance higher than that of the interlayer insulating film. A step of forming a plurality of etching stopper films respectively, a step of simultaneously forming a plurality of contact holes having different depths reaching the plurality of etching stopper films through the interlayer insulating film by etching, and after the contact hole forming step And a step of removing the etching stopper film. 2. The film thickness of the etching stopper film is larger as the depth of the contact hole formed on the etching stopper film is shallower.
A method for forming a contact hole as described above. 3. A semiconductor device having a contact hole formed by the method for forming a contact hole according to claim 1.