JPH08161834A - Encoder - Google Patents

Abstract

PURPOSE: To relieve the restriction on processing time for run length detection of modulated output by comparing the max. run lengths of the data to be modulated, outputting the result of the comparison to apply the smaller max. run length and outputting the result of the comparison as a selection signal after inversion or non-inversion. CONSTITUTION: A 0 is added as a control bit by a '0' adding circuit 11 to the inputted data to be modulated and this data is inputted to a precoder 12. This precoder 12 converts the input to I-NRZI. The precoder 12 executes conversion by normally using 00 as the final bit of the modulated output of the previous word. The converted output of the precoder 12 is inputted via a bit inversion circuit 13 to a holding circuit 10. The circuit 13 outputs the respective inputted bits to the holding circuit 10 after inversion or non-inversion in accordance with the modulated output and the output of a determining circuit 15. A run length detecting circuit 14 determines the max. length of the present word for 1 and 0 of the control bit in accordance with the modulated outputs from the precoder 12 and the circuit 10 and outputs the selection signal to select the control bit to apply the max. length to the determining circuit 15, thereby controlling the bit inversion processing of the circuit 13.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder suitable for a 24-25 modulator and the like.

[0002]

2. Description of the Related Art In recent years, with the progress of digital technology, image information has been digitally processed, and, for example, a digital video tape recorder (hereinafter also referred to as VTR) has been developed. In the transmission and recording of digital signals, it is difficult to transmit or record the signal components in the low frequency region with high efficiency. Therefore, modulation to a balanced code for suppressing the signal components in the direct current and low frequency regions, That is, DC-free modulation is often used.

In DC-free modulation, the charge accumulation value (DSV) (Digital Sum Valu) of a recording modulation signal is generally used.
The absolute value of e) is made small. That is, in order to reduce the absolute value of the DSV by allocating a plurality of codes having different CDS (Code Digital Sum) (indicating the difference between the number “0” and “1” of the recorded waveform of the code) to one code. DC free is achieved by selecting the code of.

By the way, in the VTR, tracking control is performed so that the magnetic head traces the recording track surely. In this case, it may be possible to adopt a tracking method using a pilot signal in order to achieve high density recording. The pilot signal is reproduced from adjacent tracks having different azimuth angles. Therefore,
As the frequency of the pilot signal, a low frequency band in which the azimuth loss effect is relatively small is selected. When the pilot method is adopted in the analog VTR, the FM-modulated luminance signal and the low-frequency conversion color signal, which are the main signals, do not have a spectrum in the low frequency band, so that the interference by the pilot signal does not occur. However, since the occupied band of the main signal is not limited in the digital VTR, the pilot signal and the main signal cannot be frequency-multiplexed independently of each other, and they become mutual interference components.

Therefore, the digital VTR employs a modulation method in which a low frequency component (hereinafter, referred to as a digital pilot tone) which becomes a pilot signal is generated by intentionally varying the DSV of a recording modulation signal. This modulation method is effective because the spectrum of the main signal itself is concentrated in a specific low frequency band, other signals are not particularly generated, and an interference wave with respect to the main signal is not multiplexed. As for a conventional encoder for generating a digital pilot tone for such tracking, Japanese Patent Laid-Open No. 5-2840 adopting 24-25 modulation.
There is one disclosed in Japanese Patent No. 34.

In magnetic recording, the output characteristics deteriorate as the recording frequency increases. Therefore, in digital recording, it is necessary to increase the minimum magnetization reversal interval, that is, to convert into a modulation signal having a large minimum pulse width. Further, similarly, it is impossible to obtain a sufficient output for the components in the DC and low frequency regions. Therefore, it is necessary to limit the run length (the number of consecutive bits of the same polarity) of the recording signal to reduce the maximum pulse width of the modulation signal and obtain a DC-free characteristic in which not only the DC component but also the entire low frequency component is suppressed. is there. By limiting the modulation code runs, high density recording, azimuth recording and overwriting recording are possible.

FIG. 5 is a block diagram showing a conventional coding apparatus provided with a run length detecting circuit for detecting such run length, and shows an example in which 24-25 modulation is adopted.

The 24-25 modulation method shown in this proposal is 2
A digital pilot tone is generated by adding 1 bit to a 4-bit input data string to make it 25 bits. By appropriately setting 1 bit to be added (hereinafter referred to as a control bit), three kinds of frequencies can be obtained. f
The digital pilot tones of 0, f1 and f2 are generated and the run length is prevented from exceeding the set value.

A "0" adding circuit 1 adds "0" as a control bit to the input modulated data. Further, "1" is added as a control bit to the modulated data by the "1" adding circuit 2. The output of the "0" addition circuit 1 and the output of the "1" addition circuit 2 are the precoders 3 and 4, respectively.
To perform an I-NRZI (interleaved NRZI) conversion for obtaining an exclusive OR of bits around two clocks. For I-NRZI conversion for a given word,
I need the last bit of the modulation output for the previous word,
The precoders 2 and 3 perform I-NRZI conversion based on the modulated output of the previous word from the holding circuit 10.

The outputs of the precoders 3 and 4 are given to the selection circuit 9, and the selection circuit 9 is controlled by the selection signal from the decision circuit 8 to select either one of the outputs of the precoders 3 and 4 to control bits. For example, a modulated output with "0" added is output, or a modulated output with "1" added as a control bit is output. The holding circuit 10 holds the output of the selection circuit 9 and outputs a modulated output in word units.

The decision circuit 8 decides whether to use "1" or "0" as a control bit based on the maximum run length and an external factor that determines the frequency component. The maximum run length is detected by the run length detection circuits 5 and 6. Run length detection circuit 5, 6
To the output of the precoders 3 and 4, respectively, and the run length detection circuits 5 and 6 obtain the maximum run length. In this case, in order to detect the run length extending over the modulation output of the previous word and the modulation output of the current word, the run length up to the modulation output end of the previous word is supplied from the holding circuit 7. The run length detection circuits 5 and 6 detect the maximum run length based on the output of the holding circuit 7 and the output of the precoders 3 and 4, and output it to the decision circuit 8. Also,
The run length detection circuits 5 and 6 also obtain a run length from the last bit of the current word to the first bit side (hereinafter, also referred to as cumulative run length) and output it to the decision circuit 8 in order to detect the run length of the next word. .

The decision circuit 8 is a run length detection circuit 5, 6
If none of the maximum run lengths exceeds the set value N, a selection signal for determining the control bit based on an external factor is output, and if the maximum run length exceeds the set value N, It outputs a selection signal for selecting a modulation output with a maximum run length that is small. The cumulative run length output from the circuit selected by the determination circuit 8 among the run length detection circuits 5 and 6 is given to the holding circuit 7,
The holding circuit 7 outputs to the run length detection circuits 5 and 6 when the run length of the next word is detected.

As described above, the apparatus of FIG. 5 obtains the run length of the modulation output for each word and determines the control bit based on the external factor, and the run length of the modulation output becomes equal to or more than the predetermined set value N. In this case, the modulation output that reduces the run length is selected. This controls the frequency component of the modulation output to generate a predetermined pilot tone, and limits the run length to obtain a good magnetization characteristic. Is getting

By the way, as described above, the final bit of the modulation output of the previous word is necessary for the I-NRZI conversion in the precoders 3 and 4, and the precoders 3 and 4 need to output the last bit of the modulation output of the previous word. No conversion output can be obtained. On the other hand, I-N for the modulated data of the next word
It is necessary to output the modulation output before the RZI conversion processing, and when the run length detection is started after the modulation output of the previous word is determined and the conversion outputs are output from the precoders 3 and 4, the run length detection circuit 5 , 6 has a problem that the processing time is significantly restricted.

[0015]

As described above, in the above-described conventional coding apparatus, since the modulation processing in the precoder cannot be performed until the modulation output of the previous word is determined, the run length detection is performed. There was a problem that the processing time of was restricted.

It is an object of the present invention to provide an encoding device capable of relaxing the restriction on the processing time for detecting the run length.

[Structure of the Invention]

A coding device according to the present invention adds a control bit for adding a control bit of a predetermined polarity of 1 bit for each L bits (L is a positive integer) of input modulated data. And a modulation means for performing I-NRZI conversion on the output of the control bit adding means assuming that 1 bit of a predetermined polarity is added to the head of the control bit adding means, and outputting a conversion output in word units of (L + 1) bits. A first bit inverting means for inverting or not inverting an inverted bit group that inverts a bit when the polarity of the control bit among the bits of the conversion output is changed, and the control bit of each bit of the conversion output Has a second bit inverting means for inverting or non-inverting a common bit group that does not bit-invert even if the polarity of is changed, and modulates by inverting or non-inverting each bit of the conversion output. Of the modulation output of the preceding word and the final bit of the modulation output of the previous word and the modulation output of the current word. The first run length detecting means for detecting the maximum run length of the current word when the first bit has the same polarity, the last bit of the modulation output of the previous word and the first bit of the modulation output of the current word are Second run length detecting means for detecting the maximum run length of the current word when the polarities are different; maximum run length detected by the first run length detecting means and the second run length detecting means Of the first or second run length detecting means for giving a smaller maximum run length by comparing the maximum run length detected by Comparing means for outputting the comparison result, inverting means for inverting or non-inverting the comparison result based on the final bit of the modulation output after the modulation output of the previous word is determined, and outputting as the selection signal, and the selection signal And a deciding means for giving a signal for controlling the inversion or non-inversion of the inversion bit group to the bit inversion means based on the above.

[0018]

In the present invention, the control bit adding means adds a control bit having a predetermined polarity to the modulated data, and the modulating means performs I-NRZI conversion on the assumption that one bit having a predetermined polarity is added to the head. Before the modulation output of the previous word is determined, the first and second run length detecting means respectively determine whether the last bit of the modulation output of the previous word and the first bit of the modulation output of the current word are the same, or As a difference, the maximum run length is calculated. These maximum run lengths are compared by the comparison means, and the comparison means outputs the comparison result indicating the first or second run length detection means which gives a small maximum run length. When the modulation output of the previous word is determined, the inverting means inverts or non-inverts the comparison result based on this modulation output and outputs it as a selection signal. The determining means controls the first bit inverting means based on the selection signal. In this way, the run length of the modulation output is reduced.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an encoding device according to the present invention.

The modulated data to be inputted is a "0" addition circuit.
Give to 11. The "0" adding circuit 11 adds "0" as a control bit to the modulated data and gives it to the precoder 12. The precoder 12 I-NRZI converts the output of the "0" addition circuit 1. I-NRZI conversion for a given word requires the last bit of the modulated output for the previous word,
The precoder 12 always performs conversion by using "00" as the final bit of the modulation output of the previous word.

The conversion output of the precoder 12 is a bit inverting circuit.
It is supplied to the holding circuit 10 via 13. Bit inversion circuit 13
Is configured to invert or non-invert each bit of the converted output of the precoder 12 based on the modulation output and the output of the decision circuit 15 described later, and output the inverted bit to the holding circuit 10. The holding circuit 10 holds the output of the bit inverting circuit 13 and outputs it as a modulation output in word units.
The last bit of the holding circuit 10 is output to the bit inversion circuit 13 and the run length detection circuit 14. Table 1 below is for explaining the operation of the bit inverting circuit 13.

[0022]

[Table 1] Now, as shown in Table 1, the input 24-bit modulated data is “0000000000000000000000”.
Table 1 shows the I-NRZI conversion result when the control bit to be added is "0" or "1" and the last bit of the previous word is "0" or "1". When "1" of the I-NRZI conversion result is associated with a positive level signal and "0" is associated with a negative level signal, the last bit and the control bit of the previous word are "0", "." In the case of 0 "(hereinafter referred to as the case of (a)), the DSV of the conversion result gradually increases to" 1 "," 1 ".
In this case (hereinafter referred to as the case of (d)), the DSV of the conversion result gradually decreases. Similarly, when the last bit and control bit of the previous word are “0” and “1” (hereinafter,
In the case of (b)) and in the cases of "1" and "0" (hereinafter referred to as the case of (c)), the DSV of the conversion result does not change. That is, the DSV can be controlled by appropriately setting the control bit according to the last bit of the previous word, the digital pilot tone of the predetermined frequency is generated in the I-NRZI conversion result, and the maximum run length is set to the predetermined value. It can be limited to a value that does not exceed the set value N.

As is clear from Table 1 above, in the case of (a), that is, when the last bit of the previous word is "0" and the control bit is also "0", the modulated data is directly used as the conversion result. Is output. In the case of (b), I-NRZ
The I conversion result is the inverted data of every other bit of the modulated data. When each bit inverted by the control bit “1” in the bit string of the I-NRZI conversion result is an inverted bit group, as is clear from the comparison between the case (c) and the case (d) in Table 1, Last bit of word is "1"
Even in the case of, it can be seen that each bit of the inversion bit group is inverted when the control bit is “0” and when it is “1”.

That is, the control bit is "1" or "0".
Instead of adding "0", the same modulation output can be obtained even if "0" is always added as a control bit and the inverted bit group is inverted or non-inverted. For this reason, the "0" addition circuit 11 always adds "0" as the control bit, and the bit inversion circuit
13 reverses or reverses the inverted bit group,
The same modulation output as when "1" or "0" is added as a control bit is obtained.

If each bit other than the inverted bit group is a common bit group, when the last bit of the previous word is "0", the common bit group has the same polarity as the modulated data and is "1". In some cases, it will be the inverted version of the modulated data. For this reason, the precoder 12 assumes that the last bit of the previous word is always "00".
Performing I conversion, the bit inverting circuit 13 inverts or non-inverts the common bit group based on the final bit of the actual modulation output. That is, the inversion or non-inversion processing for the common bit group of the bit inversion circuit 13 corresponds to the last bit of the previous word, and the last bit of the modulation output of the previous word from the holding circuit 10 is “0”. The bit inversion circuit 13 outputs the common bit group as it is to “1”
, The common bit group is inverted and output.

The bit inversion circuit 13 is controlled by the decision circuit 15 to invert or non-invert the inverted bit group of the precoder 12. The run length detection circuit 14 determines the maximum run length of the current word when the control bit is “1” and the control bit is “0” based on the conversion output of the precoder 12 and the modulation output from the holding circuit 10. Of the present word and outputs a selection signal for selecting a control bit giving a small maximum run length to the decision circuit 15, and the maximum run length based on the selected control bit sets a set value N. A control signal indicating whether or not to exceed is output to the decision circuit 15. The decision circuit 15 controls bit inversion processing for the inversion bit group of the bit inversion circuit 13 based on the selection signal and the control signal from the run length detection circuit 14 and an external factor. In this embodiment, the run length detection circuit
The 14 starts the run length detection before the modulation output of the previous word is determined.

FIG. 2 is a block diagram showing a specific configuration of the run length detection circuit 14 shown in FIG.

The run length detection circuit 14 of this embodiment always performs the run length calculation of three patterns, which will be described later, regardless of the modulation output of the previous word. The run length detection circuit 14 is
The calculation operation is started before the modulation output of the previous word is determined, and after the modulation output of the previous word is determined,
Two of the run lengths of the pattern are selected, and the selection signal is obtained by comparing the magnitudes of the two selected run lengths.

That is, in FIG. 2, the conversion output from the precoder 12 is given to the exclusive OR circuit 21. The exclusive-OR circuit 21 performs an exclusive-OR operation on the bits before and after one bit of the bit string for each word. Run length detection circuit 14
Must determine the number of consecutive "0" s and the number of consecutive "1" s. However, the run-length detection circuit 14 may detect the maximum value of the run-length regardless of whether it is "0" or "1". Therefore, the run length detection circuit 14 is adapted to perform an exclusive OR operation. The exclusive OR operation result is "0" if the polarities of the preceding and following bits are the same, and is "1" for each different. That is, the number of consecutive "0" s of the exclusive OR operation result + 1 becomes the run length of "0" or "1". Assuming that one word length of the converted output is (L + 1) bits, the output of the exclusive OR operation circuit 21 is L bits for each word.

By the way, when the last bit of the modulation output of the previous word and the head bit (control bit) of the current word have the same polarity, it is necessary to use the run length up to the previous word to detect the run length. Now, it is assumed that one word has (L + 1) bits and L = 24. In this case, FIG. 3 shows the modulation output of the previous word as “000
0000000000000000000000 "and the modulated data of the current word is" 1010101010 ".
FIG. 10 is an explanatory diagram showing a modulation output having the longest run length by setting 1010101001010 ″.
FIG. 3A shows the case where the control bit is “0”.
(B) shows the case where the control bit is "1".

In FIG. 3, a shows the number of bits up to the pre-modulation output necessary for detecting the run length of the current word. Now, it is assumed that all bits of the previous modulation output are "0" and the previous modulation output is also "0" continuous in the opposite direction from the last bit. In this case, the control bit is "1"
By adding "," continuous "0" s can be prevented and the maximum run length in the current word can be reduced. Table 2 below shows the relationship between a and the maximum run length.

[0032]

[Table 2] As shown in Table 2, when a is L-1 (= 23), the maximum run length is L when the control bit is "0" and L + 1 when the control bit is "1". That is,
In this case, the maximum run length can be suppressed to L (= 24) by setting the control bit to "0".
When a is L, the maximum run length is L + 1 regardless of whether the control bit is "0" or "1" as shown in Table 2 above. When a is L + 1, the control bit is "0" and the maximum run length is L + 2.
And becomes "L + 1" at "1". That is, in this case,
By setting the control bit to "1", the maximum run length can be suppressed to L + 1. Furthermore, a is L + 2
In this case, as is clear from Table 2 above, the maximum run length can be suppressed to L + 1 by setting the control bit to "1". Similarly, when a is L or more, the maximum run length is L + 1. In other words, in FIG. 3, a is unlimitedly increased, but in reality, the maximum run length does not become a value larger than L + 1, so by setting L + 1 as a, the maximum run length of the current word can be accurately set. You can ask.

FIG. 4 is an explanatory diagram for explaining the relationship between the last bit and head bit (control bit) of the modulation output and the range required for calculating the maximum run length. In FIG. 4, first0 and first1 respectively indicate the first bit (control bit) of the current word or the previous word, and last1 and last2 respectively indicate the last word or the last bit two words before. Also,
The arrow indicates the range required to calculate the maximum run length.

As described above, in order to detect the maximum run length of the current word, it is only necessary to consider up to the modulation output two words before, so the possible patterns are the four patterns of FIG. That is, in FIG. 4A, first0 = last1, first1 = last
If it is 2. In addition, in FIG. 4B, first0 ≠ last
1 and first1 = last2, and FIG.
This is the case where rst0 = last1 and first1 ≠ last2, as shown in FIG.
(D) is a case where first0 ≠ last1 and first1 ≠ last2. Of these four patterns (hereinafter referred to as A pattern to D pattern, respectively), the B pattern and D pattern are
As shown by the arrows in FIGS. 4B and 4D, the required ranges are the same. Therefore, the maximum run length may be detected only for the A, B, and C patterns.

Before the modulation output of the previous word is determined, the patterns considered as the modulation output of the current word are, as shown in Table 1 above, two patterns based on the last bit of the modulation output of the previous word and control. There are 4 patterns in total, 2 patterns based on the polarities of the bits. In the tables (3) and (4) below, the modulated data is "011010011".
In the case of 100100001010011 ", the relationship between the modulation output of four patterns and the exclusive OR operation result is shown.

[0036]

[Table 3]

[Table 4] The cases of Tables 4 (a) to 4 (d) correspond to the cases of Table 3 (a) to (d), respectively. As is clear from the comparison between cases (a) and (d) and cases (b) and (c) in Tables 3 and 4, the polarity of the last bit of the previous modulation output and the first bit of the current modulation output (control It can be seen that the exclusive OR operation results are aggregated into two patterns depending on whether or not the polarities of (bits) are the same, and that these two patterns have a bit inversion relationship with each other.

In FIG. 2, the output of the exclusive OR circuit 21 is supplied to the bit inverting circuit 25 and also to the maximum run length detection circuits 22 and 23. The output of the exclusive OR circuit 21 corresponds to the case of (a) in Tables 3 and 4 above. Further, as shown in Table 4, the run length in this case is the same as the run length in the case of (d). Therefore, in the case of (a), that is, when the last bit of the modulation output of the previous word is “0” and the control bit is “0”, the run length is detected, and the cases of (a) and (d) in Table 4 are detected. When the modulation output of is selected, when the final bit is fixed, "0" is selected as the control bit when the final bit is "0", and "1" is selected as the control bit when the final bit is "1". You can select it.

The patterns considered as the cases (a) and (d) of Table 4 are the A pattern or the C pattern of FIG. The maximum run length detection circuit 22 detects the maximum run length of the A pattern, and the maximum run length detection circuit 23 detects the maximum run length of the C pattern. The maximum run length detection circuits 22 and 23 are provided with run lengths from holding circuits 26 and 27, which will be described later, to pre-modulation outputs, respectively, as initial values, add 1 to these initial values, and execute exclusive OR circuit 21. The output is used to detect the maximum run length of the L-bit current word and select circuit 28
Output to. Further, the maximum run length detection circuit 22 detects the run length from the last bit of the current word toward the leading bit and outputs it to the holding circuit 26 as an initial value of the maximum run length of the next word.

The bit inversion circuit 25 is an exclusive OR circuit 21.
Maximum run length detection circuit 24
Output to. As a result, the maximum run length detection circuit 24
Thus, it becomes possible to detect the maximum run length in the cases of (b) and (c) in Table 4 above. (B) in Table 4 above,
In the case of (c), that is, when the last bit of the pre-modulation output and the control bit of the current word have different polarities, FIG.
As shown in FIG. 4, the patterns required to detect the maximum run length are the B and D patterns in FIG. That is, in this case, it is not necessary to consider the run length of the previous word. The maximum run length detection circuit 24 detects the maximum run length of the bit-inverted exclusive OR result and outputs it to the comparison circuit 29. Further, the maximum run length detection circuit 24 detects the run length from the last bit of the current word to the head bit direction and outputs it to the holding circuit 27 as the initial value of the maximum run length of the next word.

The holding circuits 26 and 27 respectively have A pattern or C pattern.
The run length up to the previous word for detecting the maximum run length of the pattern is held, and when the maximum run length of the next word is detected, it is supplied to the maximum run length detection circuits 22 and 23 as an initial value.

The selection circuit 28 uses the last bit last two words last
2 and the first bit first1 of the previous word are given and both have the same polarity, the maximum run length of the A pattern from the maximum run length detection circuit 22 is compared with the comparison circuit 29.
When the polarities are different, the maximum run length of the C pattern from the maximum run length detection circuit 23 is given to the comparison circuit 29.

The comparison circuit 29 compares the maximum run length of the A pattern or C pattern from the selection circuit 28 with the maximum run length of the B and D patterns from the maximum run length detection circuit 24, and determines which maximum run length. Signal indicating whether the modulation output in the cases of (a) and (d) in Table 4 or the modulation output in the cases of (b) and (c) in Table 4 is selected. Is given to the inverting circuit 30. The comparison circuit 29 also outputs a control signal indicating whether or not the input maximum run length exceeds the set value N. The inverting circuit 30 is
After the modulation output of the previous word is confirmed, if the last bit last1 of the modulation output of the previous word is input and last1 is “0”, the output of the comparison circuit 29 is directly output as the selection signal and last1 is set to “1”. If it is ", the comparison circuit 29
The output of is inverted and output as a selection signal.

In FIG. 1, the selection signal and the control signal from the run length detection circuit 14 are given to the decision circuit 15. When the control signal indicates that the maximum run length does not exceed the set value N, the determining circuit 15 inverts or inverts the inversion bit group of the bit inversion circuit 13 based on an external factor that determines the frequency component. Control the inversion process. When the control signal indicates that the maximum run length exceeds the set value N, the decision circuit 15 controls the inversion or non-inversion process for the inversion bit group of the bit inversion circuit 13 based on the selection signal. It is like this.

Next, the operation of the embodiment thus constructed will be described.

The modulated data to be inputted is a "0" addition circuit.
Give to 11. The "0" addition circuit 11 adds "0" to the modulated data as a control bit and gives it to the precoder 12, and the precoder 12 outputs "00" as the final bit of the modulation output of the previous word.
, The output of the “0” addition circuit 11 is I-NR.
ZI convert. The converted output is given to the bit inversion circuit 13 and the run length detection circuit 14.

Before the modulation output of the previous word is confirmed,
The bit inversion circuit 13 does not perform inversion or non-inversion processing.
On the other hand, the run length detection circuit 14 starts calculation of the maximum run length.

When the modulation output of the previous word is not fixed, the four patterns shown in Tables 3 and 4 are considered as the modulation output for the input modulated data. Of these four patterns, the run lengths in case (a) and case (d) are the same, and in case (b) and case (c).
The run lengths also match. Therefore, the run length detection circuit 14 has the cases (a) and (d) and (b),
The maximum run length is obtained for the two patterns in the case of (c).

That is, the converted output of the precoder 12 is given to the exclusive OR circuit 21. The exclusive OR circuit 21 calculates an exclusive OR between the preceding and following bits. The number of consecutive "0" s of the exclusive OR operation result + 1 indicates the run length. In addition,
Since "0" is used as the last bit of the previous word and the control bit of the current word by the "0" addition circuit 11 and the precoder 12, the output of the exclusive OR circuit 21 is (a) in Tables 3 and 4 above. ).

The exclusive OR operation result is output to the maximum run length detection circuits 22 and 23 and the bit inversion circuit 25. As shown in Table 4 above, in the cases of (a) and (d) and (b),
In the case of (c), since the exclusive OR operation result is the bit-inverted, the bit inversion circuit 25 bit-inverts the output of the exclusive OR circuit 21 to set The exclusive OR operation result corresponding to the cases of b) and (c) is obtained.

In the case of (b) and (c) in Tables 3 and 4 above,
This corresponds to the B and D patterns of FIG. 4, and it is sufficient to consider only the run length of the current word, and the maximum run length detection circuit 24
Determines the maximum run length from the output of the bit inversion circuit 25, detects the run length from the last bit of the current word to the leading bit direction, and supplies it to the holding circuit 27 as the initial value of the next word for storage. (A) in Tables 3 and 4 above,
The case of (d) corresponds to the A and C patterns of FIG. The maximum run length detecting circuit 23 detects the maximum run length in the C pattern, and the run length from the holding circuit 27 to the previous word is given as an initial value to detect the maximum run length of the current word. Further, the maximum run length detection circuit 22 detects the maximum run length in the A pattern, and the run length from the holding circuit 26 to the previous word is given as an initial value to detect the maximum run length of the current word. The maximum run length detection circuit 22 detects the run length from the last bit of the current word in the direction of the first bit, and supplies it to the holding circuit 26 as the initial value of the next word for storage.

The A pattern and the C pattern are based on the polarities of the first bit of the previous word and the last bit of the previous two words, and the selection circuit 28 determines whether the modulation output of the previous word from the holding circuit 10 is established. Given the bits first1 and last2, the maximum run length based on the pattern that can be actually taken is output to the comparison circuit 29. Thus, the comparison circuit
29 can be used as the modulation output of the current word (a),
The maximum run length obtained in the case of (d) and the cases of (b) and (c) is supplied. The comparison circuit 29 outputs a control signal indicating whether or not the input maximum run length exceeds the set value N, and the maximum run length from the selection circuit 28 and the maximum run length from the maximum run length detection circuit 24. And outputs a signal indicating which run length is smaller to the inverting circuit 30.

That is, in the inverting circuit 30, (a) in Table 3
A signal indicating selection of the modulation output in the case of (d) or a signal indicating selection of the modulation output in the cases of (b) and (c) of Table 3 is given. The inverting circuit 30 is provided with the last bit of the previous word, and when this last bit is “0”, selection for selecting the case of (a) of Table 3 or the case of (b) of Table 3 A signal is output, and when it is "1", a selection signal for selecting the case (d) of Table 3 or the case (c) of Table 3 is output.

When it is shown that the maximum run length does not exceed the set value N regardless of which modulation output is selected by the control signal, the decision circuit 15 determines the control bit based on an external factor. To the bit inversion circuit 13. When the last bit of the previous word is given from the holding circuit 10 and the last bit is “0”, the bit inversion circuit 13 outputs the common bit group as it is, and the inversion bit group is used as an instruction from the decision circuit 15. Inversion or non-inversion processing is performed based on the above. Further, the bit inverting circuit 13 inverts the common bit group and inverts or non-inverts the inverted bit group based on the instruction from the decision circuit 15 when the last bit of the previous word is “1”. .

When the control signal indicates that the maximum run length exceeds the set value N, the decision circuit 15 sends a signal for determining the control bit to the bit inversion circuit 13 based on the selection signal. give. The bit inversion circuit 13 inverts or inverts the inversion bit group based on the output of the decision circuit 15 as in the case where the maximum run length does not exceed the set value N.

As described above, in the present embodiment, there are two patterns that can be taken as the modulation output of the current word in accordance with the polarities of the last bit and the first bit of the modulation output, and the pattern of the previous word is utilized. Before the modulation output is confirmed,
For each of these patterns, the maximum run length is detected, and after the modulation output of the previous word is confirmed, the control bit of the current word is selected based on the final bit of the previous word, and sufficient processing time for run length detection is selected. Therefore, the constraint on processing time is relaxed.

[0056]

As described above, according to the present invention, there is an effect that the restriction on the processing time for detecting the run length can be relaxed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an encoding device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a run length detection circuit 14 in FIG.

FIG. 3 is an explanatory diagram showing a modulation output having the longest run length.

FIG. 4 is an explanatory diagram for explaining a relationship between a final bit and a leading bit of a modulation output and a range necessary for calculating a maximum run length.

FIG. 5 is a block diagram showing a conventional encoding device.

[Explanation of symbols]

11 ... "0" addition circuit, 12 ... Precoder, 13 ... Bit inversion circuit, 14 ... Run length detection circuit, 15 ... Decision circuit

Claims (4)

[Claims] 1. L bits (L bits of input modulated data)
Is a positive integer), a control bit adding means for adding a control bit of a predetermined polarity for each 1 bit, and I-assuming that the output of the control bit adding means has a 1 bit of a predetermined polarity added at the beginning thereof. NRZI
Modulation means for performing conversion and outputting a conversion output in word units of (L + 1) bits, and an inversion bit group that inverts the bits when the polarity of the control bit is changed among the bits of the conversion output is inverted or non-inverted. A first bit inverting means for inverting and a second bit inverting means for inverting or non-inverting a common bit group that does not bit-invert even if the polarity of the control bit is changed among the bits of the converted output, Bit inversion means for inverting or non-inverting each bit of the conversion output and outputting it as a modulation output, and for controlling inversion or non-inversion of the second bit inversion means based on the modulation output of the previous word; The first run for detecting the maximum run length of the current word when the last bit of the modulation output of the current word and the first bit of the modulation output of the current word have the same polarity. Length detecting means, and second run length detecting means for detecting the maximum run length of the current word when the last bit of the modulation output of the previous word and the first bit of the modulation output of the current word have different polarities. Comparing the maximum run length detected by the first run length detection means with the maximum run length detected by the second run length detection means, and giving the smaller maximum run length, the first and second run lengths. Comparing means for outputting a comparison result indicating any one of the detecting means, and inverting or non-inverting the comparison result based on the final bit of the modulation output of the previous word after the modulation output of the previous word is determined and outputting it as a selection signal. And a signal for controlling inversion or non-inversion of the inversion bit group based on the selection signal to the bit inversion means. Encoding apparatus characterized by comprising a determination means for obtaining. 2. The comparison means outputs, together with the comparison result, a control signal indicating whether or not the maximum run length detected by the first or second run length detection means exceeds a predetermined set value, When the control signal indicates that the maximum run length detected by the first or second run length detecting means does not exceed a predetermined set value, the determining means determines a value other than the maximum run length. The bit inverting means is controlled based on a factor, and when it is shown that a predetermined set value is exceeded, the bit inverting means is controlled based on the selection signal. Encoding device described. 3. The first run length detecting means stores the run length up to the previous word, and a first holding means for holding the run length up to the previous word, and a current word based on the output of the first holding means and the converted output. A first maximum run length detecting means for detecting the maximum run length, giving it to the first holding means and outputting it, and a second holding the output of the second run length detecting means as the run length up to the previous word Holding means for detecting the maximum run length of the current word based on the output of the second holding means and the converted output, and the first and second maximum run length detecting means. One of the outputs of the maximum run length detecting means is selected based on whether or not the last bit of the modulation output two words before and the first bit of the modulation output of the previous word have the same polarity, and the comparison is performed. The encoding apparatus according to claim 1, characterized by comprising a selection means for providing to the stage. 4. The first and second run length detecting means detect the maximum run length based on an exclusive OR operation result of about 1 bit before and after the converted output. Encoding device described.