JPH08149169A - Digital quadrature modulator - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To obtain a modulated signal with a frequency of 1/4 of the maximum processing speed of the D / A converter. [Configuration] Pre-filters 29 and 30 for attenuating repetitive noise generated after conversion into an analog signal by a predetermined level,
Baseband I, Q signal 13, 14 band-limiting filter 1,
2, a digital quadrature modulation circuit composed of polarity inverters 31, 32 and a P / S converter 33, a D / A converter 9 for converting the digital modulation signal 23 into an analog modulation signal 24, and an unnecessary frequency component LPF 10 for removing, analog mixer 11 for mixing analog signal 25 with local oscillation signal 26, and BPF 12 for removing unnecessary frequency component of output analog signal 27.
A digital quadrature modulator is constituted by.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature modulator used for radio equipment such as digital mobile communication.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing the configuration of a conventional digital quadrature modulator of this type. In FIG.
Reference numerals 1 and 2 are digital band limiting filters for band limiting the base band I and Q signals 13 and 14, respectively, and 3 and 4 are band limited base band I and Q signals 15 and 16 and carrier signals.
(COS waveform signal 19, SIN waveform signal 20) Digital multiplier 5, 5 is a counter for calling the SIN waveform signal and the COS waveform signal, 6 is a COS waveform generation ROM for outputting the COS waveform signal, and 7 is a SIN waveform signal SIN waveform generation ROM for output, 8 is a digital adder for adding both I and Q signals 21 and 22, 9 is a D / A converter for converting the digital modulation signal 23 into an analog modulation signal 24, and 10 is an analog modulation signal 24 , An analog mixer for mixing the analog signal 25 output by the low-pass filter 10 with the local oscillation signal 26 from the local oscillator LO for up-conversion, and 12 for outputting the analog signal. It is a bandpass filter that outputs an analog modulated signal 28 from which unnecessary frequency components of the analog signal 27 are removed.

The operation of the digital quadrature modulator configured as described above will be described. First, the baseband I signal 13,
The baseband Q signal 14 is input to the digital band limiting filters 1 and 2, respectively, and band limited. Next, the band-limited baseband I signal 15 and baseband Q signal
16 is input to the digital multipliers 3 and 4, respectively.

A sampling clock 17 is input to the counter 5, and a control signal 18 is output from the counter 5. This control signal 18 is the COS waveform generation ROM 6 and SI
The COS waveform signal 19 and the SIN waveform signal 20 are input to the N waveform generating ROM 7 as carrier signals and input to the digital multipliers 3 and 4, respectively.

The band-limited baseband I signal 15
And the COS waveform signal 19 are multiplied by the digital multiplier 3 to output the I signal 21. Further, the band-limited baseband Q signal 16 and SIN waveform signal 20 are multiplied by the digital multiplier 4 and a Q signal 22 is output.

Next, the I signal 21 and the Q signal 22 are added by the digital adder 8 and a digital modulated signal 23 is output. This digital modulation signal 23 is input to the D / A converter 9, and an analog modulation signal 24 is obtained. An unnecessary frequency component is removed from the analog modulated signal 24 by the low pass filter 10, and an analog signal 25 is obtained.

This analog signal 25 is sent to the analog mixer 11
Is input to, and mixed with the local oscillation signal 26 from the local oscillator LO and up-converted to obtain an analog signal 27. Finally, the analog signal 27 is input to the bandpass filter 12 and unnecessary frequency components are removed, whereby an analog modulated signal 28 is obtained.

[0008]

The modulated signal output from the above-described conventional digital quadrature modulator is generally mixed with the local oscillation signal from the local oscillator in the subsequent stage and up-converted to obtain the necessary signal component. The others are filtered out. However, as the frequency of the modulation signal decreases, a steep filter is required, and it becomes difficult to realize the filter. Therefore, it is necessary to increase the frequency of the modulation signal output from the digital quadrature modulator.

However, the frequency of the modulated signal output by the digital quadrature modulator is determined by the operation speed of the digital multiplier. In the digital quadrature modulator having the above configuration, when the number of samplings per cycle is 4, the frequency of the modulation signal is 1 which is the maximum operation speed of the digital multiplier.
/ 4 is the limit.

SUMMARY OF THE INVENTION The first object of the present invention is to provide a digital quadrature modulator capable of outputting a modulation signal having a frequency of 1/4 of the maximum processing speed of a D / A converter in order to solve such a conventional drawback. It is what

In addition to the first object, a second object is to further increase the speed by outputting the aliasing noise component of the fundamental modulated wave as a modulation signal.

Further, in addition to the above-mentioned first object, a third object is to further increase the speed by outputting the higher harmonic components of the fundamental modulated wave as a modulation signal.

Further, in addition to the above-mentioned first object, a fourth object is to further increase the speed by reducing the number of operation bits.

[0014]

In order to achieve each of the above objects, the present invention provides a first solving means for achieving the first object, wherein folding noise generated after converting a digital signal into an analog signal is predetermined. A prefilter for attenuating only the level, a digital band limiting filter for band limiting the baseband I and Q signals, a digital quadrature modulation circuit composed of a polarity inverter and a parallel-serial converter, and an output by the digital quadrature modulation circuit. D / A for converting the converted digital modulation signal to an analog modulation signal
A converter, a low-pass filter for removing unnecessary frequency components of the analog modulated signal output by the D / A converter, and an analog mixer for up-converting the analog signal output by the low-pass filter by mixing with the local oscillation signal. A band pass filter for removing unnecessary frequency components of the analog signal output by the analog mixer, and an analog modulation signal is obtained from the output of the band pass filter.

The second means for achieving the above second object is a digital band limiting filter for band limiting the baseband I and Q signals, a digital quadrature constituted by a polarity inverter and a parallel-serial converter. A modulation circuit, a polarity inverter that inverts the polarity of the digital signal output by the digital quadrature modulation circuit, and a D / A converter that converts the digital signal whose polarity is inverted by the polarity inverter into an analog modulation signal. And a bandpass filter for extracting the aliasing noise component of the analog modulation signal output by the D / A converter as a modulation signal and removing unnecessary frequency components, and the analog signal output by the bandpass filter for the local oscillation signal. With an analog mixer that mixes with and up-converts Consists bandpass filter for removing an unnecessary frequency component of the output analog signal, characterized by obtaining the analog modulated signal from the output of the bandpass filter.

A third means for achieving the third object is a digital band limiting filter for band limiting the baseband I and Q signals, a digital quadrature constituted by a polarity inverter and a parallel-serial converter. A modulation circuit, a D / A converter for converting a digital signal output by the digital quadrature modulation circuit into an analog modulation signal, and a high-order harmonic component of the analog modulation signal output by the D / A converter A band-pass filter that takes out as a signal and removes unnecessary frequency components, an analog mixer that mixes the analog signal output by the band-pass filter with a local oscillation signal and up-converts, and an unnecessary analog signal output by the analog mixer. It consists of a bandpass filter that removes frequency components. Characterized in that obtaining an analog modulated signal from the output of the de-pass filter.

A fourth means for achieving the above fourth object is a digital quadrature modulation circuit composed of a polarity inverter and a parallel-serial converter, and a digital modulation signal output by the digital quadrature modulation circuit. A D / A converter for converting the signal into an analog modulated signal, and the D / A converter
A low-pass filter for removing unnecessary frequency components of the analog modulation signal output by the A converter, and an analog mixer for up-converting the analog signal output by the low-pass filter by mixing with the local oscillation signal.
It is characterized by comprising a band-pass filter for band-limiting the analog signal output by the analog mixer, and obtaining an analog modulated signal from the output of the band-pass filter.

[0018]

According to each of the solutions of the present invention, the polarity inverter and the parallel-serial converter are used without using the ROM or the digital multiplier for outputting the COS and SIN waveform signals as in the conventional digital quadrature modulator. In the present invention, the number of oversamplings per cycle of the carrier is set to 4 by using the digital quadrature modulation circuit described above. Therefore, the frequency of the basic modulation wave is set to the maximum processing speed of the D / A converter. Can be set to 1/4.

Further, according to the second solving means, the first
In addition to the effect of the above, by outputting the aliasing noise component as a modulation signal, the maximum processing speed of the D / A converter is 3
A modulated signal having a frequency of / 4 can be obtained.

Further, according to a third solving means, the first
In addition to the effect of the above, by outputting a high-order harmonic component as a modulation signal, the maximum processing speed of the D / A converter is reduced to 5 /
A modulated signal of 4 frequencies can be obtained.

Further, according to a fourth solving means, the above first
In addition to the effect of (1), the speed can be further increased by reducing the number of required operation bits by limiting the band using the bandpass filter in the latter stage.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of a digital quadrature modulator according to a first embodiment of the present invention. In FIG. 1, 29 and 30 are pre-filters that attenuate a folding noise component generated after converting a digital signal into an analog signal by a predetermined level, 31 and 32 are polarity inverters that invert the polarity of an input signal, and 33 is four It is a parallel-serial converter (hereinafter referred to as P / S converter) that synthesizes signals input in a system in time order by a sampling clock 17 and converts the signals into one system signal. These polarity inverters 31, 32 and the P / S converter 33 constitute a digital quadrature modulation circuit. In addition, the same numbers are assigned to the blocks, signals and the like having the same functions described in FIG. 7, and the description thereof will be omitted.

FIGS. 5 and 6 are timing charts of the digital quadrature modulator shown in FIG. 1 and FIGS. 2 to 4 which will be described later, and will be described with reference to FIG. The same applies to FIG. A is a sampling clock, which corresponds to 17 in FIG. B is a sampling clock obtained by dividing the sampling clock A by 2, C is a sampling clock obtained by dividing the sampling clock A by 4, and D is a band-limited baseband I signal.
Corresponds to 15. E is a band-limited baseband Q signal, which corresponds to 16 in FIG. F is the baseband I signal of D
This is a signal obtained by reversing the polarity of 15 and corresponds to 36 in FIG. G is E
1 is a signal obtained by reversing the polarity of the baseband Q signal 16 of
Corresponds to 37. H is a signal obtained by the logical product of the baseband I signal 15 of D and the sampling clock of C,
I is a signal obtained by the logical product of the D baseband I signal 15 and the signal obtained by inverting the polarity of the sampling clock of C, J is a signal obtained by the logical sum of the H signal and the I signal, and K is A signal obtained by the logical product of the E baseband Q signal 16 and the sampling clock of C, L is E
Signal obtained by ANDing the baseband Q signal 16 of
Is a signal obtained by the logical sum of the K signal and the L signal, N is a signal obtained by the logical product of the J signal and the B sampling clock, and O is the polarity of the M signal and the B sampling clock. A signal obtained by the logical product with the inverted signal, P is a digital modulation signal, and corresponds to 23 in FIG.

The operation of the digital quadrature modulator shown in FIG. 1 configured as above will be described with reference to the timing charts of FIGS. 5 and 6.

The baseband I signal 13 and the baseband Q signal 14 are input to prefilters 29 and 30, respectively,
The pre-filters 29 and 30 attenuate the frequency component closest to the modulation signal among the aliasing noise components generated after conversion to the analog signal by a predetermined level.

The baseband I signal 34 and the baseband Q signal 35 output by the pre-filters 29 and 30 are band-limited by the digital band limiting filters 1 and 2, respectively, and are band-limited to D and E shown in FIG. 5, respectively. A baseband I signal 15 and a baseband Q signal 16 are obtained. On the other hand, the band-limited baseband I of D and E
Signal 15 and baseband Q signal 16 are polarity reversals respectively
The polarities are inverted by 31, 32 to obtain the -I signal 36 of F and the -Q signal 37 of G shown in FIG. 5, respectively. D band-limited baseband I signal 15, E bandlimited baseband Q signal 16, F -I signal 36 and G -Q signal
The outputs from the four systems of 37 are input to the P / S converter 33, respectively. These signals are combined by the P / S converter 33 in time sequence at the timing of the cycle of the sampling clock 17 of A shown in FIG.

That is, the baseband I of D shown in FIG.
The signal H in FIG. 5 is obtained by the logical product of the signal 15 and the sampling clock C in which the sampling clock 17 in A is divided by 4, and the baseband I signal 15 in D in FIG. The signal I of FIG. 5 is obtained by the logical product of the signal 36 of F and the signal of which the sampling clock 17 of A is divided by 4 and the polarity of the sampling clock of C is inverted.
The signal S (nT / 2) of J shown in FIG. 5 is obtained by the logical sum of the signal H and the signal I shown in FIG. This J signal S
(nT / 2) is as shown in (Equation 1).

[0029]

[Equation 1] However, n; 0,1,2, ..., k; 0,1,2, ..., T; 1 / Modulation frequency Similarly, the baseband Q signal 16 and A of E shown in FIG.
The signal K of FIG. 5 is obtained by the logical product of the sampling clock 17 of FIG. 4 and the sampling clock of C, and the signal G of FIG. 5 obtained by inverting the polarity of the baseband Q signal 16 of E shown in FIG. And sampling clock 17 of A is 4
The signal of L in FIG. 5 is obtained by a logical product of the frequency-divided C sampling clock and a signal whose polarity is inverted, and the logical sum of the signal K and the signal L shown in FIG. nT / 2) is obtained. This M signal SS (nT / 2) is (Equation 2)
It becomes as shown in.

[0030]

[Equation 2] However, n; 0, 1, 2, ..., k; 0, 1, 2, ..., T; 1 / modulation frequency Next, the sampling clocks 17 for the signals J and A shown in FIG.
The signal N of FIG. 6 is obtained by the logical product with the sampling clock of B obtained by dividing
6 is obtained by the logical product of a signal obtained by dividing the sampling clock 17 of A and A by 2 and the polarity of the sampling clock of B being inverted, and by the logical sum of these signals N and O, the signal of FIG. P digital modulation signal DATA shown
(nT / 4) is obtained. This P digital modulation signal DATA (n
T / 4) becomes as shown in (Equation 3).

[0031]

(Equation 3) However, n; 0,1,2, ..., k; 0,1,2, ..., T; 1 / Modulation frequency The digital modulation signal 23 of P shown in FIG.
, And the analog modulation signal 24 is obtained at the timing of the sampling clock 17 of A shown in FIG. An unnecessary frequency component is removed from the analog modulated signal 24 by the low pass filter 10, and an analog signal 25 is obtained.

The analog signal 25 is input to the analog mixer 11, mixed with the local oscillation signal 26 from the local oscillator LO and up-converted to obtain an analog signal 27. The analog signal 27 is input to the bandpass filter 12, and unnecessary frequency components are removed, whereby an analog modulated signal 28 is obtained and output.

As described above, according to this embodiment (1), a digital quadrature modulation circuit composed of a polarity inverter and a P / S converter is used instead of the conventional ROM and digital multiplier. Therefore, in the present invention, the number of oversamplings per carrier period is set to 4,
The frequency of the fundamental modulated wave is 1 of the maximum processing speed of the D / A converter.
It can be / 4.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and the modulation frequency is limited to about 10 MHz in the conventional configuration. However, the general market 10
Since the maximum processing speed of the bit D / A converter is about 400 MHz, the modulation frequency can be set to about 100 MHz in this embodiment (1), and a modulation signal having a frequency about 10 times that of the conventional configuration can be obtained. be able to.

(Embodiment 2) FIG. 2 is a block diagram showing the structure of a digital quadrature modulator according to a second embodiment of the present invention. In FIG. 2, reference numeral 38 denotes a polarity inverter for inverting the polarity of the digital modulation signal 23 output from the P / S converter 33, which is connected between the P / S converter 33 and the D / A converter 9. Reference numeral 39 is a bandpass filter that outputs the aliasing noise component of the basic modulated wave as a modulation signal, and is connected between the D / A converter 9 and the analog mixer 11. Other than the above, FIG.
The same signals and functional blocks described in 1 above are assigned the same reference numerals and explanations thereof are omitted.

The operation of the digital quadrature modulator shown in FIG. 2 configured as described above will be described with reference to the timing charts of FIGS. 5 and 6.

The baseband I signal 13 and the baseband Q signal 14 are digital band limiting filters 1 and 1, respectively.
Entered in 2. This digital band limiting filter 1,
The band-limited base band I signal 15 and the base band Q of D and E shown in FIG.
The signal 16 is obtained. On the other hand, the D and E band-limited baseband I signal 15 and the baseband Q signal 16 are polarity-inverted by the polarity inverters 31 and 32, respectively, and the -I signal 36 and G of F shown in FIG. A Q signal 37 is obtained. The outputs from the four systems of the band-limited baseband I signal 15 of FIG. 5, the band-limited baseband Q signal 16 of E, the -I signal 36 of F and the -Q signal 37 of G are P / It is input to the S converter 33. These signals are combined by this P / S converter 33 in time sequence at the timing of the cycle of the sampling clock 17 of A shown in FIG.

That is, the baseband I of D shown in FIG.
The signal H in FIG. 5 is obtained by the logical product of the signal 15 and the sampling clock C in which the sampling clock 17 in A is divided by 4, and the baseband I signal 15 in D in FIG. The signal I of FIG. 5 is obtained by the logical product of the signal 36 of F and the signal of which the sampling clock 17 of A is divided by 4 and the polarity of the sampling clock of C is inverted.
The signal S (nT / 2) of J shown in FIG. 5 is obtained by the logical sum of the signal H and the signal I shown in FIG. This J signal S
(nT / 2) is as shown in (Equation 1) above.

Similarly, the baseband Q signal 16 of E and the sampling clock 17 of A shown in FIG.
The signal of K in FIG. 5 is obtained by the logical product with the sampling clock of FIG. 5, and the signal 37 of G in FIG. 5 and the sampling clock 17 of A shown in FIG. The signal of L in FIG. 5 is obtained by the logical product of the signal obtained by reversing the polarity of the sampling clock of C described above, and the logical sum of the signal K and the signal L shown in FIG.
M signal SS (nT / 2) is obtained. This M signal SS (nT / 2)
Becomes as shown in (Equation 2) above.

Next, the signal N shown in FIG. 6 is obtained by the logical product of the signal J shown in FIG. 5 and the sampling clock 17 obtained by dividing the sampling clock 17 for A by two.
6 is obtained by the logical product of a signal M and a sampling clock 17 of A, which is obtained by dividing the sampling clock 17 of A by 2, and a signal obtained by inverting the polarity of the sampling clock of B, and the logical sum of these signals N and O is obtained. , P digital modulation signal DATA (nT / 4) shown in FIG. 6 is obtained. The digital modulation signal DATA (nT / 4) of P is as shown in (Equation 3).

The polarity of the digital modulation signal 23 of P shown in FIG. 6 is inverted by the polarity inverter 38, and the signal 40 is obtained.
This signal 40 is input to the D / A converter 9, and the A signal shown in FIG.
An analog modulation signal 24 is obtained at the timing of the sampling clock 17 of.

The analog modulation signal 24 is input to the bandpass filter 39, the aliasing noise component is output as a modulation signal, unnecessary frequency components are removed, and the analog signal 25 is output.
Is obtained. Since the aliasing noise component is a signal obtained by inverting the polarity of the fundamental modulated wave, a desired modulated signal can be obtained.

The analog signal 25 is input to the analog mixer 11, mixed with the local oscillation signal 26 from the local oscillator LO and up-converted to obtain an analog signal 27. The analog signal 27 is input to the bandpass filter 12, and unnecessary frequency components are removed, whereby an analog modulated signal 28 is obtained and output.

As described above, according to the present embodiment (2), the digital quadrature modulation circuit composed of the polarity inverter and the P / S converter is used instead of the conventional ROM and digital multiplier. In the present invention, since the number of oversamplings per carrier cycle is 4, the frequency of the fundamental modulated wave can be set to 1/4 of the maximum processing speed of the D / A converter. Further, when the number of samplings per cycle is 4, the frequency of the aliasing noise is three times the frequency of the fundamental modulated wave according to the sampling theorem. Therefore, in the embodiment (2), it is possible to obtain a modulated signal having a frequency of 3/4 of the maximum processing speed of the D / A converter.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and the modulation frequency is limited to about 10 MHz in the conventional configuration. However, the general market 10
Since the maximum processing speed of the bit D / A converter is about 400 MHz, the modulation frequency can be set to about 300 MHz in this embodiment (2), and a modulation signal having a frequency about 30 times that of the conventional configuration can be obtained. be able to.

(Embodiment 3) FIG. 3 is a block diagram showing the structure of a digital quadrature modulator according to a third embodiment of the present invention. This is because the polarity inverter 38 provided between the P / S converter 33 and the D / A converter 9 in the embodiment (2) (FIG. 2) is eliminated, and the digital modulation of the P / S converter 33 is directly performed. Traffic light 23
Is input to the D / A converter 9.

The operation of the digital quadrature modulator shown in FIG. 3 configured as described above will be described with reference to the timing charts of FIGS. 5 and 6.

The baseband I signal 13 and the baseband Q signal 14 are digital band limiting filters 1 and 1, respectively.
Entered in 2. This digital band limiting filter 1,
The band-limited base band I signal 15 and the base band Q of D and E shown in FIG.
The signal 16 is obtained. On the other hand, the D and E band-limited baseband I signal 15 and the baseband Q signal 16 are polarity-inverted by the polarity inverters 31 and 32, respectively, and the -I signal 36 and G of F shown in FIG. A Q signal 37 is obtained. The band-limited baseband I signal 15 of FIG.
The outputs from the four systems of the E band limited baseband Q signal 16, the F -I signal 36 and the G -Q signal 37 are P.
It is input to the / S converter 33. These signals are sent to the sampling clock of A shown in FIG. 5 by the P / S converter 33.
They are combined in time order at the timing of 17 cycles.

That is, the baseband I signal of D in FIG.
The signal H in FIG. 5 is obtained by the logical product of 15 and the sampling clock C in which the sampling clock 17 in A is divided by four, and the baseband I signal 15 in D in FIG. Signal 36 and A sampling clock 17
The signal of I in FIG. 5 is obtained by the AND operation with the signal obtained by inverting the polarity of the sampling clock of C divided by 4
The signal S (nT / 2) of J shown in FIG. 5 is obtained by the logical sum of the signal H and the signal I shown in FIG. This J signal S (nT /
2) is as shown in (Equation 1) above.

Similarly, the baseband Q signal 16 of E and the sampling clock 17 of A shown in FIG.
The signal of K in FIG. 5 is obtained by the logical product with the sampling clock of FIG. 5, and the signal 37 of G in FIG. 5 and the sampling clock 17 of A shown in FIG. The signal of L in FIG. 5 is obtained by the logical product of the signal obtained by inverting the polarity of the sampling clock of C and the signal SS (nT / nT / M of FIG. 5 is obtained by the logical sum of the signal K and the signal L shown in FIG. 2) is obtained. This M signal SS (n
T / 2) is as shown in (Equation 2) above.

Next, the signal N shown in FIG. 6 is obtained by the logical product of the signal J shown in FIG. 5 and the sampling clock 17 obtained by dividing the sampling clock 17 for A by two.
6 is obtained by the logical product of a signal M and a sampling clock 17 of A, which is obtained by dividing the sampling clock 17 of A by 2, and a signal obtained by inverting the polarity of the sampling clock of B, and the logical sum of these signals N and O is obtained. , P digital modulation signal DATA (nT / 4) shown in FIG. 6 is obtained. The digital modulation signal DATA (nT / 4) of P is as shown in (Equation 3).

The digital modulation signal 23 of P shown in FIG. 6 is D
An analog modulated signal 24 is obtained at the timing of the sampling clock 17 of A shown in FIG. The analog modulation signal 24 is input to the bandpass filter 39, and the high-order harmonic component is output as a modulation signal,
The unnecessary frequency component is removed, and the analog signal 25 is obtained.

This analog signal 25 is sent to the analog mixer 11
Is input to, and mixed with the local oscillation signal 26 from the local oscillator LO and up-converted to obtain an analog signal 27. This analog signal 27 is input to the bandpass filter 12 and by removing unnecessary frequency components,
An analog modulated signal 28 is obtained and output.

As described above, according to the present embodiment (3), it is possible to use a digital quadrature modulation circuit composed of a polarity inverter and a P / S converter, without using a ROM and a digital multiplier as in the prior art. According to the present invention, the number of oversamplings per carrier cycle is set to 4, so that the frequency of the fundamental modulated wave is 1 / the maximum processing speed of the D / A converter.
It can be 4. When the number of samplings per cycle is 4 and the second harmonic of the fundamental modulated wave is output as a modulated signal, the second
The frequency of the second harmonic component is 5 times the frequency of the fundamental modulated wave. Therefore, in the present embodiment (3), it is possible to obtain a modulation signal having a frequency of 5/4 of the maximum processing speed of the D / A converter.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and the modulation frequency is limited to about 10 MHz in the conventional configuration. However, the general market 10
Since the maximum processing speed of the bit D / A converter is about 400 MHz, the modulation frequency can be set to about 500 MHz in this embodiment (3), and a modulation signal with a frequency about 50 times that of the conventional configuration can be obtained. be able to.

(Embodiment 4) FIG. 4 is a block diagram showing the structure of a digital quadrature modulator according to a fourth embodiment of the present invention. This eliminates the pre-filters 29 and 30 in the first embodiment (FIG. 1) and directly directly outputs the baseband I signal 13, the baseband Q signal 14, and the -I signal 36, which is the polarity inversion of these I and Q signals. The outputs from the four systems of the -Q signal 37 are input to the P / S converter 33.

The operation of the digital quadrature modulator of FIG. 4 configured as described above will be described with reference to the timing charts of FIGS. 5 and 6.

Baseband I signal 1 of D and E shown in FIG.
5, baseband Q signal 16 has polarity inverters 31 and 3 respectively
The polarity is inverted by 2 and the −I of F shown in FIG.
The signal 36 and the -Q signal 37 of G are obtained. These baseband I signal 15, baseband Q signal 16 and -I signal 36 of F
The outputs from the four systems of the -Q signal 37 of G and G are P / S.
Input to the converter 33. These signals are P / S converter
33, they are combined in time order at the timing of the cycle of the sampling clock 17 of A shown in FIG.

That is, the baseband I signal of D in FIG.
The signal H in FIG. 5 is obtained by the logical product of 15 and the sampling clock C in which the sampling clock 17 in A is divided by four, and the baseband I signal 15 in D in FIG. Signal 36 and A sampling clock 17
The signal of I in FIG. 5 is obtained by the AND operation with the signal obtained by inverting the polarity of the sampling clock of C divided by 4
The signal S (nT / 2) of J shown in FIG. 5 is obtained by the logical sum of the signal H and the signal I shown in FIG. This J signal S (nT /
2) is as shown in (Equation 1) above.

Similarly, the baseband Q signal 16 of E and the sampling clock 17 of A shown in FIG.
The signal of K in FIG. 5 is obtained by the logical product with the sampling clock of FIG. 5, and the signal 37 of G in FIG. 5 and the sampling clock 17 of A shown in FIG. The signal of L in FIG. 5 is obtained by the logical product of the signal obtained by inverting the polarity of the sampling clock of C and the signal SS (nT / nT / M of FIG. 5 is obtained by the logical sum of the signal K and the signal L shown in FIG. 2) is obtained. This M signal SS (n
T / 2) is as shown in (Equation 2) above.

Next, the signal N of FIG. 6 is obtained by the logical product of the signal J shown in FIG. 5 and the sampling clock 17 of A obtained by dividing the sampling clock 17 of A by two.
6 is obtained by the logical product of a signal M and a sampling clock 17 of A, which is obtained by dividing the sampling clock 17 of A by 2, and a signal obtained by inverting the polarity of the sampling clock of B, and the logical sum of these signals N and O is obtained. , P digital modulation signal DATA (nT / 4) shown in FIG. 6 is obtained. The digital modulation signal DATA (nT / 4) of P is as shown in (Equation 3).

The digital modulation signal 23 of P shown in FIG. 6 is D
An analog modulated signal 24 is obtained at the timing of the sampling clock 17 of A shown in FIG. An unnecessary frequency component is removed from the analog modulated signal 24 by the low pass filter 10, and an analog signal 25 is obtained.

This analog signal 25 is sent to the analog mixer 11
Is input to, and mixed with the local oscillation signal 26 from the local oscillator LO and up-converted to obtain an analog signal 27. The analog signal 27 is input to the bandpass filter 12 and band-limited, whereby an analog modulated signal 28 is obtained and output.

As described above, according to the present embodiment (4), a digital quadrature modulation circuit composed of a polarity inverter and a P / S converter is used instead of the conventional ROM and digital multiplier. According to the present invention, the number of oversamplings per carrier cycle is set to 4, so that the frequency of the fundamental modulated wave is 1 / the maximum processing speed of the D / A converter.
It can be 4.

Further, when the band limitation is performed in the base band section, the required number of operation bits for obtaining sufficient characteristics is about 12 bits. However, in the present embodiment (4), the band limitation is performed by using the band pass filter in the latter part, so that the required number of operation bits can be reduced to about 8 bits and the speed can be further increased.

The maximum processing speed of the current commercially available 12-bit digital multiplier is about 30 MHz, and in the conventional configuration, the modulation frequency is limited to about 7 MHz. However, the maximum processing speed of a commercially available 8-bit D / A converter is about 400MHz,
In this embodiment (4), the modulation frequency can be set to about 100 MHz, and a modulation signal having a frequency about 14 times that of the conventional configuration can be obtained.

[0067]

As described above, the present invention does not use a conventional ROM or digital multiplier, but uses a polarity inverter and a P / P converter.
By using the digital quadrature modulation circuit composed of the S converter, the frequency of the fundamental modulated wave can be made 1/4 of the maximum processing speed of the D / A converter.

Further, according to the embodiment (1), for example, when the number of operation bits is 10, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz. The limit is about 10MHz. However, since the maximum processing speed of a general commercially available 10-bit D / A converter is about 400 MHz, in this embodiment (1), the modulation frequency can be set to about 100 MHz, which is about 10 times that of the conventional configuration. It is possible to obtain a modulated signal with a frequency of.

Further, according to the embodiment (2), the aliasing noise component is further output as a modulated signal, so that D
This has the effect that a modulated signal having a frequency of 3/4 of the maximum processing speed of the / A converter can be obtained.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and the modulation frequency is limited to about 10 MHz in the conventional configuration. However, the general market 10
Since the maximum processing speed of the bit D / A converter is about 400 MHz, the modulation frequency can be set to about 300 MHz in this embodiment (2), and a modulation signal having a frequency about 30 times that of the conventional configuration can be obtained. be able to.

According to the embodiment (3), the maximum number of D / A converters is increased by setting the number of samplings per cycle to 4 and outputting the second harmonic component of the fundamental modulated wave as a modulated signal. It has an effect that a modulated signal having a frequency of 5/4 of the processing speed can be obtained.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and the modulation frequency is limited to about 10 MHz in the conventional configuration. However, the general market 10
Since the maximum processing speed of the bit D / A converter is about 400 MHz, the modulation frequency can be set to about 500 MHz in this embodiment (3), and a modulation signal with a frequency about 50 times that of the conventional configuration can be obtained. be able to.

Further, according to the embodiment (4), the band-pass filter is used in the subsequent stage to limit the band, and the required number of operation bits is reduced, thereby further increasing the speed. Have.

The maximum processing speed of the current commercial 12-bit digital multiplier is about 30 MHz, and in the conventional configuration, the modulation frequency is limited to about 7 MHz. However, the maximum processing speed of a commercially available 8-bit D / A converter is about 400MHz,
In this embodiment (4), the modulation frequency can be set to about 100 MHz, and a modulation signal having a frequency about 14 times that of the conventional configuration can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital quadrature modulator according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a digital quadrature modulator according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a digital quadrature modulator according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a digital quadrature modulator according to a fourth embodiment of the present invention.

FIG. 5 is a timing chart for explaining an operation of each unit of FIGS. 1 to 4.

FIG. 6 is a timing chart for explaining the operation of each unit in FIGS. 1 to 4.

FIG. 7 is a block diagram showing a configuration of a conventional digital quadrature modulator.

[Explanation of symbols]

1, 2 ... Digital band limiting filter, 9 ... D / A converter, 10 ... Low pass filter, 11 ... Analog mixer, 12, 39 ... Band pass filter, 13 ... Base band I signal, 14 ... Base band Q signal, 15 ... band-limited baseband I signal, 16 ... band-limited baseband Q signal, 17 ... sampling clock, 23 ...
Digital modulation signal, 24 ... Analog modulation signal, 25 ...
Analog signal from which unnecessary frequency components of analog modulated signal 24 are removed, 26 ... Local oscillation signal, 27 ... Analog modulated signal
24 up-converted analog signal, 28 ... analog modulated signal, 29, 30 ... pre-filter, 31, 32, 38 ...
Polarity inverter, 33 ... Parallel-serial (P / S) converter, 36 ...- I signal, 37 ...- Q signal.

Claims (4)

[Claims] 1. A prefilter for attenuating aliasing noise generated after converting a digital signal into an analog signal by a predetermined level, a digital band limiting filter for band limiting the baseband I signal and the baseband Q signal, and a polarity inverter. A digital quadrature modulation circuit composed of a parallel-serial converter, a D / A converter for converting a digital modulation signal output by the digital quadrature modulation circuit into an analog modulation signal, and an output by the D / A converter. A low-pass filter for removing unnecessary frequency components of the analog modulated signal, an analog mixer for up-converting the analog signal output by the low-pass filter with a local oscillation signal, and an unnecessary frequency of the analog signal output by the analog mixer Remove the component A digital quadrature modulator comprising a band-pass filter and obtaining an analog modulation signal from the output of the band-pass filter. 2. A digital quadrature modulation circuit composed of a digital band limiting filter for band limiting the baseband I signal and the baseband Q signal, a polarity inverter and a parallel-serial converter, and output by the digital quadrature modulation circuit. Polarity invertor for inverting the polarity of the converted digital signal, and D / A for converting the digital signal whose polarity is inverted by the polarity invertor into an analog modulation signal
A converter and a bandpass filter for extracting a folding noise component of the analog modulation signal output by the D / A converter as a modulation signal and removing an unnecessary frequency component;
An analog mixer that mixes an analog signal output by the bandpass filter with a local oscillation signal for up-conversion, and a bandpass filter that removes unnecessary frequency components of the analog signal output by the analog mixer. A digital quadrature modulator, which obtains an analog modulation signal from the output of. 3. A digital quadrature modulation circuit configured by a digital band limiting filter for band limiting the baseband I signal and the baseband Q signal, a polarity inverter and a parallel-serial converter, and output by the digital quadrature modulation circuit. A D / A converter for converting the digital signal thus converted into an analog modulation signal, and a band for extracting a high-order harmonic component of the analog modulation signal output by the D / A converter as a modulation signal and removing an unnecessary frequency component A pass filter, an analog mixer that mixes an analog signal output by the band pass filter with a local oscillation signal to up-convert, and a band pass filter that removes unnecessary frequency components of the analog signal output by the analog mixer, From the output of the bandpass filter, A digital quadrature modulator which obtains a analog modulation signal. 4. A digital quadrature modulation circuit composed of a polarity inverter and a parallel-serial converter, and a D / A converter for converting a digital modulation signal output by the digital quadrature modulation circuit into an analog modulation signal.
A low-pass filter for removing unnecessary frequency components of the analog modulation signal output by the D / A converter, an analog mixer for up-converting the analog signal output by the low-pass filter by mixing it with a local oscillation signal, and the analog mixer A digital quadrature modulator comprising a band-pass filter for band-limiting the analog signal output by, and obtaining an analog modulated signal from the output of the band-pass filter.