JP3356849B2 - Digital quadrature modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature modulator used for radio equipment such as digital mobile communication, and more particularly to a digital quadrature modulator for obtaining a high-frequency modulated wave.

[0002]

2. Description of the Related Art A conventional digital quadrature modulator is shown in FIG.
As shown in (a), a cosine (C
OS) a ROM 4 for outputting a waveform signal 12, and a sine (SI)
N) ROM 5 for outputting waveform signal 13, counter 3 for sending control signal 11 for calling SIN waveform signal and COS waveform signal to ROM 4 and ROM 5, multiplication for multiplying I baseband signal 8 and COS waveform signal 12 Vessel 1,
A multiplier 2 for multiplying the Q baseband signal 9 by the SIN waveform signal 13; an adder 6 for adding the I signal 14 output from the multiplier 1 and the Q signal 15 output from the multiplier 2; A D / A converter 7 for converting a digital modulation signal 16 output from the converter 6 into an analog modulation signal 17.

In this digital quadrature modulator, first, a baseband I signal 8 and a baseband Q signal 9 are input to multipliers 1 and 2, respectively. Also, the sampling frequency clock
10 is input to the counter 3, and the counter 3 outputs a control signal 11.

The control signal 11 is a COS waveform generating ROM
4 and the SIN waveform generation ROM 5, and the COS waveform generation ROM 4 outputs the COS waveform signal 12 as a COS waveform signal 12 in FIG.
As shown in (5), the values at the sample points of the COS curve are sequentially output according to the control signal. Further, the SIN waveform generation ROM 5 sequentially outputs the values at the sample points of the SIN curve as the SIN waveform signal 13 according to the control signal, as shown in FIG. These waveform signals 12, 13
Is input to the multiplier 1 or 2.

[0005] The multiplier 1 includes a baseband I signal 8 and a CO
The multiplier 2 multiplies the S waveform signal 12 to output an I signal 14, and the multiplier 2 multiplies the baseband Q signal 9 by the SIN waveform signal 13 to output a Q signal 15.

[0006] The I signal 14 and the Q signal 15 are added by the adder 6 and output as a digital modulation signal 16.

As shown in FIGS. 4 (b) and 4 (c), the digitally modulated signal 16 is a digital value that approximates one cycle of the COS or SIN waveform by eight sample values as a COS waveform signal and a SIN waveform signal. Is used, the following time-series data is obtained. I (0), (I (1) + Q (1)) / √2, Q (2), (−I
(3) + Q (3)) / √2, -I (4),-(I (5) + Q
(5)) / √2, -Q (6), (I (7) -Q (7)) / √2,
‥ where I (m) and Q (m) indicate the values of I and Q at the time point m.

The time-series data includes a COS waveform and S
When the period of the IN waveform, that is, the period of the modulated wave is T,
Generally, it can be expressed as follows. I (nT), {I ((n + 1/8) T) + Q ((n + 1/8) T)} / √2, Q ((n + 1/4) T), ｛−I ((n + 3/8) T) + Q ((n + 3/8) T) / {2, -I (n + 1/2) T), {-I ((n + 5/8) T) -Q ((n + 5/8) T)} / {2, −Q ((n + 3/4) T), {I ((n + 7/8) T) −Q ((n + 7/8) T)} / √2, (1) where n; 0, 1, 2, ... The digital modulation signal 16 is converted into an analog signal by the D / A converter 7, and an analog modulation signal 17 is obtained.

[0009]

The modulated signal output from the modulator is generally up-converted in a subsequent stage by mixing with a local oscillation signal, and components other than necessary signal components are removed by a filter. This filter is
As the frequency of the modulation signal becomes lower, it is required to have a sharp narrow band characteristic, and it becomes difficult to realize the characteristic. Therefore, it is necessary to increase the frequency of the modulation signal output from the modulator as much as possible.

However, the frequency of the modulated wave output from the modulator is determined by the operation speed of the multiplier. In a modulator having a configuration in which one cycle of a carrier signal is approximated by eight sample points, the highest frequency of the multiplier is obtained. 1/8 of the calculation speed is the limit.

An object of the present invention is to provide a digital quadrature modulator based on a new concept which can output a modulated wave having the same frequency as the maximum operating speed of a multiplier. It is an object.

[0012]

Therefore, according to the present invention, in a digital quadrature modulator for converting a digital modulation signal into an analog signal and outputting the analog signal, a baseband I signal and a baseband Q signal are synthesized in time sequence to form one system. First parallel-serial conversion means for converting the sum of the baseband I signal and the baseband Q signal into 1 / √
A first multiplying means for multiplying by two, a second multiplying means for multiplying the subtracted value of the baseband I signal and the baseband Q signal by 1 / √2, and a first multiplying means and a second multiplying means. Second parallel-serial conversion means for synthesizing the output signals in time sequence and converting the signals into one system signal;
-Parallel-serial conversion means and second parallel-serial
a third parallel-serial conversion unit that combines signals output from the serial conversion unit in time order and converts the signal into one system signal, and outputs a signal obtained by inverting the polarity of the output signal in the third parallel-serial conversion unit. Polarity reversing means;
And a fourth parallel-serial conversion means for combining signals output from the parallel-serial conversion means and the polarity inversion means in time order and converting the signals into the digital modulation signal.

[0013]

[Function] In this digital quadrature modulator, a Parallel-Seri
A digital modulation signal is formed by a combination of the al conversion means. Since the multiplier is inserted before the second parallel-serial conversion means and only performs 1 / √2 multiplication, this digital quadrature modulator outputs a modulated wave having the same frequency as the maximum operation speed of the multiplier. Can be output.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital quadrature modulator according to an embodiment of the present invention, as shown in FIG. 1, combines signals input from two systems in time order and converts them into one system signal.
-Serial converters (P / S converters) 18, 23, 24 and 26
, An adder 19 for adding the two input signals, a subtractor 20 for subtracting the two input signals, and 1 /
乗 算 Multipliers 21 and 22 for multiplying by 2 times, a polarity inverter 25 for inverting the polarity of the input signal, and a D for converting the digital modulation signal u output from the P / S converter 26 into an analog modulation wave signal / A converter 7.

FIGS. 2 and 3 show timing charts of the digital quadrature modulator in the embodiment.

A is a sampling clock input to each of the P / S converters 18, 23, 24 and 26. b is a clock obtained by dividing the sampling clock a by 2 and formed by the P / S converter 24. c is a clock obtained by dividing the sampling clock a by 4 and is formed in the P / S converters 18 and 23.

D is a clock obtained by dividing the sampling clock a by 8, is formed by the P / S converter 26, and is output to the D / A converter 7 as a modulation frequency clock.

E is a baseband I signal, and f is a baseband Q signal.

G is a signal obtained by the logical product of the baseband I signal e and the clock c, and h is a signal obtained by the logical product of the baseband Q signal f and the inverted signal of the clock c. is there. i is a logical sum of the signal g and the signal h, which corresponds to a signal obtained by synthesizing the baseband I signal e and the baseband Q signal f in chronological order and converting them into one system. Output from the container 18.

J is a signal obtained by adding (I + Q) the baseband I signal e and the baseband Q signal f and multiplying by 1 / √2, and k is the baseband I signal e from the baseband Q signal f. This is a signal obtained by subtracting (-I + Q) and multiplying by 1 / √2.

1 is a signal obtained by the logical product of the signal j and the clock c, and m is a signal obtained by the logical product of the signal k and a signal obtained by inverting the polarity of the clock c.

N is a logical sum of the signal 1 and the signal m, which corresponds to a signal obtained by synthesizing the signal j and the signal k in chronological order and converting them into one system. Output from

O is a signal obtained by the logical product of the signal i and the clock b, and p is a signal obtained by the logical product of the signal n and the inverted signal of the clock b.
q is a logical sum of the signal o and the signal p, which corresponds to a signal obtained by synthesizing the signal i and the signal n in chronological order and converting them into one system, and is output from the P / S converter 24. .

R is a signal obtained by inverting the polarity of the signal q. s
Is a signal obtained by the logical product of the signal q and the modulation frequency clock d, and t is the signal obtained by the logical product of the signal r and the signal whose polarity is inverted from the modulation frequency clock d.

U is the logical sum of the signal s and the signal t, and P
This is a digitally modulated wave signal output from the / S converter 26.

The operation of the digital quadrature modulator will be described.

When a baseband I signal e and a baseband Q signal f having a phase difference of 90 degrees are input to a P / S converter 18, the P / S converter 18 converts these signals into a sampling clock a. The signals are synthesized in chronological order at the timing of the cycle of the clock b divided by two.

For this purpose, the signal g is obtained by the logical product of the baseband I signal e and the clock c having a period twice as long as the clock b, and the logical product of the baseband Q signal f and the inverted signal of the clock c. And the signal h is obtained by the logical sum of the signal g and the signal h.

When the period of the modulated wave is T, the signal g is
I (nT / 2) and the signal h is Q
((n + 1/2) T / 2), the signal i
(= S (nT / 2)) is expressed by the following equation (2).

S (nT / 2) = I (nT / 2) + Q ((n + 1/2) T / 2)) (2) where n: 0, 1, 2, ‥ T; 1 / modulation wave frequency.

The baseband I signal e and baseband Q signal f are input to an adder 19 and a subtractor 20,
The adder 19 outputs (I + Q), and the subtractor 20 outputs (−I +
Q) is output. Multipliers 21 and 22 multiply these output signals by 1 / √2 to form a signal j or k, and input them to P / S converter 23.

The P / S converter 23 combines these signals in time sequence at the timing of the clock b. For this purpose, the signal 1 is obtained by the logical product of the signal j and the clock c, the signal m is obtained by the logical product of the signal k and the inverted signal of the clock c, and the signal n is obtained by the logical sum of the signal 1 and the signal m.
Get.

The signal 1 is {I (nT / 2) + Q (nT / 2)}.
/ √2, and the signal m is ｛−I ((n
+1/2) T / 2) + Q ((n + 1/2) T / 2)｝ / √2, the signal n (= U (nT / 2)) is expressed by the following equation (3). Become.

U (nT / 2) = {I (nT / 2) + Q (nT / 2)} / √2 + ｛− I ((n + 1/2) T / 2) + Q ((n + 1/2) T / 2)｝ / √2 (3) where n; 0, 1, 2, ‥ T; 1 / modulation wave frequency.

The signal i output from the P / S converter 18 and
The signal n output from the P / S converter 23 is a P / S converter.
24, and the P / S converter 24 combines these signals in chronological order at the timing of the cycle of the sampling clock a.

For this purpose, the signal o is obtained by the logical product of the signal i and the clock b having a period twice as long as the sampling clock a, and the signal p is obtained by the logical product of the signal n and the inverted signal of the clock b. Then, a signal q is obtained from the logical sum of the signal o and the signal p.

The signal o is I (nT / 2) + Q ((n + 1/2) T /
2), and the signal p is ｛I ((n + 1 /
4) T / 2) + Q ((n + 1/4) T / 2)｝ / {2 + ｛− I ((n
+3/4) T / 2) + Q ((n + 3/4) T / 2)｝ / √2, the signal q (= V (nT / 2)) is expressed by the following equation (4). Become.

V (nT / 2) = I (nT / 2) + {I ((n + 1/4) T / 2) + Q ((n + 1/4) T / 2)} / √2 + Q ((n + 1/2 ) T / 2) + {-I ((n + 3/4) T / 2) + Q ((n + 3/4) T / 2)} / {2 (4) where n; 0, 1, 2, ‥ T; 1 / modulation wave frequency.

The signal q output from the P / S converter 24 is
Branched into two, one of which is inverted by a polarity inverter 25,
A signal r (= −V (nT / 2)) is formed. −V (nT
/ 2) is expressed by the following equation (5).

−V (nT / 2) = − I (nT / 2) + {− I ((n + 1/4) T / 2) −Q ((n + 1/4) T / 2)} / √2−Q ((n + 1/2) T / 2) + {I ((n + 3/4) T / 2) -Q ((n + 3/4) T / 2)} / {2 (5) where n; 0, 1, 2, ‥ T; 1 / modulation wave frequency.

The signal q (= V (nT / 2)) and the signal r (= −
V (nT / 2)) is input to the P / S converter 26, and the P / S converter 26 synthesizes these signals in chronological order at the timing of the period of the clock c obtained by dividing the sampling clock by four.

For this purpose, the signal s is obtained by the logical product of the signal q and the modulated wave frequency clock d having a period twice as long as the clock c, and the signal r and the modulated wave frequency clock d are obtained.
The signal t is obtained by the logical product of the inverted signal and the signal u.

The signal s is I (nT) + ｛I ((n + 1/8) T) +
Q ((n + 1/8) T)｝ / √2 + Q ((n + 1/4) T) + ｛-I
((n + 3/8) T) + Q ((n + 3/8) T)｝ / √2, and the signal t is −I (n + 1/2) T) + ｛− I ((n
+5/8) T) -Q ((n + 5/8) T)｝ / √2-Q ((n + 3/4)
T) + {I ((n + 7/8) T) -Q ((n + 7/8) T)} / {2, so that the signal u (= DATA (nT))
Is as follows.

DATA (nT) = I (nT) + {I ((n + 1/8) T) + Q ((n + 1/8) T)} / {2 + Q ((n + 1/4) T) + ｛− I (( n + 3/8) T) + Q ((n + 3/8) T) / {2-I (n + 1/2) T) + ｛-I ((n + 5/8) T) -Q ((n + 5/8) T) ｝ / {2-Q ((n + 3/4) T) + {I ((n + 7/8) T) -Q ((n + 7/8) T)} / √2 (6) where n; 0, 1, 2, ‥ T; 1 / modulation wave frequency.

Equation (6) shows that, as shown by the waveform of the signal u in FIG. 3, I (nT) and ｛I ((n + 1/8)
T) + Q ((n + 1/8) T)｝ / √2, Q ((n + 1/4) T),
{-I ((n + 3/8) T) + Q ((n + 3/8) T)} / {2, I
(n + 1/2) T), ｛-I ((n + 5/8) T) -Q ((n + 5/8)
T)｝ / √2, Q ((n + 3/4) T), ｛I ((n + 7/8) T) −
Q ((n + 7/8) T)｝ / √2 indicates that each data is sequentially output in time series, which is the same as the content of the equation (1).

The digital modulation signal u is input to the D / A converter 7 and is converted into an analog signal at the timing of the modulation frequency clock d, and an analog modulation signal is obtained.

As described above, the digital quadrature modulator of the embodiment obtains a digital modulation wave by a combination of a plurality of P / S converters. In this modulator, the multiplier is a P / S converter
It is inserted before 23 and is used only to perform 1 / √2 multiplication on the output of the adder and the subtractor.
The cycle of this multiplication is the same as the cycle of the modulated wave, as shown in FIGS. Therefore, in this modulator, the frequency of the modulated wave can be increased to the same frequency as the maximum operating speed of the multiplier, that is, to about 400 MHz when using a multiplier having 8 bits of operation bits.

[0048]

As is apparent from the above description of the embodiment, the digital quadrature modulator of the present invention can realize digital quadrature modulation by a configuration basically different from that of the conventional device. A modulated wave having the same frequency as the maximum operation speed can be obtained.

The frequency of the modulated wave obtained by the conventional device is
Since the maximum operation speed of the multiplier is limited to 1/8, the digital quadrature modulator of the present invention can obtain eight times the frequency.

Therefore, the filtering process on the signal output from the digital quadrature modulator becomes easier.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital quadrature modulator of the present invention;

FIG. 2 is a timing chart of various signals in the digital quadrature modulator according to the embodiment;

FIG. 3 is a continuation of the timing chart;

FIG. 4 is a block diagram (a) showing a configuration of a conventional digital quadrature modulator, and FIGS. 4 (b) and 4 (c) showing carrier data.

[Explanation of symbols]

 1, 2 Multiplier 3 Counter 4 COS waveform generation ROM 5 SIN waveform generation ROM 6 Adder 7 D / A converter 8 Baseband I signal 9 Baseband Q signal 10 Sampling frequency clock 11 Control signal 12 COS waveform signal 13 SIN Waveform signal 14 I signal 15 Q signal 16 Digital modulation signal 17 Analog modulation signal 18, 23, 24, 26 P / S converter 19 Adder 20 Subtractor 21, 22 Multiplier 25 Polarity inverter

Claims (1)

(57) [Claims] 1. A digital quadrature modulator that converts a digital modulation signal into an analog signal and outputs the analog signal, wherein a first parallel signal that combines a baseband I signal and a baseband Q signal in time order and converts the combined signal into one system signal.
Serial conversion means; first multiplication means for multiplying the sum of the baseband I signal and the baseband Q signal by 1 / √2; and 1 / √ to the subtraction value of the baseband I signal and the baseband Q signal. Second multiplication means for multiplying by two; second parallel-serial conversion means for synthesizing signals output from the first multiplication means and the second multiplication means in time order and converting the signals into one system signal; The first Parallell-Serial conversion means and the second Para
A third Parallel-Seri that combines signals output from the lell-Serial conversion means in time sequence and converts the signals into one system signal
al conversion means, polarity inversion means for outputting a signal obtained by inverting the polarity of the output signal in the third Parallel-Serial conversion means, and a signal output from the third Parallel-Serial conversion means and the polarity inversion means. A digital quadrature modulator comprising: fourth parallel-serial conversion means for combining the signals in time sequence and converting the signals into the digitally modulated signals.