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JPH08116681A - Voltage type inverter - Google Patents

Voltage type inverter

Info

Publication number
JPH08116681A
JPH08116681A JP6248221A JP24822194A JPH08116681A JP H08116681 A JPH08116681 A JP H08116681A JP 6248221 A JP6248221 A JP 6248221A JP 24822194 A JP24822194 A JP 24822194A JP H08116681 A JPH08116681 A JP H08116681A
Authority
JP
Japan
Prior art keywords
circuit
gate
gate signal
short
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6248221A
Other languages
Japanese (ja)
Inventor
Yoshihide Kamanaka
吉秀 鎌仲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP6248221A priority Critical patent/JPH08116681A/en
Publication of JPH08116681A publication Critical patent/JPH08116681A/en
Pending legal-status Critical Current

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  • Inverter Devices (AREA)

Abstract

PURPOSE: To prevent the short circuit of arms even when a gate signal becomes abnormal. CONSTITUTION: The title voltage type inverter concerns an inverter having a main circuit 1 with U- and X-phase arms composed of IGBTs, and a gate circuit 3 whose gate signals on-off-drive both arms. And a short-circuit preventing circuit 5 detects the on operation of the gate signal for the U-phase arm, and makes the gate signal for the X-phase off forcedly. As a result of this, it becomes possible to prevent the simultaneous on operation (short circuit) of the upper and lower arms even in the case of malfunctioning of the control circuit and the gate circuit 3, and in the case of noise entry into the gate signals.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電圧形インバータに係
り、特にゲート制御回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage source inverter, and more particularly to a gate control circuit.

【0002】[0002]

【従来の技術】電圧形インバータを図2に例示する。主
回路1は、半導体スイッチになるIGBTに逆並列に還
流用ダイオードを持つアームU,V,X,Yをブリッジ
構成する。制御装置2は、出力周波数/電圧指令に応じ
て主回路1の各アームU,V,X,Yのオン・オフ制御
信号を発生する。ゲート回路3、4は、オン・オフ制御
信号を増幅して各アームU,V,X,Yを個々にゲート
ドライブする。
2. Description of the Related Art A voltage type inverter is illustrated in FIG. The main circuit 1 has a bridge configuration of arms U, V, X and Y having free wheeling diodes in antiparallel with an IGBT which is a semiconductor switch. The control device 2 generates an on / off control signal for each arm U, V, X, Y of the main circuit 1 according to the output frequency / voltage command. The gate circuits 3 and 4 amplify the on / off control signal to individually gate drive the arms U, V, X, and Y.

【0003】主回路1の半導体スイッチにはパワートラ
ンジスタやFET、GTO、サイリスタなど種々のもの
が置換される。
The semiconductor switches of the main circuit 1 are replaced with various ones such as power transistors, FETs, GTOs and thyristors.

【0004】制御装置2による制御方法は、負荷や電源
の要求に応じてPWM制御や、これにベクトル制御を組
み合わせたものなど種々の方法がある。
As a control method by the control device 2, there are various methods such as PWM control and a combination of this and vector control according to the demand of a load and a power supply.

【0005】また、保護回路として、過電圧保護や過電
流保護回路の他に、主回路1の上下アームの短絡(同時
オン)を防止するために、上下アームに同時にオン信号
が発生しないよう、制御装置2側でゲート信号の加工が
なされる。
In addition to an overvoltage protection circuit and an overcurrent protection circuit, as a protection circuit, in order to prevent a short circuit (simultaneous ON) of the upper and lower arms of the main circuit 1, control is performed so that ON signals are not simultaneously generated in the upper and lower arms. The gate signal is processed on the device 2 side.

【0006】[0006]

【発明が解決しようとする課題】従来の上下アームの短
絡防止方式では、以下の場合のようにゲート信号に異常
が発生した場合にアーム短絡を防止できない。
The conventional short-circuit prevention method for the upper and lower arms cannot prevent the arm short-circuit when an abnormality occurs in the gate signal as in the following cases.

【0007】(1)制御装置2に異常が発生した場合。(1) When an abnormality occurs in the control device 2.

【0008】(2)制御装置2とゲート回路3、4間、
又はゲート回路3、4と主回路のゲート信号線にノイズ
が侵入した場合。
(2) Between the control device 2 and the gate circuits 3 and 4,
Or when noise enters the gate circuits 3 and 4 and the gate signal lines of the main circuit.

【0009】(3)ゲート回路3、4に異常が発生した
場合。
(3) When an abnormality occurs in the gate circuits 3 and 4.

【0010】本発明の目的は、ゲート信号に異常が発生
した場合にもアームの短絡を防止できる電圧形インバー
タを提供することにある。
It is an object of the present invention to provide a voltage source inverter capable of preventing arm short circuit even when an abnormality occurs in a gate signal.

【0011】[0011]

【課題を解決するための手段】本発明は、前記課題の解
決を図るため、半導体スイッチを上下アームとし、ゲー
ト回路のゲート信号によって上下アームをオン・オフ駆
動する電圧形インバータにおいて、前記上下アームの一
方のアームのゲート信号のオンを検出して他方のアーム
のゲート信号をオフに強制する短絡防止回路を備えたこ
とを特徴とする。
In order to solve the above-mentioned problems, the present invention provides a voltage source inverter in which a semiconductor switch is used as upper and lower arms and the upper and lower arms are turned on and off by a gate signal of a gate circuit. It is characterized in that a short circuit prevention circuit for detecting ON of the gate signal of one arm and forcing the gate signal of the other arm to OFF is provided.

【0012】[0012]

【作用】上下アームのゲート信号のオンをそれぞれ検出
して他方のアームのゲート信号をオフに強制することに
より、上下アームの同時オンを防止する。
The on / off of the gate signals of the upper and lower arms is detected and the gate signals of the other arms are forced to be off, thereby preventing the upper and lower arms from being simultaneously turned on.

【0013】[0013]

【実施例】図1は、本発明の一実施例を示す要部回路図
であり、ゲート回路3から主回路1のU,X相のアーム
にゲート信号を印加する部分である。
1 is a circuit diagram of an essential part showing an embodiment of the present invention, which is a part for applying a gate signal from a gate circuit 3 to arms of U and X phases of a main circuit 1.

【0014】IGBTにされるU,X相のアームU,X
のゲートとソース間にはそれぞれ短絡防止回路5、6が
設けられる。
Arms U and X of U and X phases to be IGBT
Short-circuit prevention circuits 5 and 6 are provided between the gate and the source of the circuit, respectively.

【0015】短絡防止回路5は、U相アームUのゲート
信号を取り込み、アームUのオン信号を検出してX相ア
ームXのゲート信号をオフに強制する。同様に、短絡防
止回路6は、X相アームXのゲート信号を取り込み、ア
ームXのオン信号を検出してU相アームUのゲート信号
をオフに強制する。
The short-circuit prevention circuit 5 takes in the gate signal of the U-phase arm U, detects the ON signal of the arm U, and forcibly turns off the gate signal of the X-phase arm X. Similarly, the short-circuit prevention circuit 6 takes in the gate signal of the X-phase arm X, detects the ON signal of the arm X, and forces the gate signal of the U-phase arm U to OFF.

【0016】具体的には、短絡防止回路5に示すよう
に、U相ゲート信号のハイレベルで電流制限抵抗Rを通
して絶縁用のフォトカプラPCの入力発光ダイオードを
駆動し、フォトカプラPCの出力トランジスタのオン動
作によりダイオードD3を通してX相ゲート信号線を短
絡する。ダイオードD1,D2,D3はフォトカプラP
Cの入出力素子を逆電圧から保護する。なお、ダイオー
ドD3には直列に電流制限抵抗を設ける場合もある。
Specifically, as shown in the short circuit prevention circuit 5, the input light emitting diode of the photocoupler PC for insulation is driven at a high level of the U-phase gate signal through the current limiting resistor R, and the output transistor of the photocoupler PC is driven. The X-phase gate signal line is short-circuited through the diode D3 by the ON operation of The diodes D1, D2 and D3 are photocouplers P
Protect the input / output device of C from reverse voltage. A current limiting resistor may be provided in series with the diode D3.

【0017】本実施例において、ゲート回路3は、U,
X相のゲート信号が互いに同時にオンしないよう位相制
御した波形になり、正常なゲート信号であれば上下アー
ムU,Xが同時にオンすることはないが、制御装置2や
ゲート回路3に異常が発生した場合やゲート信号線にノ
イズが発生した場合に短絡防止回路5、6による短絡防
止がなされる。
In this embodiment, the gate circuit 3 includes U,
The waveforms are such that the X-phase gate signals are phase-controlled so that they do not turn on at the same time. If the gate signals are normal, the upper and lower arms U and X will not turn on at the same time, but an abnormality will occur in the control device 2 or the gate circuit 3. In this case or when noise occurs in the gate signal line, the short circuit prevention circuits 5 and 6 prevent short circuits.

【0018】例えば、X相ゲート信号のオン期間にU相
ゲート信号線に誤ったオン信号が発生すると、このオン
信号を短絡防止回路5が検出してX相ゲート信号をオフ
に強制し、アームU,Xの同時オンを抑止する。
For example, when an erroneous ON signal is generated in the U-phase gate signal line during the ON period of the X-phase gate signal, the short-circuit prevention circuit 5 detects this ON signal and forcibly turns OFF the X-phase gate signal, so that the arm The simultaneous turn-on of U and X is suppressed.

【0019】逆に、U相ゲート信号のオン期間にX相ゲ
ート信号線に誤ったオン信号が発生すると、このオン信
号を短絡防止回路6が検出してU相ゲート信号をオフに
強制し、アームU,Xの同時オンを抑止する。
On the contrary, when an erroneous ON signal is generated in the X-phase gate signal line during the ON period of the U-phase gate signal, the short-circuit prevention circuit 6 detects this ON signal and forces the U-phase gate signal to OFF, The simultaneous turn-on of arms U and X is suppressed.

【0020】なお、実施例においては、主回路1の半導
体スイッチを電圧駆動のIGBTとする場合を示すが、
トランジスタなど電流駆動の半導体スイッチ素子を持つ
インバータに適用して同等の作用効果を得ることができ
る。この電流駆動の半導体スイッチの場合には、ベース
電流やゲート電流を遮断又は迂回できる短絡防止回路に
構成される。
In the embodiment, the semiconductor switch of the main circuit 1 is a voltage driven IGBT.
The same effect can be obtained by applying the present invention to an inverter having a current-driven semiconductor switch element such as a transistor. In the case of this current-driven semiconductor switch, it is configured as a short-circuit prevention circuit capable of interrupting or bypassing the base current and the gate current.

【0021】また、実施例では単相インバータの場合を
示すが、3相インバータや多相インバータにおいても各
相単位の上下アームにそれぞれ短絡防止回路を設けて同
様の短絡防止ができる。
In the embodiment, the case of a single-phase inverter is shown, but also in a three-phase inverter or a multi-phase inverter, short-circuit prevention circuits can be provided in the upper and lower arms of each phase unit to prevent the same short-circuit.

【0022】[0022]

【発明の効果】以上のとおり、本発明によれば、電圧形
インバータにおいて、上下アームの一方のアームのゲー
ト信号のオンを検出して他方のアームのゲート信号をオ
フに強制する短絡防止回路を設けたため、ゲート信号に
異常が発生した場合にも上下アームの同時オンを確実に
防止できる効果がある。
As described above, according to the present invention, in the voltage type inverter, the short-circuit prevention circuit for detecting the ON state of the gate signal of one of the upper and lower arms and forcing the gate signal of the other arm to OFF is provided. Since it is provided, even if an abnormality occurs in the gate signal, it is possible to reliably prevent the upper and lower arms from being turned on at the same time.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す要部回路図。FIG. 1 is a circuit diagram of a main part showing an embodiment of the present invention.

【図2】電圧形インバータの回路例。FIG. 2 is a circuit example of a voltage source inverter.

【符号の説明】[Explanation of symbols]

1…主回路 2…制御装置 3、4…ゲート回路 5、6…短絡防止回路 1 ... Main circuit 2 ... Control device 3, 4 ... Gate circuit 5, 6 ... Short circuit prevention circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体スイッチを上下アームとし、ゲー
ト回路のゲート信号によって上下アームをオン・オフ駆
動する電圧形インバータにおいて、 前記上下アームの一方のアームのゲート信号のオンを検
出して他方のアームのゲート信号をオフに強制する短絡
防止回路を備えたことを特徴とする電圧形インバータ。
1. A voltage-type inverter that uses a semiconductor switch as an upper and lower arm and drives the upper and lower arms on / off by a gate signal of a gate circuit, wherein the gate signal of one of the upper and lower arms is detected to be on and the other arm is detected. Voltage source inverter characterized by having a short circuit prevention circuit for forcing the gate signal of the device to turn off.
JP6248221A 1994-10-14 1994-10-14 Voltage type inverter Pending JPH08116681A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6248221A JPH08116681A (en) 1994-10-14 1994-10-14 Voltage type inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6248221A JPH08116681A (en) 1994-10-14 1994-10-14 Voltage type inverter

Publications (1)

Publication Number Publication Date
JPH08116681A true JPH08116681A (en) 1996-05-07

Family

ID=17174984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6248221A Pending JPH08116681A (en) 1994-10-14 1994-10-14 Voltage type inverter

Country Status (1)

Country Link
JP (1) JPH08116681A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006166676A (en) * 2004-12-10 2006-06-22 Sumitomo Electric Ind Ltd Protective device and power control device incorporating the protective device
JP2015076989A (en) * 2013-10-09 2015-04-20 日立オートモティブシステムズ株式会社 Protection circuit, delay circuit and inverter device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006166676A (en) * 2004-12-10 2006-06-22 Sumitomo Electric Ind Ltd Protective device and power control device incorporating the protective device
JP2015076989A (en) * 2013-10-09 2015-04-20 日立オートモティブシステムズ株式会社 Protection circuit, delay circuit and inverter device

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