JPH08116502A - Video display - Google Patents

Abstract

(57) [Abstract] [Purpose] A television image display device for a computer system without requiring a special type of display capable of supporting the frequency of a television synchronizing signal or a frame memory for the television image. To display. [Structure] A video signal converter 72 converts a television video signal S1 into a video signal S2 applicable to a display device of a personal computer. Video signal converter 72
Can convert a video signal for one line into a video signal for two lines by using a FIFO memory for two lines. The command video generation unit 74 generates a video signal S3 representing a key command image for selecting a television channel and adjusting the volume. The multiplexer 76 synthesizes these two video signals S2 and S3 and displays the television image and the key command image on the monitor. Television video signal S
If 1 is not input, the key command image is displayed on the monitor using the preliminary synchronization signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device used in a computer system having a display device and a display control unit to display a television image on the display device.

[0002]

2. Description of the Related Art In recent years, personal computers capable of displaying television images on monitors have become widespread. FIG. 19 is an explanatory diagram showing display examples of television images on two types of personal computers. In the first type, as shown in FIG. 19A, a mode in which a television image is displayed on the entire screen of the monitor and a mode in which a computer image is displayed are switched. In the second type, as shown in FIG.
The television image is displayed in one window of the computer image.

[0003]

In the type in which the image display mode is switched as shown in FIG. 19A, the television signal is usually given to the monitor as it is when the television image is displayed. . However, this type of personal computer has a problem in that a special multi-scan display capable of handling both a television signal and a computer video signal must be used. That is, since the frequency of the horizontal synchronizing signal of the television signal is about 15 kHz and the synchronizing signal of the video signal of the computer is about 30 kHz, a relatively expensive multi-scan display capable of supporting both of them has been required.

On the other hand, as shown in FIG. 19B, a computer system of the type that displays a television image in a window requires a dedicated frame memory for storing the video data of the television image. There was a problem.

The present invention has been made in order to solve the above-mentioned problems in the prior art, and is a special display of a type that can cope with the frequency of a synchronizing signal of a television and a frame memory for a television image. It is an object of the present invention to provide a video display device capable of displaying a television image on a display device of a computer system without requiring the above.

[0006]

In order to solve the above problems, the video display apparatus according to claim 1 of the present invention is used in a computer system having a display device and a display controller, and is used in a television. A video display device for displaying an image on the display device, wherein one scanning line segment of the first synchronization signal is based on a first video signal representing a television image and the first synchronization signal. During the period, a video signal converter that generates the second video signal by repeatedly generating the first video signal for one scanning line twice, and a command key including a plurality of command keys for operating the television. By outputting while switching between the command key video signal and the second video signal, a command video generation unit for generating a command key video signal representing an image, A video mixer section for generating a third video signal representing a video in which a command key image and the television image are combined, and a second synchronization for synchronizing with the second video signal based on the first synchronization signal. A second synchronization signal generation unit for generating a signal; a preliminary synchronization signal generation unit for generating a preliminary synchronization signal substantially equivalent to the first synchronization signal; and an input terminal for the first synchronization signal and the preliminary synchronization signal. Each of them is provided, and when the first synchronization signal is given, the first synchronization signal is selected and given to the second synchronization signal generation unit, while the first synchronization signal is not given. In this case, a synchronization signal selection unit for selecting the preliminary synchronization signal and giving it to the second synchronization signal generation unit is provided.

The video converting section repeatedly generates the video signal of the same scanning line twice during one scanning line of the television image, thereby generating the second video signal applicable to the display device of the computer system. Can be generated. Further, by displaying the command key image on a part of the television image, the user can easily perform operations such as channel selection and volume adjustment of the television image. Further, since the second synchronization signal is created from the preliminary synchronization signal when the first synchronization signal is not input, the command key image is displayed on the display device even when the first synchronization signal is not input. Can be displayed.

A video display device according to a second aspect is a video display device for use in a computer system having a display device and a display control unit, for displaying a television image on the display device. Based on a first video signal representing a television image and the first sync signal, the first video signal for one scan line is changed to 2 during the period for one scan line of the first sync signal. A video signal conversion unit that repeatedly generates twice to generate a second video signal; a command video generation unit that generates a command key video signal representing a command key image including a plurality of command keys for operating a television; An image in which the command key image and the television image are combined by switching and outputting the command key image signal and the second image signal. A video mixer unit for generating a third video signal representing the second to generate a second synchronizing signal synchronized with the second video signal based on said first synchronization signal
A synchronization signal generation unit; a preliminary synchronization signal generation unit that generates a preliminary synchronization signal substantially equivalent to the second synchronization signal;
Input terminals for the sync signal and the preliminary sync signal, respectively, and when the second sync signal is given, the second sync signal is selected and given to the display device, while the second sync signal is given. A synchronization signal selecting section for selecting the preliminary synchronization signal and supplying it to the display device when the synchronization signal is not supplied.

According to the second aspect of the present invention, the command key image can be displayed on the display device by using the preliminary synchronization signal when the first synchronization signal is not input.

In the video display device according to the third aspect, the command video generation section stores a first frame memory for storing the command key video signal and a second frame memory for storing a switching signal supplied to the video mixer section. Of the command key video signal from the first frame memory by supplying a common read address to the frame memory and the first and second frame memories.
An address generation unit for reading the switching signal from the second frame memory.

With this configuration, the command key image can be easily displayed in a desired area on the screen of the display device.

A video display device according to a fourth aspect is a video display device for use in a computer system having a display device and a display control unit and displaying a television image on the display device. Based on the first video signal of the interlaced scan representing the image and the first sync signal, the first video signal of one scan line is changed to 2 during the period of one scan line of the first sync signal. A video signal conversion unit that repeatedly generates twice to generate a second video signal, and a frequency that is twice the frequency of the first horizontal synchronization signal included in the first synchronization signal based on the first synchronization signal. A horizontal synchronization signal generation unit that generates a second horizontal synchronization signal, and a second synchronization signal that has the same frequency as the first vertical synchronization signal included in the first synchronization signal based on the first synchronization signal. In order to generate a vertical synchronizing signal, a starting point of one pulse of the first vertical synchronizing signal is detected, and then one pulse of the second vertical synchronizing signal is generated in synchronization with the second horizontal synchronizing signal. A vertical synchronization signal generator that
It is characterized by including.

The first video signal for interlaced scanning is
In contrast to the signal in which scanning is performed by shifting one scanning line between the odd field and the even field, the second video signal is a non-interlaced scan in which each scanning line of the first video signal is repeated twice. Signal. When the second video signal is displayed on the display device in synchronization with the sync signals generated by the horizontal sync signal generator and the vertical sync signal generator, the scan lines of the odd field and the even field in the first video signal are displayed. The gap is displayed as it is. As a result, the image of each scanning line on the display device is temporally interpolated, and the image quality is improved.

According to a fifth aspect of the present invention, in the video display device, the video signal converting section includes two line memories for respectively storing the first video signals for one scanning line and the two line memories for video. A write line memory for writing a signal and a read line memory for reading a video signal are alternately and complementarily switched, and the first line signal is synchronized with the first clock signal in response to the first clock signal. While writing one video signal to the write line memory, control is performed to read the second video signal from the read line memory in response to a second clock signal synchronized with the second synchronization signal. And a control unit.

In this way, the second video signal applicable to the display device of the computer system is generated by using the plurality of line memories without using the frame memory for storing the video signal of the television. You can

[0016]

【Example】

A. Overall Configuration of Computer System: FIG. 1 is a block diagram showing the configuration of a personal computer system equipped with a video display device according to an embodiment of the present invention.
This computer system includes a CPU 20 and a RAM 2
2, a ROM 24, an I / O interface 26, and a video RAM (VRAM) 28 as a frame memory.
A first video control unit 30 for controlling writing and reading of video stored in the VRAM 28, and a video display unit 40 for controlling display of a television image.
A keyboard 50 and a mouse 52 as input means and a remote control transmitter 54 as television image operation means are connected to the I / O interface 26. In addition, the video display unit 40 includes a speaker 60.
And a color monitor (color display) 62 are connected. The color monitor 62 includes the first video controller 3
Horizontal sync signal of video signal (approx. 30kHz)
z) as long as it is compatible with a horizontal synchronizing signal (about 15 kHz) of a normal television video signal. The color monitor 62 is a color C
Various display devices such as RTs and color liquid crystal displays can be used.

The image display unit 40 corresponds to the image display device of the present invention. The first video control unit 30 corresponds to the display control unit, and the color monitor 62 corresponds to the display device.

The video display unit 40 includes an external video input unit 41 that receives a video signal from a video player, a television video input unit 42 that receives a television signal, and a second video control unit that processes the input video signal. 44, an audio control unit 46 for reproducing audio, and a video switch 48. CPU bus 21 connected to CPU 20
Is the television image input unit 42 and the second image control unit 4
4, the audio control unit 46, and the video switch 48. In addition, "video signal" in this specification
There are cases where a sync signal is included (a video signal in a broad sense) and cases where a sync signal is not included (a video signal in a narrow sense).

[0019] Television tuning and volume control, and
Operations such as switching between television and video can be performed using the remote control transmitter 54.

The second video control unit 44 includes an external video input unit 4
One of the video signal SVV input from 1 and the video signal STV input from the television video input unit 42 is selected, and the video signal is converted into a video signal SV applicable to the color monitor 62. The audio control unit 46 selects one of the audio signal SVS input from the external video input unit 41 and the audio signal STS input from the television video input unit 42, controls the volume thereof, and controls the speaker 60. The audio signal SS is supplied. Video switch 48
Is the video signal SV output from the second video control unit 44.
And one of the video signals SPC output from the first video control unit 30 and select the selected video signal SD from the color monitor 6
Supply to 2. These video signals SV, SPC, S
Each of D includes a video signal and a sync signal (vertical sync signal and horizontal sync signal) in a narrow sense. A selection signal SEL indicating selection in the video switch 48 is supplied from the CPU 20 to the video switch 48 via the CPU bus 21. Since the video switch 48 does not require high-speed switching, an electromagnetic relay can be used as the video switch 48.

B. Internal configuration of second video control unit 44: FIG.
FIG. 4 is a block diagram showing an internal configuration of the second video control unit 44. The second video controller 44 includes a video switch 70,
The video signal converter 72, the command video generator 74, the multiplexer 76, and the AND circuit 78 are included.
The video switch 70, the video signal converter 72, and the command video generator 74 are connected to the CPU bus 21. The multiplexer 76 corresponds to the video mixer section in the present invention. Instead of the multiplexer 76, a tri-state buffer is provided at each output section of the video signal conversion section 72 and the command video generation section 74, and these tri-state buffers are complementarily switched to achieve the same function as that of the multiplexer 76. It can also be realized.

The video switch 70 has an external image input section 4
One of the video signal SVV input from 1 and the video signal STV input from the television video input unit 42 is selected.
The video signal converter 72 converts the video signal S1 given from the video switch 70 into a video signal S2 which is synchronized with a sync signal which is almost equivalent to the sync signal of the personal computer. The command video generation unit 74 uses the remote control transmitter 54, the keyboard 50, the mouse 52 and the like to generate a key command image for performing operations such as television channel selection and volume adjustment on the screen. The multiplexer 76 switches the video signal S2 output from the video signal conversion unit 72 and the video signal S3 output from the command video generation unit 74 for each pixel to display a television image and a key command image in one screen. To synthesize. A switching signal PIPSW to the multiplexer 76
Is given from the command video generation unit 74.

C. Internal Configuration and Operation of Video Signal Converter 72: FIG. 3 is a block diagram showing the internal configuration of the video signal converter 72 shown in FIG. As shown in FIG. 3A, the video signal conversion unit 72 includes a video decoder 80, an AD converter 82, a FIFO memory unit 84, a DA converter 86, and a control unit 88. ing. Video decoder 8
0 decodes the composite video signal S1 given from the video switch 70 (FIG. 2) to generate the component video signals NR, NG and NB of RGB three colors, the vertical synchronizing signal NV and the horizontal synchronizing signal NH. Since these synchronizing signals NV and NH are signals synchronized with the television image, the frequency of the vertical synchronizing signal is about 60 Hz and the frequency of the horizontal synchronizing signal is about 15 kHz. The control unit 88 uses the first synchronizing signals NV and NB to generate the second synchronizing signal VV, which is almost equivalent to the synchronizing signal of the personal computer.
Generate VH. The frequency of the sync signal of the personal computer is, for example, about 6 for the vertical sync signal (VSYNC).
0 Hz, the horizontal synchronizing signal (HSYNC) is about 30 kHz. The second vertical synchronizing signal VV is the first vertical synchronizing signal N.
It has the same frequency as V and has a second horizontal synchronizing signal VH
Has a frequency twice that of the first horizontal synchronizing signal NH. The internal configuration of the control unit 88 will be described later.

When processing a digital video signal of a moving picture supplied from a CD-ROM or the like, FIG.
As shown in, the moving picture decompression unit 81 may be provided instead of the decoder 80 and the AD converter 82.

Component video signals NR, NG, NB
Is converted from an analog signal to a digital signal by the AD converter 82, and the digital video signal NRGB is F
It is provided to the IFO memory unit 84. The FIFO memory unit 84 and the control unit 88 use the second synchronization signal VV,
The digital video signal VRGB synchronized with VH is generated, and this function will be described later. The digital video signal VRGB thus obtained is converted into analog video signals VR, VG, VB by the DA converter 86. The analog video signals VR, VG, and VB are used as the second synchronization signal V
If the color monitor 62 is supplied with V and VH, a television image can be displayed on the color monitor 62. The conversion timing in the DA converter 86 is defined by the clock signal VCLK provided from the control unit 88.

When a liquid crystal display is used as the color monitor 62, the D / A converter 86 is bypassed, and the digital video signal NRGB is directly output from the video signal conversion section 72.

FIG. 4 is a block diagram showing the internal structure of the FIFO memory unit 84 shown in FIG. The FIFO memory unit 84 includes two FIFO memories 91 and 92.
And these are virtual toggle switches 9
3, 94 are complementarily and alternately switched. Two
Each of the FIFO memories 91 and 92 is a line memory that stores a digital video signal for one scanning line. The memory used for storing the video signal of the television in the video display unit 40 is a FIFO for two lines.
Since only the O memories 91 and 92 are required, there is an advantage that the required memory capacity is smaller than that of the device using the frame memory.

The virtual toggle switches 93 and 94 have a function of switching the input and output of the two FIFO memories 91 and 92 complementarily and alternately by the input enable signal RE and the output enable signal OE provided from the control unit 88. Is an equivalent circuit showing. Two FIFO memories 91, 9
The input clock signal NCLKI and the output clock signal VCLK are commonly supplied to the input terminal 2.

FIG. 5 is a timing chart showing the operation of the video signal converter 72 shown in FIG. FIG. 5 (a),
The first and second vertical synchronizing signals NV shown in (b) have the same frequency. The frequency of the second horizontal synchronizing signal VH shown in FIG. 5 (g) is about 30 kHz, and FIG.
The frequency of the first horizontal synchronizing signal NH shown in (
z) twice.

Since the television signal is interlaced, as shown in FIG. 5A, an even field and an odd field alternately appear for each pulse of the vertical synchronizing signal NV. 5E to 5H show the operation during a period corresponding to a plurality of lines (scanning lines) in one field. That is, FIG. 5E shows the first horizontal synchronizing signal NH, and FIG. 5F shows the digital video signal NRGB written in the FIFO memory unit 84.
Shows the R component NR of. 5 (g) shows the second horizontal synchronizing signal VH, and FIG. 5 (h) shows the FIFO.
The R component VR of the digital video signal VRGB read from the memory unit 84 is shown. Note that FIG.
The characters "1L" and "2" described in (f) and (h)
“L” and the like indicate the first line, the second line, and the like, respectively.

The first period T1 shown in FIGS. 5 (e) to 5 (h).
In, the video signal of the second line is written in the first FIFO memory 91, while the video signal of the first line is read twice from the second FIFO memory 92. In the period T2, the video signal of the third line is written in the second FIFO memory 92,
Meanwhile, the video signal of the second line is the first FIFO
It has been read twice from the memory 91.

FIGS. 5 (i) to 5 (n) show a period T2 in which the writing of the third line and the reading of the second line are performed.
The operation of a part of is shown enlarged. 5 (k) is 2
The input clock signal NCLK applied to the two FIFO memories 91 and 92 is shown, and FIG. 5 (n) shows the output clock signal VCLK. 5 (j) and (m) are
In synchronization with clock signals NCLK and VCLK,
The figure shows how the values of the video signals NR and VR change for each pixel. In this embodiment, the output clock signal V
The frequency fVCLK of CLK is set to twice the frequency fNCLK of the input clock signal NCLK, and as a result, reading of two pixels is performed during writing of one pixel. As a result, the video signal of the previous line is read twice during the writing of one line (FIG. 5 (f)) (FIG. 5).
(H)).

Generally, if the relationship of fVCLK = M * fNCLK (M is an integer) is set, the video signal of the preceding line can be read M times during the writing of one line. At this time, the frequency fVH of the second horizontal synchronizing signal VH
Also, the set value of the PLL circuit in the control unit 88 is set to be M times the frequency fNH of the first horizontal synchronizing signal NH.

The output of the crystal oscillator having a frequency eight times the frequency fsc (3.58 MHz) of the color subcarrier of the NTSC signal is used as the output clock signal VCLK, and this output clock signal VCLK is divided by two. The input clock signal NCLK having the frequency 4fsc may be generated. Alternatively, the clock signal used in the video decoder 80 is used as the input clock signal NCLK, and this input clock signal NCLK is used by using the PLL circuit.
Output clock signal VCL having twice the frequency of CLK
It is also possible to generate K. Further, the second horizontal synchronizing signal VH can be generated using a counter that generates one pulse each time the number of pulses of the output clock signal VCLK is counted by a predetermined number.

As described above, the writing and reading of the video signal are simultaneously performed while the two FIFO memories 91 and 92 are alternately and complementarily switched for each input of the video signal for one line. , A video signal (FIG. 5 (h)) synchronized with the second horizontal synchronizing signal VH can be generated. The second horizontal synchronizing signal VH is supplied to the display controller (first video controller 3 shown in FIG. 1) of the personal computer.
0) has a frequency (about 30 kHz) substantially equivalent to the horizontal synchronizing signal generated by the above (0), the video signal VRGB synchronized with the second horizontal synchronizing signal VH is supplied to the color monitor 62 for a personal computer. For example, the television image can be displayed on the color monitor 62.

D. Internal structure and operation of the command video generation unit 74: When a television image is displayed on almost the entire screen of the color monitor 62, the remote control transmitter 5
4 (FIG. 1) is used to select a television channel and adjust the volume. However, it is convenient if the mouse 52 and the keyboard 50 can be used for tuning and volume control without using the remote control transmitter 54. Therefore, in this embodiment, an image of a key command for selecting a channel and adjusting the volume is generated by the command video generation unit 74 (FIG. 2) and displayed on the color monitor 62.

FIG. 6 is a block diagram of the command image generator 7 shown in FIG.
FIG. 4 is a block diagram showing an internal configuration of the fourth embodiment. The command video generation unit 74 has a vertical counter 102, a command video memory 104, a horizontal counter 106, and a command memory control unit 108.

FIGS. 7A and 7B are explanatory views showing some examples of key command images stored in the command video memory 104. In the key command image of FIG. 7A, a button (key) for selecting channels 1 to 12, a button for up / down channel, and one of three video input sources are selected. It has a button for operating and a button for adjusting the volume. In the key command image of FIG. 7B, the tuning buttons and the volume control buttons are arranged in a horizontal row corresponding to the function keys of the keyboard 50. Figure 7
If a key command image close to the key layout of the remote control transmitter 54 is used as in (A), there is an advantage that the user can easily operate. On the other hand, if the buttons (keys) are arranged so as to correspond to the function keys as shown in FIG. 7B, the user can easily memorize the function keys for tuning and adjusting the volume. There is an advantage that tuning and volume adjustment can be easily performed without displaying the key command image.

The command video memory 104 is, for example, as shown in FIG.
First frame memory 104R for three planes for storing the key command image of (A) as a color image,
It has 104G and 104B and 1 plane 2nd frame memory 104P for storing the switching signal PIPSW to give to the multiplexer 76 (FIG. 2).
3-plane frame memories 104R and 10 for RGB
Each of 4G and 104B has a depth of 1 bit, and data of 3 bits for each pixel represents 8 colors.

The vertical counter 102 is a circuit for generating the vertical address of the command video memory 104. The reset terminal receives the second vertical synchronizing signal VV and the clock input terminal receives the second horizontal synchronizing signal VH. It has been entered. The horizontal counter 106 is the command video memory 104.
The second horizontal synchronizing signal VH is input to the reset terminal and the output clock signal VCLK which is also supplied to the FIFO memory unit 84 (FIG. 4) is input to the clock input terminal. Has been entered. The vertical counter 102 and the horizontal counter 106 correspond to the address generator in the present invention. The addresses generated by these counters 102 and 106 are
It is commonly given to each plane of the command video memory 104.

FIG. 8 is an explanatory diagram showing the relationship of various images in the second image controller 44 (FIG. 2). The television image signal S1 input to the image signal converting section 72 (see FIG.
(A)) and the converted video signal S2 (FIG. 8 (B)) represent substantially the same video. However, the television video signal S1 before conversion is interlaced scanning, whereas the video signal S2 after conversion is non-interlaced scanning. As shown in FIG. 8C, the command video memory 104 stores the video of the key command shown in FIG. 7A or 7B in a partial area of the frame memory. The area where the key command is displayed (key command display area) and the area where the moving picture is displayed (moving picture display area) on the screen of the color monitor 62 are stored in the fourth plane 104P of the command video memory 104. They are distinguished by the switching signal PIPSW. That is,
The switching signal PIPSW is set to 1 level in the key command display area, and the switching signal PIPSW is set to 0 level in the moving image display area MPA.

Vertical counter 1 of command image generation unit 74
02 and the horizontal counter 106 display the second synchronization signals VV and V.
A vertical address and a horizontal address of the command video memory are generated according to H and the clock signal VCLK. From the command video memory 104, a key command video signal Y representing a key command image according to these addresses.
R, YG, YB and the switching signal PIPSW are read. The switching signal PIPSW is the AND circuit 78 shown in FIG.
Has been entered in. The AND circuit 78 also receives the second switching signal SSW given from the CPU 20 via the CPU bus 21.

When the key command image is displayed on the color monitor 62, the CPU 20 sets the second switching signal SSW to 1
Set to level. In this case, the first switching signal PIPSW output from the command video generation unit 74 is ANDed.
It passes through the circuit 78 as it is and is given to the multiplexer 76. Therefore, in the area where the first switching signal PIPSW is at 1 level (that is, the key command display area), the key command video signal S3 is selected and output to the color monitor 62, and the area where the first switching signal PIPSW is at 0 level (that is, In the video display area), the video signal S2 of the television
Is selected and output. As a result, the television image and the key command image are combined and displayed on the color monitor 62, as shown in FIG. When the user operates a key or button of the key command image using the keyboard 50 or the mouse 52, a routine for accepting the key command is started, the key input is discriminated, and operations such as channel selection and volume adjustment are executed.

On the other hand, the key monitor image is displayed on the color monitor 6
If not displayed on the CPU 2, the CPU 20 sets the second switching signal SSW to the 0 level. In this case, since the multiplexer 76 always selects and outputs the television video signal S2, only the television video is displayed on the color monitor 62, as shown in FIG.

The command memory control unit 108 uses the C
Command video memory 104 according to a command from the PU 20
Work to rewrite the video signal inside. By this rewriting operation, the key command image is changed from FIG. 7A to FIG.
It is possible to change to (B) or change the position of the key command image to an arbitrary position on the screen.

As described above, in this embodiment, since the key command image and the television image are combined and displayed, even when the television image is displayed on almost the entire screen, the remote control transmitter is displayed. Instead of using 54, input means for a personal computer, such as a keyboard 50 and a mouse 52, can be used to perform television channel selection and volume adjustment.

E. Internal configuration and operation of control unit 88: FIG.
4 is a block diagram showing an internal configuration of a control unit 88 shown in FIG. The control unit 88 uses the I ² C controller 110.
(“I ² C” is a trademark of Philips), a preliminary sync signal generator 112, a switch 114, and a sync signal converter 116. The I ² C controller 110 is
It is connected to the decoder 80 via the I ² C bus, detects whether the television video signal S1 is input to the decoder 80, and sets the value of an internal flag (not shown). The CPU 20 monitors the flag in the I ² C controller 110 by an interrupt every 100 ms, and outputs a switching signal SW for switching the switch 114. The switch 114 responds to the switching signal SW by either one of the synchronization signals NV1 and NH1 (first synchronization signal) given from the decoder 80 and the preliminary synchronization signals NV2 and NH2 given from the preliminary synchronization signal generator 112. To output. The preliminary synchronizing signals NV2 and NH2 generated by the preliminary synchronizing signal generator 112 are signals having the same cycle as the synchronizing signal of the television video signal.

The television image signal S1 is sent to the decoder 80.
Is input, that is, when the synchronizing signals NV1 and NH1 are supplied from the decoder 80 to the switch 114, the switch 114 outputs the synchronizing signals NV1 and NH1.
, NH1 are selected and output. On the other hand, when the television video signal S1 is not input to the decoder 80, the switch 114 selects and outputs the preliminary synchronization signals NV2 and NH2 provided from the preliminary synchronization signal generator 112. In the configuration shown in FIG. 9, the I ² C controller 1
The CPU 10, the CPU 20, and the switch 114 correspond to the synchronization signal selection unit in the present invention.

The sync signal converter 116 includes a switch 114.
The sync signals VV and VH for the color monitor 62 are generated based on the sync signals NV and NH given from the above. The internal structure of the synchronization signal converter 116 will be described later.

If the control unit 88 shown in FIG. 9 is used, the sync signal conversion unit 116 generates the sync signals VV and VH for the color monitor 62 even when the television video signal S1 is not input to the decoder 80. As a result, the key command image can be displayed on the color monitor 62. Therefore, even when the television video signal S1 is not supplied to the computer system, there is an advantage that the user can operate the keys and buttons on the key command image displayed on the color monitor 62.

FIG. 10 is a block diagram showing a second configuration of the control unit 88. The decoder 80 in FIG. 10 outputs a switching signal SW indicating whether or not the normal television video signal S1 is input. Therefore, this switching signal S
By supplying W to the switch 114, the same function as in FIG. 9 can be exhibited without the I ² C controller 110. In the configuration shown in FIG. 10, the decoder 80 and the switch 114 configure the synchronization signal selection unit in the present invention.

FIG. 11 is a block diagram showing a third configuration of the control unit 88. In the configuration shown in FIG. 11, the synchronization signal converter 116 outputs the synchronization signals NV1,
A sync signal VV for the color monitor 62 based on NH1
1 and VH1 are created. In addition, the preliminary synchronization signal generator 11
Reference numeral 8 designates preliminary sync signals VV2 and VH for the color monitor 62.
Raises 2. Then, the switch 114 selects and outputs one of these two sets of synchronization signals. The control unit shown in FIG. 11 also has the same effect as the control unit shown in FIGS. 9 and 10.

F. Internal Structure and Operation of Sync Signal Converter 116: FIG. 12 is a block diagram showing the internal structure of the sync signal converter 116 shown in FIGS. 9 to 11. The synchronization signal conversion unit 116 includes a PLL circuit 120, a display system horizontal synchronization signal generation unit 122, and a display system vertical synchronization signal generation unit 124.
And a 1/2 frequency divider 126 and a delay circuit section 128. The PLL circuit 120 generates the output clock signal VCLK based on the horizontal synchronization signal NH output from the switch 114 (FIG. 9) in the control unit 88. The output clock signal VCLK is a signal having a frequency that is eight times the frequency fsc (3.58 MHz) of the color subcarrier of the NTSC signal, and is output from the control unit 88 to the command video generation unit 74.
(FIG. 2) and the FIFO memory unit 84 (FIG. 4). The frequency divider 121 in the PLL circuit 120
It is also possible to change the frequency of the output clock signal VCLK by changing the setting value of the CPU 20. The ½ frequency divider 126 outputs the output clock signal V
CLK is divided in half and the input clock signal NCLK
Generate This input clock signal NCLK is used as a write clock signal for the FIFO memory unit 84, as shown in FIG.

The display system horizontal sync signal generator 122 is
SC system horizontal synchronizing signal NH and output clock signal VCLK
Then, the horizontal synchronizing signal MH of the display system is generated. FIG.
FIG. 3 is a block diagram showing an internal configuration of a display system horizontal synchronization signal generator 122. The horizontal sync signal generator 122
A reset signal generation circuit 130, a first pulse width counter 132, a synchronization period counter 134, a second pulse width counter 136, an AND circuit 138, and an EXOR circuit 140 are provided.

FIG. 14 shows the display system horizontal synchronizing signal generator 12.
6 is a timing chart showing the operation of No. 2. The reset signal generation circuit 130 is an edge detection circuit that detects the falling edge of the NTSC system horizontal synchronization signal NH in synchronization with the output clock signal VCLK. That is, FIG.
As shown in (a) to (c), the reset signal generation circuit 1
Reference numeral 30 detects a falling edge of the NTSC system horizontal synchronizing signal NH and generates a reset signal RES having a pulse width of one cycle of the output clock signal VCLK. This reset signal RES indicates that the three counters 132, 134, 1
When applied to the reset terminals of 36, the outputs H1, H2, H3 of the three counters are reset to the L level.

The first pulse width counter 132 has a period P of L level of the display system horizontal synchronizing signal MH (FIG. 14 (g)).
Count 1 (ie pulse width). The first pulse width counter 132 starts counting the number of pulses of the output clock signal VCLK when reset by the reset signal RES, and outputs the output H1 when counting a predetermined number of pulses corresponding to the pulse width P1 of the horizontal synchronizing signal MH. To H
Start up to the level (Fig. 14 (d)). The synchronization period counter 134 is enabled when the output H1 of the first pulse width counter 132 becomes H level, and starts counting the number of pulses of the output clock signal VCLK. Then, when a predetermined number of pulses corresponding to a period P2 obtained by removing the pulse width P1 from one cycle T of the display system horizontal synchronization signal MH is counted, the output H2 thereof rises to H level (FIG. 14).
(E)). The second pulse width counter 136 is enabled when the output H2 of the synchronization period counter 134 becomes H level, starts counting the number of pulses of the output clock signal VCLK, and counts a predetermined number of pulses corresponding to the pulse width P1. The output H3 is raised to H level (FIG. 14 (f)). The AND circuit 138 takes the logical product of the inverted signal of the output H3 of the second pulse width counter 136 and the output H2 of the synchronization period counter 134. Also, EXO
The R circuit 140 generates the display system horizontal synchronization signal MH by taking the exclusive OR of the output of the AND circuit 138 and the output H1 of the first pulse width counter 132. As a result, the display system horizontal synchronization signal MH having a cycle T that is 1/2 the cycle of the NTSC system horizontal synchronization signal NH (FIG. 14A).
(FIG. 14 (g)) is obtained. Three counters 1
The setting value of the count number at 32, 134, 136 is
It can be changed by the CPU 20.

As shown in FIG. 12, this display system horizontal synchronizing signal MH is delayed by a few pulses of the output clock signal VCLK in the delay circuit section 128 and is supplied to the color monitor 62 as the display system horizontal synchronizing signal VH. Become. The delay circuit unit 128 is a shift register in which a plurality of flip-flops are connected. The display system horizontal synchronizing signal is delayed by slightly shifting the falling timing of the display system horizontal synchronizing signal VH from the falling timing of the display system vertical synchronizing signal VV so that the color monitor 62 can achieve good synchronization. To do so. The delay circuit unit 128 can be omitted. That is,
The unsynchronized horizontal synchronizing signal MH is a signal substantially equivalent to the final horizontal synchronizing signal VH.

FIG. 15 shows the display system vertical synchronizing signal generator 12.
FIG. 4 is a block diagram showing an internal configuration of the fourth embodiment. The vertical synchronizing signal generator 124 includes an inverter 150, three D-type flip-flops 151 to 153, a NAND circuit 154.
It has and. Three D-type flip-flops 151-
The pre-delayed horizontal synchronizing signal MH generated by the display system horizontal synchronizing signal generator 122 is applied to the clock input terminal of 153. D of the first D-type flip-flop 151
A signal obtained by inverting the NTSC vertical synchronizing signal NV by the inverter 150 is applied to the input terminal.
The output Q1 of the first D-type flip-flop 151 is the second
Of the second D-type flip-flop 152, and the output Q2 of the second D-type flip-flop 152 is applied to the D-input terminal of the third D-type flip-flop 153. The NAND circuit 154 has a first
Output Q1 of the D-type flip-flop 151 of
The inverted output Q3 of the type flip-flop 153 is given, and the vertical synchronizing signal VV of the display system is output.

FIG. 16 shows the display system vertical synchronizing signal generator 12.
4 is a timing chart showing the operation of No. 4 in FIG. After the vertical synchronizing signal NV of the NTSC system falls, the horizontal synchronizing signal MH
The vertical synchronizing signal VV of the display system falls in synchronism with. The pulse width of the vertical sync signal VV of the display system is two cycles of the horizontal sync signal MH. This is based on the fact that the pulse width of the vertical synchronizing signal is defined as two cycles of the horizontal synchronizing signal in the VGA standard which is the standard of the video signal of the computer. Since the vertical sync signal NV of the NTSC system has a pulse width of two cycles or more of the horizontal sync signal VH of the display system, the display system vertical sync signal generator 124 outputs V.
The vertical synchronizing signal VV compliant with the GA standard is generated. The falling timing of the display system vertical synchronization signal VV is synchronized with the horizontal synchronization signal MH with a delay of several cycles of the display system horizontal synchronization signal MH after the fall of the NTSC system vertical synchronization signal NV. You may make it fall.

FIG. 17 is a timing chart showing the operation of displaying the odd and even fields of an NTSC television image in accordance with the display system synchronizing signals VV and VH. Note that FIG. 17 shows the details of the operation shown in FIG. 5 regarding the relationship between the odd field and the even field.

In the odd field, as shown in FIG.
As shown in (b), the edge of the NTSC vertical synchronizing signal NV is synchronized with the pulse of the horizontal synchronizing signal NH. On the other hand, in the even field, as shown in FIGS. 17 (g) and 17 (h), the edge of the vertical synchronizing signal NV of the NTSC system deviates from the pulse of the horizontal synchronizing signal NH by a half of the cycle of the horizontal synchronizing signal NH. ing. FIG. 17C shows the timing of the digital video signal NRGB in the odd number field, and the video signal representing the video from the first scanning line to the first half of the 263rd scanning line (denoted as “263f”) is It has occurred. Also, FIG. 17I shows the timing of the digital video signal NRGB in the even field, and the video signal representing the video from the second half of the 263rd scanning line (denoted as “263s”) to the 525th scanning line. Is occurring. As can be seen by comparing FIGS. 17 (c) and 17 (i), with reference to the vertical synchronization signal NV,
The video in the odd-numbered field and the video in the even-numbered field are shifted by 1/2 of one cycle of the horizontal synchronizing signal NH. Since one cycle of the horizontal synchronizing signal NH corresponds to two scanning lines on the screen of the television, a shift of 1/2 of one cycle corresponds to one scanning line.

As described with reference to FIG. 5, in the computer system of this embodiment, the color monitor 62 is non-interlaced by using the horizontal sync signal VH of the display system having a frequency twice the horizontal sync signal NH of the NTSC system. The display is made by scanning. That is, in FIG.
As can be seen by comparing (c) and (f), in the period of one scanning line of the image signal NRGB of the NTSC system, the same image regarding the scanning line immediately before is repeated twice and the color monitor 6
It is displayed in 2. For example, as shown in FIG.
While the video signal of the second scanning line of the NTSC video signal NRGB is input, the video signal of the first scanning line is repeatedly output to the color monitor 62 twice. As a result, in the odd field, the image of each scanning line from the first scanning line to the 262th scanning line is repeatedly displayed twice each. On the other hand, as shown in FIG. 17 (l), in the even field, the image of each scanning line from the latter half 263s of the 263rd scanning line to the 525th scanning line is repeatedly displayed twice. Also,
As can be seen by comparing FIGS. 17F and 17L, the display of the even field and the display of the odd field on the color monitor 62 are deviated by one scanning line.

FIG. 18 is an explanatory diagram showing an odd field image and an even field image displayed on the color monitor 62. As shown in FIGS. 18A and 18B, in each of the odd field and the even field, the image of each scanning line is repeatedly displayed twice. However, in the odd field, the display is started later than the even field by one scanning line. This is shown in FIG.
It can be understood from the timings of (f) and (l). FIG. 18C shows an image observed by the user. Since the image of the odd field and the image of the even field are alternately displayed on the color monitor 62, the image of each scanning line on the screen of the color monitor 62 is the image of the scanning line of the odd field and the scanning of the even field. It is observed as an image in which the line image is interpolated. For example, the image of the uppermost scanning line on the screen looks like the image of the second half 263s of the 263rd scanning line. Further, the image of the second scanning line from the top of the screen appears as an image obtained by interpolating the image of the first scanning line of the NTSC system and the image of the second half 263s of the 263rd scanning line. Therefore, the images of the scanning lines on the screen are all viewed as different images.

The image is temporally interpolated as shown in FIG. 18, because the vertical sync signal VV of the display system is generated in synchronization with the horizontal sync signal MH of the display system as shown in FIG. Because there is. The horizontal synchronizing signal VH shown in FIGS. 17E and 17K is the same as the horizontal synchronizing signal MH generated by the display system horizontal synchronizing signal generator 122.
The signal is slightly delayed by 8 and is substantially equivalent to the horizontal synchronizing signal MH before the delay. If N
Horizontal synchronization signal NH of TSC system (FIGS. 17B and 17H)
When the vertical synchronizing signal VV is generated in synchronization with the above, since the video of the odd field and the video of the even field are not shifted by one scanning line as shown in FIG. 18, the displayed video looks like a mosaic. On the other hand, as in this embodiment, if the vertical synchronizing signal VV of the display system is generated in synchronization with the horizontal synchronizing signal MH (≈VH) of the display system, FIG.
As shown in FIG. 8, the image on the screen is temporally interpolated, so that the image quality of the image can be improved.

In the example of FIG. 18, for convenience of illustration, an image from the first scanning line to the 262th scanning line of the odd field and a second half of the 263rd scanning line of the even field to the 524th scanning line. Although all of the images are drawn so as to be displayed on the screen of the color monitor 62, in reality, a part of the upper part and the lower part of them are not displayed on the screen. The back porch period and the front porch period are appropriately adjusted according to the timing of the display system synchronizing signals VV and VH shown in FIG.

The present invention is not limited to the above embodiments, but can be implemented in various modes without departing from the scope of the invention, and the following modifications can be made.

(1) In the above embodiment, the 8-bit key command image is represented by 3 bits, but it is also possible to represent the multi-color key command image by more bits. For example, when a key command image is represented in 24-bit full color, the depth of the command video memories 104R, 104, 104B for 3 planes is 8 bits. It is also possible to use a color palette to represent a desired color with a small number of bits.

(2) In the above embodiment, the FI for two lines
Although the video signals are converted using the FO memories 91 and 92, it is possible to use other types of line memories instead of the FIFO memories. However, the FIFO memory has an advantage that read / write control is simple. The line memory for three lines or more may be used, and the line memory for writing and the line memory for reading may be switched in a predetermined order. At this time, the image quality can be improved by simultaneously reading out the video signals of a plurality of lines and performing the line interpolation from the video signals of the plurality of lines.

[0069]

As described above, according to the first aspect of the present invention, the video converting unit is a television image
By repeatedly generating the video signal of the same scanning line twice during the period of the scanning line, the second video signal applicable to the display device of the computer system can be generated. Further, by displaying the command key image on a part of the television image, the user can easily perform operations such as channel selection and volume adjustment of the television image. Furthermore, the command key image can be displayed on the display device even when the first synchronization signal is not input.

According to the second aspect of the invention, the command key image can be displayed on the display device by using the preliminary synchronization signal when the first synchronization signal is not input.

According to the invention described in claim 3, the command key image can be easily displayed in a desired area of the screen of the display device.

According to the invention described in claim 4, since the image of each scanning line on the display device is temporally interpolated,
The image quality can be improved.

According to the fifth aspect of the present invention, the second device applicable to the display device of the computer system can be applied by using a plurality of line memories without using a frame memory for storing a television video signal. The video signal of can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a personal computer system including a video display device as an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a second video control unit 44.

FIG. 3 is a block diagram showing an internal configuration of a video signal converter 72 (FIG. 2).

FIG. 4 is a block diagram showing an internal configuration of a FIFO memory unit 84 (FIG. 3).

FIG. 5 is a timing chart showing the operation of the video signal conversion unit 72 (FIG. 3).

FIG. 6 is a block diagram showing an internal configuration of a command video generation unit 74 (FIG. 2).

FIG. 7 is an explanatory diagram showing an example of a key command image.

FIG. 8 is an explanatory diagram showing a relationship between various images in a second image controller 44 (FIG. 2).

9 is a block diagram showing an internal configuration of a control unit 88 (FIG. 3).

FIG. 10 is a block diagram showing a second configuration of the control unit 88.

11 is a block diagram showing a third configuration of the control unit 88. FIG.

FIG. 12 is a block diagram showing an internal configuration of a synchronization signal converter 116 (FIG. 9).

FIG. 13 is a display system horizontal synchronization signal generator 122 (FIG. 12).
Block diagram showing the internal configuration of FIG.

FIG. 14 is a timing chart showing the operation of the display system horizontal synchronization signal generator 122.

FIG. 15 is a display system vertical synchronization signal generator 124 (FIG. 12).
Block diagram showing the internal configuration of FIG.

FIG. 16 is a timing chart showing the operation of the display system vertical synchronization signal generator 124.

FIG. 17 is a timing chart showing a display operation of an odd field and an even field of a video signal according to an example.

FIG. 18 is an explanatory diagram showing a relationship between scanning lines of odd fields and images of even fields displayed on the color monitor 62.

FIG. 19 is a conceptual diagram showing a display mode of a conventional television image.

[Explanation of symbols]

20 ... CPU 21 ... CPU bus 22 ... RAM 24 ... ROM 26 ... I / O interface 28 ... VRAM 40 ... First video display section 41 ... External video input section 42 ... Television video input section 44 ... Second video display section 46 ... Audio control unit 48 ... Video switch 50 ... Keyboard 52 ... Mouse 54 ... Remote control transmitter 60 ... Speaker 62 ... Color monitor 70 ... Video switch 72 ... Video signal conversion unit 74 ... Command video generation unit 76 ... Multiplexer 78 ... AND Circuit 80 ... Video decoder 81 ... Video expansion unit 82 ... A / D converter 84 ... FIFO memory unit 86 ... DA converter 88 ... Control unit 91, 92 ... FIFO memory 93, 94 ... Toggle switch 102 ... Vertical counter 104 Command video memory 106 Horizontal counter 108 Command memory control unit 110 ... I ² C controller 112 ... auxiliary synchronization signal generation unit 114 ... Switch 116 ... synchronizing signal converting unit 118 ... auxiliary synchronization signal generation unit 120 ... PLL circuit 121 ... frequency divider 122 ... display system horizontal sync signal generator Part 124 ... Display system vertical synchronizing signal generating part 128 ... Delay circuit part 130 ... Reset signal generating circuit 132 ... Pulse width counter 134 ... Synchronization period counter 136 ... Pulse width counter 138 ... AND circuit 140 ... EXOR circuit 150 ... Inverters 151-153 ... D-type flip-flop 154 ... NAND circuit MH ... display system horizontal synchronizing signal MPA ... moving image display area NCLK ... input clock signal NH ... horizontal synchronizing signal of television image signal NH1 ... vertical synchronizing signal of television image signal (first Sync signal) NH2 ... Preliminary horizontal sync Signal NRGB ... Digital video signal NV ... Vertical sync signal of television video signal (first sync signal) NV1 ... Vertical sync signal of television video signal (first sync signal) NV2 ... Preliminary vertical sync signal PIPSW ... Switching signal RE ... input enable signal RES ... reset signal S1 ... television video signal S2 ... television video signal S3 ... key command video signal SD ... output video signal SPC ... computer video signal SSW ... switching signal SS ... output audio signal STS ... television Audio signal STV ... Television video signal SVS ... External input audio signal SVV ... External input video signal SV ... Video signal SEL ... Selection signal SW ... Switching signal VCLK ... Output clock signal VH ... Display horizontal sync signal VH1 ... Display horizontal sync Signal (second synchronizing signal) VH2 ... Preliminary horizontal synchronizing signal VRGB ... De Digital video signal VV ... Vertical sync signal for display system VV1 ... Vertical sync signal for display system (second sync signal) VV2 ... Preliminary vertical sync signal YR ... Key command video signal

Claims (5)

[Claims] 1. A video display device for use in a computer system having a display device and a display control unit for displaying a television image on the display device, the first video signal representing the television image. A second video signal by repeatedly generating the first video signal for one scanning line twice during the period for one scanning line of the first sync signal based on the first synchronization signal. A video signal converter that generates a command key video signal representing a command key image including a plurality of command keys for operating a television, the command key video signal, and the second video signal By outputting while switching between and, a third image representing a video image in which the command key image and the television image are combined.
A video mixer section for generating a video signal of the second video signal, a second sync signal generating section for generating a second sync signal that is in synchronization with the second video signal based on the first sync signal, A preliminary synchronization signal generation unit that generates a preliminary synchronization signal that is substantially equivalent to a signal; and input terminals for the first synchronization signal and the preliminary synchronization signal, respectively. When the first synchronization signal is applied, The first synchronization signal is selected and given to the second synchronization signal generation section, while the preliminary synchronization signal is selected and the second synchronization signal generation is performed when the first synchronization signal is not given. A video signal display device, comprising: 2. A video display device for use in a computer system having a display device and a display control unit for displaying a television image on the display device, the first video signal representing the television image. A second video signal by repeatedly generating the first video signal for one scanning line twice during the period for one scanning line of the first sync signal based on the first synchronization signal. A video signal converter that generates a command key video signal representing a command key image including a plurality of command keys for operating a television, the command key video signal, and the second video signal By outputting while switching between and, a third image representing a video image in which the command key image and the television image are combined.
A video mixer section for generating a video signal of the second video signal, a second sync signal generating section for generating a second sync signal that is in synchronization with the second video signal based on the first sync signal, A preliminary synchronization signal generator that generates a preliminary synchronization signal almost equivalent to a signal; and input terminals for the second synchronization signal and the preliminary synchronization signal, respectively, and when the second synchronization signal is given, And a synchronization signal selection unit that selects the second synchronization signal and supplies it to the display device, while selects the preliminary synchronization signal and supplies it to the display device when the second synchronization signal is not supplied. An image display device comprising: 3. The video display device according to claim 1, wherein the command video generation unit includes a first frame memory that stores the command key video signal, and a switching signal provided to the video mixer unit. The second to remember
By supplying a common read address to the first frame memory and the second frame memory, the command key video signal is read from the first frame memory and the second frame memory is read from the second frame memory. An image display device comprising: an address generation unit that reads a switching signal. 4. A video display device for use in a computer system having a display device and a display control unit for displaying a television image on the display device, the first interlaced scanning representing the television image. Based on the video signal and the first synchronization signal, the first video signal for one scanning line is repeatedly generated twice during the period for one scanning line of the first synchronization signal. A video signal conversion unit for generating a video signal, and a second horizontal synchronization signal having a frequency twice that of the first horizontal synchronization signal included in the first synchronization signal, based on the first synchronization signal. A horizontal synchronization signal generation unit that generates the second synchronization signal, and a second synchronization signal that has the same frequency as the first vertical synchronization signal included in the first synchronization signal based on the first synchronization signal.
In order to generate the vertical synchronization signal of the first vertical synchronization signal, the first pulse of the second vertical synchronization signal is synchronized with the second horizontal synchronization signal after detecting the start point of the first pulse of the first vertical synchronization signal. An image display device comprising: a vertical synchronization signal generation unit that generates the vertical synchronization signal. 5. The video display device according to claim 1, wherein the video signal conversion unit stores the first video signals for one scanning line, respectively.
One line memory and the two line memories are alternately and complementarily switched to a write line memory for writing a video signal and a read line memory for reading a video signal, and the first synchronization signal. While writing the first video signal in the write line memory in response to a first clock signal in synchronization with the second video signal in response to a second clock signal in synchronization with the second synchronization signal. A control unit for controlling reading of a signal from the read line memory;
A video display device.