JPH0744151A - Video display - Google Patents

Abstract

(57) [Abstract] [Purpose] The CPU makes the contents of the first video storage unit the second
The first image stored in the first image storage unit and the second image stored in the second image storage unit are switched and displayed at high speed without being transferred to the image storage unit. [Structure] The phase corrector 14 includes a first video signal VVS1.
Of the luminance signal WL of the second video signal VVS2
Phase correction is performed so as to synchronize with V and RH. Since the phase-corrected video signal VVS3 is synchronized with the first video signal VVS2, by switching between the two video signals VVS2 and VVS3 by the video switch 16, two videos can be switched and displayed on the monitor 16 at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device used in a computer system.

[0002]

2. Description of the Related Art FIG. 21 is a block diagram showing the configuration of a conventional computer system. This computer system includes a CPU unit 1500 that is a central processing unit, a RAM unit 1501 that is a readable / writable storage unit, a ROM unit 1502 that is a read-only storage unit, and an I / O that controls external input / output. I / O unit 1503, keyboard 1504 and mouse 15 as input devices of I / O unit 1503
05, and an external storage unit 1506 having a large capacity of storage,
And a communication unit 1507. Further, in order to display an image, a first image storage unit 1512 and a second image storage unit 1513 as display storage units are provided, and image data in the first image storage unit 1512 is read out to obtain an image signal VS1. And the video signal V in the second video storage unit 1513 for reading the video signal V
The second video control unit 1511 for converting to S2 is provided. These two video signals VS1 and VS2 are asynchronous with each other. The system further includes a relay circuit unit 1514 that selects one of the two video signals VS1 and VS2.
And the video signal VS3 selected by the relay circuit unit 1514.
A monitor 1515 for displaying is also provided. The monitor 1515 is a so-called multi-scan monitor that can be synchronized with a plurality of types of video signals.

This computer system is configured to operate under two operating systems (hereinafter referred to as "OS"). Two video storage units 15
Reference numerals 12 and 1513 are frame memories respectively used by the two OSs. Below, there are two operating systems, MS-DOS (trademark of Microsoft Corporation in the United States) and MS-DOS which is a multi-window OS.
A case of using Windows (trademark of Microsoft Corporation in the United States) will be described.

The computer system of FIG. 21 is MS-D.
When operating under the control of the OS, the CPU 1500 operates the first video control unit 1510 to operate the first video signal V1.
Output S1. The relay circuit unit 1514 selects the first video signal VS1 and outputs it as the video signal VS3 to the monitor 15
Output to 15. Therefore, the image represented by the first image signal VS1 is displayed on the monitor 1515.

The computer system is MS-Windows.
When operating under the control of ws, the CPU 1500 operates the second video control unit 1511 to operate the second video signal V
Output S2. The relay circuit unit 1514 selects the second video signal VS2 according to the selection signal RSE given from the second video control unit 1511 and outputs it as the video signal VS3. Therefore, the image represented by the second image signal VS1 is displayed on the monitor 1515.

FIG. 22 is a memory map showing a memory space under the control of MS-Windows. MS-W
When MS-DOS is started under the control of Windows,
A 1-Mbyte MS-DOS area is secured in the memory space. The newly secured MS-DOS area has a VRAM space, but since the VRAM is not mounted here, the first video storage unit 1512 is actually the VRAM space.
Used as.

When the MS-DOS is activated, the monitor 15
In FIG. 15, MS-DOS called “DOS-BOX” is shown.
Window is displayed. FIG. 23 shows MS-Win.
A state in which the first image 1531 as the DOS-BOX is displayed in the second image 1530 of dows is shown.

[0008]

[Problems to be Solved by the Invention] MS-Windows
Even when the MS-DOS is operated under the control of, the second video signal read from the second video storage unit 1513 is given to the monitor 1515 and displayed. Therefore, conventionally, the CPU 1500 needs to transfer the video data in the first video storage unit 1512 to the second video storage unit 1513 in order to display the DOS-BOX 1531 as shown in FIG. That is, the CPU unit 1500 is the first storage unit 1
A large amount of video data in 512 is always stored in the second storage unit 1513.
While continuing to transfer the data to the inside, the operation of MS-DOS had to be performed. Therefore, the CPU unit 1
Since most of the processing speed of 500 is spent on the display processing, the operation of MS-DOS becomes very slow, and there is a problem that the DOS-BOX is extremely inconvenient to use.

The present invention has been made in order to solve the above-mentioned problems in the prior art, and the first video storage unit is not required to transfer the contents of the first video storage unit to the second video storage unit by the CPU. It is an object of the present invention to display at high speed while switching between the first image stored in the second image storage unit and the second image stored in the second image storage unit.

[0010]

In order to solve the above-mentioned problems, a video display device according to claim 1 of the present invention comprises a first video storage unit managed by a first operating system. A first video control unit for reading and outputting the first video signal stored in the first video storage unit; a second video storage unit managed by a second operating system; Second video control unit for reading and outputting the second video signal stored in the video storage unit, and a first phase correction for synchronizing the first video signal with a synchronization signal of the second video signal. Section, the second video signal, and a first video switch that selects one of the first video signals corrected by the first phase correction section and outputs the selected one to the monitor. .

The first phase correction section outputs the first video signal to the second video signal.
Since it is synchronized with the synchronizing signal of the video signal of, the two video images can be switched and displayed by simply switching the two video signals by the first video switch and outputting them to the monitor.

According to the video display device of the second aspect,
The first and second video signals are asynchronous with each other.

Since the first phase correction section synchronizes the first video signal with the synchronization signal of the second video signal, the first and second video signals which are asynchronous with each other can be switched and output to the monitor. it can.

According to the image display device described in claim 3,
The first phase correction unit writes the first video signal in the frame storage unit in synchronization with a frame storage unit that stores the first video signal and a synchronization signal of the first video signal. And a read control for supplying the first video signal stored in the frame storage unit to the first video switch in synchronization with the synchronization signal of the second video signal. And a section.

Since the first video signal is stored in the frame storage section in synchronization with the synchronization signal and is read in synchronization with the synchronization signal of the second video signal, the first video signal is converted into the second video signal. Can be synchronized with the sync signal of.

According to the image display device described in claim 4,
The read control unit indicates a selection signal indicating that the first video signal is selected within the video area of the first video signal and a second video signal is selected outside the display area. Selection signal generating means for supplying the first video switch.

With this configuration, the two video signals can be switched by the first video switch to display the two videos in a superimposed state.

According to the image display device described in claim 5,
The first phase correction unit further includes an A / D conversion unit that AD converts the first video signal, which is an analog signal, into the frame storage unit, and a digital signal read from the frame storage unit. And a D-A conversion unit that D-A converts the phase-corrected first video signal, which is a signal, and supplies the first video signal to the first video switch.

In this way, the first analog video signal
It becomes possible to process the video signal of.

In the video display device according to claim 6,
The write control unit is for creating a horizontal write dot clock signal that defines a horizontal timing when writing the first video signal in the frame storage unit from a synchronization signal of the first video signal. A first PLL circuit and a vertical write line clock signal that defines vertical timing when writing the first video signal to the frame storage unit, from a synchronization signal of the first video signal. A second PLL circuit is provided, and the frequencies of the horizontal write dot clock signal and the vertical write line clock signal are respectively adjusted by the first and second PLL circuits, and stored in the frame storage unit. The image is scaled.

With this configuration, the image can be scaled when writing the first image signal in the frame storage section.

In the video display device according to claim 7,
The read control unit creates a horizontal read dot clock signal that defines a horizontal timing when reading the phase-corrected first video signal from the frame storage unit from a synchronization signal of the second video signal. And a vertical read line clock signal for defining the timing in the vertical direction when reading the first video signal after the phase correction from the frame storage unit for the second video signal. A fourth PLL circuit for creating from a synchronization signal,
By adjusting the frequencies of the horizontal read dot clock signal and the vertical read line clock signal by the third and fourth PLL circuits, respectively, the image read from the frame storage unit is scaled.

With this arrangement, the image can be scaled when the first image signal is read from the frame storage section.

In the video display device according to claim 8,
The first and second video signals are video signals representing videos of different display resolutions.

As described above, it is possible to switch and display two video signals representing videos having different display resolutions.

In the video display device according to claim 9,
Furthermore, a third video storage unit managed by a third operating system, a third video control unit for reading and outputting a third video signal stored in the third video storage unit, and the third video storage unit. A second phase correction unit for synchronizing the video signal output from the first video switch with the synchronization signal of the third video signal, a third video signal, and a video corrected by the second phase correction unit. A second video switch for selecting one of the signals and outputting it to the monitor.

In this way, it is possible to switch and display three images.

[0028]

【Example】

A. Overall Configuration and Operation of Device: FIG. 1 is a block diagram showing the configuration of a computer system including a video display device according to a first embodiment of the present invention. This computer system includes a CPU 620 that is a central processing unit, a RAM unit 2 that is a readable / writable storage unit, a ROM unit 3 that is a read-only storage unit, and an I / O that controls external input / output. And part 4. Further, a keyboard 5 and a mouse 6 as input means of the I / O unit 4, an external storage unit 7 having a large capacity of storage, and a communication unit 8 for inputting / outputting information communication with the outside. It has and.

The computer system further reads the first video storage unit 12 and the second video storage unit 13 as frame memories, and the video data in the first video storage unit 12 and converts them into the first video signal VVS1. The first video control unit 10, the second video control unit 11 for reading the video data in the second video storage unit 13 and converting it into the second video signal VVS2, and correcting the phase of the first video signal VVS1. The phase correction unit 14, the video switch 15, and the multi-scan monitor 16 are provided. Two video signals VVS1,
VVS2s are asynchronous to each other (ie, sync signals are not in sync with each other).

The two video storage units 12 and 13 have two O
Each is managed by S. That is, the first video storage unit 12 is under the control of the first OS (for example, MS-DOS), and the second video storage unit 13 is under the control of the second OS (for example, MS-Windows). The memory map is similar to that shown in FIG.

Since the formats of the video data stored in the two video storage units 12 and 13 are different from each other, the two video control units 10 and 11 also have different functions. The video data stored in the second video storage unit 13 is bitmap data in which each color of RGB is represented by, for example, 8 bits for each dot of the monitor 16. Therefore, the second video controller 1
1 is the data of each color of RGB, the predetermined synchronization signal RSYNC
It has a function of converting into an analog luminance signal according to.

The first video storage unit 12 is a text VRAM.
And a graphic VRAM. Text VR
When the image is a character, the AM stores a character code indicating the character and attribute data indicating the attribute of each character (character color, reverse display, blink display, etc.). In the attribute data, for example, one of eight colors is designated by 3 bits as the color of the character. The graphic VRAM stores bitmap data representing the graphic for each dot. In the bitmap data of the graphic, 1 bit out of 8 colors may be designated by 3 bits, or 1 color out of 16 colors may be designated by 4 bits. The first video control unit 10 includes a character generator that converts a character code into bitmap data, an attribute generator that gives an attribute to a character, a color palette that converts the color of graphic data, and a video that combines a character image and a graphic. It has a function as a multiplexer. With these functions, the first video control unit 10 generates the video signal VVS1 including the luminance signal for each dot of the monitor 16.

FIG. 2 is an explanatory diagram showing the functions of the phase corrector 14 and the video switch 5. The phase correction unit 14 has a first
Of the second video signal VVS2 is synchronized with the synchronization signal RSYNC of the second video signal VVS2. Such a function is called "phase correction". That is, the first video signal VVS1 is supplied to the phase correction unit 14 as the video signal VV1.
The phase is corrected so as to be synchronized with the synchronization signal RSYNC of S2, and becomes the video signal VVS3 after the phase correction. The phase corrector 14 further controls the phase-corrected first video signal VVS.
A switching signal VSEL for selecting one of the third video signal VVS2 and the second video signal VVS2 is generated and supplied to the video switch 15. The phase correction unit 14 is controlled by the CPU 620 via the CPU bus 610, and has a switching signal VSE.
L is generated based on an instruction from the CPU 620. As a result, the video switch 15 has two video signals VVS.
Monitor 16 of video signal VVS4 that is a composite of VVS3 and VVS3
Output to. As shown in the lower part of FIG. 2, the monitor 16 displays the video V represented by the second video signal VVS2.
The first video signal VVS3 after phase correction is included in VS2X.
An image in which the image VVS3X represented by is combined is displayed.

In this computer system, the CPU 6
The second video data stored in the first video storage unit 10
Since it is not necessary to transfer to the image storage unit 11 and the two image signals VVS1 and VVS2 are combined by the phase correction unit 14 and the video switch 15, it is possible to display two images at high speed while switching between the two images. .

FIG. 3 is a block diagram showing a schematic configuration of the phase correction unit 14. The phase correction unit 14 includes the AD converter 2
10, a frame storage unit 310, and a DA converter 410
A write controller 200 and a read controller 400.

The first video signal VVS1 includes a luminance signal (component video signal) WL, a vertical synchronizing signal WV, and
It is composed of a horizontal synchronizing signal WH. Luminance signal WL
Are RGB color signals. Second video signal VVS2
Is composed of a luminance signal (component video signal) RL, a vertical synchronizing signal RV, and a horizontal synchronizing signal RH. The sync signal RSYNC shown in FIG. 2 includes a vertical sync signal RV and a horizontal sync signal RH.

Luminance signal WL of the first video signal VVS1
Is converted into luminance data WLD by the AD converter 210. The write control unit 200 supplies the write address WADD and the write control signal WCONT to the frame storage unit 310 according to the vertical synchronization signal WV and the horizontal synchronization signal WH,
The brightness data WLD is written in the frame storage unit 310. Thus, the luminance signal WL of the first video signal VVS1 is
Since the data is written in the 3-port video memory 310 in synchronization with the synchronization signals WV and WH, the video data faithfully corresponding to the first video signal VVS1 is stored in the 3-port video memory 310.
Memorized in.

The read control section 400 controls the second video signal VV.
The read address RADD and the read control signal RCONT are supplied to the frame storage unit 310 according to the vertical synchronization signal RV and the horizontal synchronization signal RH of S2, and the brightness data WLD stored in the frame storage unit 310 is read out. The read brightness data WLDR is converted into an analog brightness signal WLR by the DA converter 410. This brightness signal WLR is
The phase-corrected video signal VVS3 is output together with the synchronization signals RV and RH of the second video signal VVS2.
In this way, the video data WLDR stored in the 3-port video memory 310 is read in synchronization with the synchronization signals RV and RH of the second video signal VVS2, so that the video data WLDR is the D-A converter 410. The video signal VVS3 converted in step 1 is synchronized with the second video signal VVS2.

In this way, the phase-corrected video signal VVS
3 is synchronized with the second video signal VVS2, the two video signals VVS2, VV
These can be combined by simply switching and outputting S3.

Note that the read control section 400 changes the switching signal V according to the level of the luminance signal RL of the second video signal VVS2.
It is also possible to adjust the level of the SEL and provide the chroma key control means for displaying the image by the luminance signal RL only when the level of the luminance signal RL is in a specific range.

FIG. 4 is a block diagram showing an example of the internal configuration of the phase correction section 14 and the video switch 15. The writing control unit 200 includes a digitizing control unit 220,
In addition, the read control unit 400 is the superimpose control unit 4
It includes 20 and two buffers 62 and 63.

The A-D converter 210 receives the first video signal V
The brightness signal WL of VS1 is converted into a digital RGB signal WLD in synchronization with the clock signal CKAD output from the digitizing control unit 220. 3-port video storage unit 3
Reference numeral 10 corresponds to the frame storage unit in FIG. The digitize control unit 220 supplies the clock signal CKAD to the AD converter 210, and the 3-port video memory 31.
The write address WADD and the write control signal WCONT are supplied to 0. The video data WLDR read from the 3-port video memory 310 is converted into a video signal VVS3 which is an analog RGB signal by the DA converter 410. The superimpose control unit 420 supplies the clock signal CKDA to the DA converter 410, and
The read address RADD and the read control signal RCONT are supplied to the port video memory 310. In the following, first, the internal configuration and operation of the digitize control unit 220 will be described, and then the internal configuration and operation of the superimpose control unit will be described.

B. Internal Configuration and Operation of Digitize Control Unit 220: FIG. 5 is a detailed block circuit diagram of the digitize control unit 220 and its peripheral circuits. In this embodiment,
As the 3-port video memory 310, for example, Sony C
XK1206 or Fujitsu's MB81C1501 is used. Here, description will be given using only the write port of the 3-port video memory 310. This 3 port video memory 3
For the 10 write ports, characteristic timing charts are described on pages 21 to 26 of the Sony data sheet 71215-ST. The 3-port video memory 310 has a configuration of 960 rows (COLUMN) × 306 columns (ROW) × 4 bits, which are provided for R, G, and B, respectively. Therefore, it is possible to store data which is quantized into 4 bits / dot in one effective horizontal scanning period with 960 dots × 3 colors.

The access to the 3-port video memory 310 is carried out in units of rows in blocks and columns in units of lines. In the 3-port video memory 310, DIN0
To DIN3 are data input terminals for inputting digital RGB signals, ADD0 to ADD3 are address input terminals, and CK
W0 is a port 0 shift signal terminal, INC0 is a port 0 line increment terminal, HCLR0 is a port 0 horizontal clear terminal, VCLR0 is a port 0 vertical clear terminal, WE
(Negative logic) is a port 0 write enable signal terminal. R, G, and B of the digital RGB signals are, for example, 4-bit signals.

In FIG. 5, reference numeral 221 denotes a horizontal write dot clock generation circuit for outputting the horizontal write dot clock signal HWDCK and the basic synchronization signal BSYNC.
Indicates a horizontal write start counter that outputs the horizontal write start signals HWS and HCLR0, and 223 indicates a horizontal write count counter that outputs the horizontal write count signal HWT. Further, reference numeral 224 is a vertical write line clock signal VWLC.
Shows a vertical write line clock generation circuit that outputs K,
225 is a vertical write start counter that outputs the vertical write start signal VWS, 226 is a vertical write number counter that outputs the vertical write number signal VWT, and 227 is a vertical write of the 3-port video memory 310. 9 shows a vertical write offset counter that outputs a vertical write offset signal VWOFT that specifies the start position of writing. Also, the OR circuit 2
28 outputs either the vertical write line clock signal VWLCK or the vertical write offset signal VWOFT as the port 0 line increment signal INC0, and the AND circuit 229 outputs the horizontal write dot clock signal H.
WDCK, horizontal write start signal HWS, inverted output of horizontal write number signal HWT, vertical write start signal VWS, and
The write enable signal WENBL is output by creating a logical product of five signals, that is, an inverted output of the vertical write number signal VWT. The NOR circuit 230 uses the vertical synchronizing signals WV and HC.
LR0 signal, output signal of OR circuit 228, and AND
The OR-NOT logical operation of four signals of the write enable signal WENBL output from the circuit 229 is performed, and the port write enable signal WE is output.

Horizontal sync signal W of the first video signal VVS1
H is supplied to the horizontal write dot clock generation circuit 221, the horizontal write start counter 222, the horizontal write number counter 223, and the vertical write start counter 225. Also, the first
The vertical synchronization signal WV of the video signal VVS1 of the vertical write line clock generation circuit 22 via the AND circuit 810.
4, vertical write start counter 225, vertical write number counter 226, vertical write offset counter 227, port vertical clear terminal VCLR0 of 3 port video memory 310
And the NOR circuit 230.

FIG. 6 is an explanatory diagram showing the function of set values in each of the circuits 221 to 227 in the digitizing control section 220. In the following, the function of each of these circuits and the meaning of their set values will be sequentially described.

Horizontal write dot clock generation circuit 221
Is a horizontal write dot clock signal HWDC having a frequency designated by the CPU 620 and synchronized with the horizontal synchronization signal WH.
It is a PLL circuit that generates K. The horizontal write dot clock signal HWDCK is AD as a clock signal CKAD that defines the sampling timing of AD conversion.
It is provided to the converter 210. The horizontal write dot clock signal HWDCK also applies to the horizontal write start counter 222, the horizontal write number counter 223, and the AND circuit 2.
It is also sent to 29.

By the way, the 3-port video memory 310 is divided into appropriate block units and the address presetting is performed. Here, when one block unit of address preset of the 3-port video memory 310 is 60 dots and one effective horizontal scanning period of the analog video signal is 46 (μs), it is generated by the horizontal write dot clock generation circuit 221. the frequency of the horizontal writing dot clock signal HWDCK is 60 (dots) / 46 - 10 ^@ 6 (s) = 1.3 (MH
Z). By this horizontal write dot clock signal HWDCK, the analog RGB signal in one effective horizontal scanning period is 60
It will be quantized with dots × 3 colors. Actually, the 3-port video memory 310 has 960 dots (16 blocks)
Is configured to store data for one effective horizontal scanning period. Therefore, if the horizontal write dot clock HWDCK of 1.3 (MHZ) × 16 (block) = 21 (MHZ) is used, the digital RGB signal in one effective horizontal scanning period can be stored with 960 dots. Further, when storing RGB signals in one effective horizontal scanning period in 10 blocks (600 dots), the horizontal write dot clock HWDCK of 1.3 (MHZ) × 10 (blocks) = 13 (MHZ) is used. .

As described above, the horizontal write dot clock generation circuit 221 has a horizontal frequency which is based on the value of the address preset block unit (60 dots) of the 3-port video memory 310 and the number of blocks to be used (1 to 16). The write dot clock signal HWDCK is output. The value of the number of blocks used is C in the personal computer.
It is set by the PU 620.

The horizontal write dot clock generation circuit 221 further includes a port shift signal terminal CKW0 of the 3-port video memory 310 (a signal for incrementing the horizontal write permission and write address of the 3-port video memory 310 in dot units). Basic synchronization signal B used as clock
SYNC also occurs. Here, considering the clock signal CKAD and the basic synchronization signal BSYNC, the clock signal CKAD for digitally converting the analog RGB signal
Is synchronized with the basic synchronization signal BSYNC,
Horizontal write permission control of the port video memory 310,
Performs address increment control in dot units.

Horizontal write dot clock generation circuit 2 described above
The basic synchronization signal BSYNC generated by 21 is a signal for achieving basic synchronization with each control circuit. The horizontal writing start counter 222, the horizontal writing number counter 223,
Vertical write line clock generation circuit 224, vertical write start counter 225, vertical write number counter 226, vertical write offset counter 227, and 3-port video memory 3
Given to 10.

As shown in FIG. 6, the frequency fHWDCK of the horizontal write dot clock signal HWDCK and the basic synchronizing signal B
Ratio of SYNC frequency fBSYNC (fHWDCK / fBSYNC)
Is a video represented by the first video signal VVS1 (see FIG. 6).
(A)) and the horizontal scaling factor MH1 of the video (FIG. 6B) written in the 3-port video memory 310.
Therefore, by adjusting the frequency fHWDCK of the horizontal write dot clock signal HWDCK, it is possible to horizontally expand or contract the image written in the 3-port image memory 310.

Vertical write line clock generation circuit 224
Is a PLL circuit which generates a vertical write line clock signal VWLCK having a frequency fVWLCK that is N times the frequency fWV of the vertical sync signal WV in synchronization with the vertical sync signal WV and sends it to the vertical write number counter 226 and the OR circuit 228. Is. The CPU 620 sets the N-fold value. As shown in FIG. 6, the vertical write line clock signal VWLC
K frequency fVWLCK and horizontal sync signal WH frequency fWH
Ratio (fVWLCK / fWH) is a vertical reduction ratio between the video represented by the first video signal VVS1 (FIG. 6A) and the video written in the 3-port video memory 310 (FIG. 6B). Equal to MV1. Therefore, by adjusting the value of the set value N in the vertical write line clock generation circuit 224 and changing the frequency fVWLCK of the vertical write line clock signal VWLCK, the image written in the 3-port video memory 310 is vertically expanded. It is possible to

After the horizontal writing start counter 222 is reset by the horizontal synchronizing signal WH and counts the pulses of the horizontal writing dot clock signal HWDCK by the number N222 of clocks designated by the CPU 620, the horizontal writing start signal HWS is output. Output. This horizontal write start signal HW
S is a signal that permits quantization from the dot position designated by the CPU 620 during the effective horizontal scanning period of the analog video signal. After generating the horizontal write start signal HWS, the horizontal write start counter 222 sends the port 0 horizontal clear signal HCLR0 to the 3-port video memory 310 for only one clock.

As shown in FIG. 6A, the set value N222 of the horizontal write start counter 222 is stored in the 3-port video memory 310 during the effective horizontal scanning period represented by the first video signal VVS1. It shows the horizontal start position of the image portion to be written (the area surrounded by the broken line in the figure).

The horizontal write number counter 223 is reset by the horizontal synchronizing signal WH, and then the horizontal write start signal H
When WS is applied, horizontal write dot clock signal HW
If the number of clocks of DCK is started and the number of clocks N223 designated by the CPU 620 is counted during the effective horizontal scanning period of the analog video signal, the analog RG
A horizontal write number signal HWT which permits the quantization of the B signal is transmitted. Therefore, the horizontal writing number counter 223 controls the effective horizontal scanning period, and it is possible to select up to which part in the horizontal direction the image is effective.

As shown in FIG. 6B, the set value N223 of the horizontal write number counter 223 is the value of the 3-port video memory 3
10 shows the number of dots in the horizontal direction of the video portion written in 10.

The vertical writing start counter 225 is reset by the vertical synchronizing signal WV, and then the clock of the horizontal synchronizing signal WH is the number N22 of clocks designated by the CPU 620.
If only 5 is counted, the effective horizontal scanning analog RGB
The vertical write start signal VWS that permits the signal quantization is set to AN.
The data is output to the D circuit 229 and the vertical writing number counter 226.

As shown in FIG. 6A, the set value N225 of the vertical writing start counter 225 is equal to the first video signal VVS.
In the effective video area (area surrounded by a solid line) represented by 1, the vertical start position of the video portion (area surrounded by a broken line) written in the 3-port video memory 310 is shown.

The vertical write number counter 226 is reset by the vertical synchronizing signal WV, and then the vertical write start signal V
When WS is applied, the vertical write line clock signal VW
Start counting the clock of LCK and set the clock count to C
Only while the number of clocks N226 designated by the PU 620 is reached, the vertical write number signal VWT which permits the quantization of the analog RGB signals is transmitted. Therefore, the vertical effective scanning period is controlled by the vertical writing number counter 226, and it is determined up to which line portion in the vertical direction the image is effective.

As shown in FIG. 6B, the set value N226 of the vertical write number counter 226 is the value of the 3-port video memory 3
10 shows the number of lines in the vertical direction of the video portion written in 10.

The writing position in the horizontal direction with respect to the display screen of the 3-port video memory 310, that is, the writing position in the COLUMN direction is set to CP by the address preset mode.
U620 performs block designation of 60 dots × 3 colors of the quantized digital RGB signal as one block.
At this time, the block is designated by the address input signal ADD0.
~ ADD3 is performed in 16 steps. That is, the address input signals ADD0 to ADD3 indicate the write start position in the 3-port video memory 310, as shown in FIG. The address input signals ADD0 to ADD
D3 is set by the CPU 620.

As shown in FIG. 6C, the vertical writing start position on the display screen of the 3-port video memory 310 is the set value N227 of the vertical writing offset counter 227.
Stipulated by That is, the vertical write offset counter 227 is reset by the vertical sync signal WV, and then the vertical write offset signal VWOFT for offsetting the vertical write position of the 3-port video memory 310 in synchronization with the basic sync signal BSYNC and The vertical write start position of the 3-port video memory 310 is controlled by sending the line increment signal INC0 by the number of pulses equal to the number of lines N227 designated by the CPU 620.

FIG. 7 is a timing chart showing the operation of the digitizing control section 220. (1) First, when the vertical synchronizing signal WV becomes high level “H” (see FIG. 7A), the vertical writing start counter 22
5, the vertical write number counter 226 and the vertical write offset counter 227 are reset, and the vertical write start signal V
The WS and the vertical write number signal VWT become low level "L" (see FIGS. 7D and 7E).

(2) Vertical write offset counter 227
Creates a vertical write offset signal VWOFT from the basic sync signal BSYNC, and
Two WOFT clocks are output (see FIG. 7).
(See (h)). This vertical write offset signal VWOFT
Is given to the port 0 line increment signal terminal INC0 of the 3-port video memory 310 via the OR circuit 228, and the vertical address of the 3-port video memory 310 is incremented twice. Which horizontal line in 310 to start writing is offset.

(3) On the other hand, the vertical writing start counter 225
When the number of clocks of the horizontal synchronization signal WH reaches the number N225 designated by the CPU 620, the vertical write start signal VW
S is set to a high level "H" to permit quantization in the vertical effective scanning period (see FIG. 7D). This makes it possible to control which horizontal line on the screen by the analog video signal is valid.

(4) Vertical write offset signal VWOFT
In the 3-port video memory 310 which has obtained the clock of (1), the vertical write address is offset by the operation of (2) above, and the horizontal synchronizing signal WH becomes high level "H" (FIG. 7).
(J)), the horizontal write start counter 222 and the horizontal write number counter 223 are reset, and the horizontal write start signal HWS and the horizontal write number signal HWT are set to the low level “L” (FIG. 7 (n). ) And (o)). Further, the horizontal write dot clock generation circuit 221 outputs the horizontal write dot clock signal HWDCK (see FIG. 7 (m)).
A that received this horizontal write dot clock signal HWDCK
The -D converter 210 uses the horizontal write dot clock signal HW.
It operates by using DCK as a sampling hold signal and a data latch signal to sample analog RGB.

The horizontal write start counter 222 counts the number of clocks of the horizontal write dot clock signal HWDCK, and when the count value reaches the number N222 designated by the CPU 620, the horizontal write start signal HWS is set to high level. Set to "H" to allow quantization in the effective horizontal scanning period (see FIG. 7 (n)). At the same time, the horizontal writing start counter 222 outputs 1 clock to the port 0 horizontal clear signal HCLR0 of the 3-port video memory 310 to prepare for writing.

At this time, the AND circuit 229 creates a logical product of the horizontal writing start signal HWS of the high level "H" and the vertical writing number signal VWT of the low level "L" which is inverted and inputted, and the horizontal writing dot The clock signal HWDCK is sent to the NOR circuit 230 as the write enable signal WENBL. Further, the NOR circuit 230 uses the high level "H" port 0 horizontal clear signal HCLR0, the high level "H" vertical sync signal WV, the high level "H" vertical write offset signal VWOFT, or the vertical write line clock signal VWLCK. And NO of the write enable signal WENBL
3-port video memory 3
It is sent to the write 0 enable signal terminal WE of 10 as the write enable signal WE.

The 3-port video memory 310 becomes writable upon receiving the write enable signal WE, and the A / D converter 2
The digital RGB signal output from 10 is written. At the same time, the horizontal write number counter 223 counts the number of clocks of the horizontal write dot clock signal HWDCK, and permits writing of the luminance signal WLD until the count value reaches the number N223 designated by the CPU 620. When the count value reaches the designated number N223, the horizontal write number counter 223 sets the horizontal write number signal HWT to the high level "H" to inhibit writing (see FIG. 7 (o)).

Thus, during the period in which the digital RGB signal WLD is written, the vertical write line clock generation circuit 224 outputs the vertical write line clock signal VWLC.
Until K is output, horizontal writing is performed for the same vertical line address. Then, when the vertical write line clock generation circuit 224 sends the vertical write line clock signal VWLCK as the port 0 line increment INC0 signal of the 3-port video memory 310, the vertical write line address of the 3-port video memory 310 is changed. Go to "1".

In this way, when the writing in the vertical direction progresses and the number of clocks of the vertical write line clock signal VWLCK output from the vertical write line clock generation circuit 224 reaches the number of lines N226 designated by the CPU 620, the vertical write is performed. The write number counter 226 sets the vertical write number signal VWT to the high level “H”, and stops writing to the 3-port video memory 310 during the vertical effective scanning period (see FIG. 7E). This writing is stopped by the next vertical synchronization signal W.
It continues until V becomes high level "H".

As described above, in this embodiment, the vertical write line clock signal VWLCK and the horizontal write dot clock signal HWDCK are adjusted to arbitrary frequencies by the CPU 620, and the A / D converter 210 and the 3-port video memory 310 are used. C by controlling the control signal output to
An image can be written in an arbitrary reduced size in the 3-port image memory 310 without transferring the image data by the PU 620. Furthermore, it is also possible to enlarge in the horizontal direction at an arbitrary enlargement ratio.

In the above operation, the high level "H" is the active logic, but the same operation is the same when the low level "L" is the active logic.

With the image processing apparatus of this embodiment, the CPU 6 in the personal computer can execute the arbitrary resolution of the analog video signal, the arbitrary aspect ratio, the window display of the arbitrary area and the video technique of the multi-strobe still image.
20 can be operated easily.

C. Detailed Configuration and Operation of Superimpose Control Unit 420: FIG. 8 is a block circuit diagram of the superimpose control unit 420 and its peripheral circuits shown in FIG. Also, the 3-port video memory 310 shown here is
The read port is used among the three input / output ports. Sony CXK1206 data sheet number 71215
On pages 27 to 31 of -ST, timing charts relating to the above read ports are described. The port used is read port 1 on page 2 of the above data sheet.

In the 3-port video memory 310, the memory drive clock signal HDCK is the port 1 shift signal terminal CK.
R1 is the memory vertical / horizontal reset signal MRST to the port 1 vertical clear terminal VCLR1, the horizontal direction reset signal HRST is the port 1 horizontal clear terminal HCLR1, and the vertical offset signal VROFT or the vertical read line clock signal VRLCK is the port 1 line increment terminal. Port 1 output enable RE1 (negative logic) to INC1
Are applied to the port 1 output enable terminal RE1 (negative logic), respectively. Also, the analog RGB signal WLDR
(1 data in each of R, G, B) is read from the port 1 data output DO10 to DO13.

Reading is controlled by the port 1 shift signal CKR1, the port 1 vertical clear signal VCLR1, the port 1 horizontal clear signal HCLR1, the port 1 line increment signal INC1, and the port 1 output enable RE1 (negative logic) corresponding to the above terminals. Analog RGB signal WLD
R is, for example, 4 bits for each of R, G, and B and is output from the port 1 data outputs DO10 to DO13, respectively.

The video switch 510 shown in FIG. 8 is switched to A by the switching signal VSEL input to the switching signal input terminal CNT.
The input of the terminal or the B terminal is output from the common terminal C. Specifically, when the switching signal VSEL is at the high level "H", the input of the B terminal is output from the C terminal, and when the switching signal VSEL is at the low level "L", the input of the A terminal is output from the C terminal. CPU620
Controls each unit via the CPU bus 610 in the personal computer.

Reference numeral 421 in FIG. 8 denotes a horizontal reference read dot clock generator which outputs a horizontal reference read dot clock signal HBDCK, and 422 denotes a horizontal read start counter which outputs a horizontal read start signal HRSA and a horizontal read direction reset signal HRST. Shown at 423 is a horizontal reference start signal HR.
It shows a horizontal 64 clock counter that outputs SB.
Reference numeral 4 denotes a horizontal read number counter that outputs a horizontal read number signal HRT, and 425 denotes a horizontal read dot clock signal H.
2 shows a horizontal read dot clock generator that outputs DDA. Further, the vertical read offset counter 426 outputs a vertical read offset signal VROFT that determines the offset line of the vertical read line of the 3-port video memory 310 with the count number synchronized with the horizontal reference read dot clock generator 421. The vertical blanking number counter 427 outputs the vertical blanking end signal VBE, and the vertical read start counter 428 outputs the vertical read start signal VBE.
RS is output, the vertical read number counter 429 outputs the vertical read number signal VRT, and the vertical read line clock generator 430 outputs the vertical read line clock signal VRLCK. The AND circuit 431 outputs two video signals VVS2,
Switching signal VSEL for superimposing VVS3
And the OR circuit 432 outputs the vertical read offset signal V
ROFT and vertical read line clock signal VRLCK
The port 1 line increment signal INC1 is output, and the NOR circuit 433 outputs the read enable RE1 signal. Reference numerals 434 and 435 denote tristate circuits and 436 denotes an inverter circuit.

The color signal of the video signal VVS2 coming from the color signal input terminal 506 is given to the A terminal of the video switch 510. The horizontal sync signal RH coming from the sync terminal 507, which forms the horizontal sync signal of the input terminal 506, receives the horizontal reference read dot clock generator 421, the horizontal read start counter 422, the horizontal 64 clock counter 423, the horizontal read number counter 424, and the vertical block. Ranking number counter 42
7, the vertical read start counter 428, the vertical read number counter 429, and the vertical read line clock generator 430, and the vertical synchronization signal RV is supplied to the 3-port video memory 310, the vertical read offset counter 426, and the vertical blanking number counter 427. , Vertical read start counter 4
28, vertical read number counter 429, and vertical read line clock generator 430. Also, the synchronization signal R
The H and RV are also sent to the synchronizing signal terminals 490 and 491, respectively.

Input / output of the horizontal synchronizing signal RH and the vertical synchronizing signal RV will be described with reference to FIG. The horizontal synchronizing signal RH and the vertical synchronizing signal RV are stored in the buffer 62,
It is given to the required signal shown in FIG. 8 in the sync signal terminals 490 and 491 and the superimpose control section 420 via 61. The buffers 61 and 62 have functions such as Impedes conversion and waveform shaping, and contribute to the accurate transmission of the synchronization signal even when the image processing devices are connected in cascade. Further, the horizontal synchronizing signal RH is given to the PLL circuit 63 in the horizontal reference read dot clock generator 421, and CP
The horizontal reference read dot clock HBD is used as a signal that specifies the horizontal resolution of the entire horizontal screen specified by U620.
CK is generated.

The PLL circuit 63 is constructed as shown in FIG. That is, from the signal line 70 to the horizontal synchronization signal RH
Is given to the phase comparator 71, and the output of the N division cycle 74 is given to the phase comparator 71. The phase comparator 71 compares the phases of these signals and outputs a signal having a pulse width corresponding to the phase difference. Output. The output of the phase comparator 71 is given to the low pass filter 72, smoothed, and given to the VCO 73. The VCO 73 oscillates at a frequency according to the applied voltage, which is the horizontal reference read dot clock HBDCK.
Then, it is sent to each section and is given to the N division cycle 74, divided to the frequency of the horizontal synchronizing signal RH and returned to the phase comparator 71. As a result, the horizontal synchronization signal RH
A horizontal reference read dot clock HBDCK synchronized with is generated.

The horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read number counter 424 in the superimpose controller 420 shown in FIG. 8 are reset by the horizontal synchronizing signal RH. Further, the vertical synchronizing signal RV coming from the synchronizing terminal 508 is the port 1 vertical clear VCLR 1 of the 3-port video memory 310, the NOR circuit 433, the vertical read offset counter 426, the vertical blanking number counter 4
27, the vertical read start counter 428, the vertical read number counter 429, the vertical read line clock generator 430, and the synchronization signal terminal 491. The vertical read offset counter 426, the vertical blanking number counter 427, the vertical read start counter 428, and the vertical read number counter 429 are reset by the vertical synchronizing signal RV.

Horizontal reference read dot clock generator 421
Generated horizontal reference read dot clock signal HBD
CK is supplied to the horizontal read start counter 422, the horizontal 64 clock counter 423, the horizontal read number counter 424, and the vertical read offset counter 426, and also through the tri-state circuit 435.
The 10 clock signal HDCK is sent to the port 1 shift signal terminal CKR1 of the 3-port video memory 310.

The horizontal read dot clock generator 42
Reference numeral 5 designates a horizontal read reference signal HRSB from the horizontal 64 clock counter 423 as a reference and is constituted by a PLL circuit which outputs a signal having a frequency N1 times the frequency of the horizontal synchronizing signal RH.
Is output. This horizontal read dot clock generator 425
Read out dot clock signal HDDA generated by
Is the port 1 shift signal terminals CKR1 and D of the 3-port video memory 310 as the clock signal HDCK of the 3-port video memory 310 via the tri-state circuit 434.
The digital RGB signal W supplied to the -A converter 410
It is used as the read clock signal of the LDR and the conversion clock signal of the DA converter 410.

FIG. 11 shows a superimpose control section 42.
It is explanatory drawing which shows the function of the setting value of each circuit in 0. Figure 1
1, the horizontal reference read dot clock signal HB
Ratio of frequency fHBDCK of DCK and frequency fHDDA of horizontal read dot clock signal HRDCK (fHBDCK / fHDDA
) Is a video read from the video memory 310 (see FIG. 11).
(A)) and an image displayed on the monitor 16 (see FIG. 11).
(B)) This is equal to the horizontal scaling factor MH2. Therefore, by adjusting the frequency fHDDA of the horizontal read dot clock signal HDDA, the image displayed on the monitor 16 can be enlarged or reduced in the horizontal direction.

The vertical read line clock generator 430
The vertical read line clock signal VRLCK is formed by a PLL circuit that outputs a signal having a frequency N2 times the frequency of the vertical synchronizing signal RV in synchronization with the vertical synchronizing signal RV.
Is output. This vertical read line clock generator 430
Vertical read line clock signal VRLC generated by
K is the 3-port video memory 31 via the OR circuit 432.
It is given to the port 1 line increment terminal INC1 for advancing a line address which is a vertical address of 0, and is also given to the port 1 output enable RE1 terminal (negative logic) via the OR circuit 432 and the NOR circuit 433.

As shown in FIG. 11, the frequency fRH of the horizontal synchronizing signal RH and the vertical read line clock signal VRLCK are set.
The frequency (fRH / fVRLCK) of the frequency fVRLCK of the video is read from the 3-port video memory 310 (FIG. 11A).
Is equal to the vertical scaling factor MV2 of the image displayed on the monitor 16 (FIG. 11B). Therefore, by adjusting the frequency fVRLCK of the vertical read line clock signal VRLCK, the image displayed on the monitor 16 can be scaled up / down in the vertical direction.

The superimpose controller 420 obtains a basic read timing based on the horizontal reference read dot clock signal HBDCK, the horizontal read dot clock signal HDDA and the vertical read line clock signal VRLCK.

The vertical read offset counter 426 is set to 3
In order to determine the start offset line position of the read line of the port video memory 310, after the count value is reset by the vertical sync signal RV, it is synchronized with the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421. At the same time, the vertical offset signal VROFT that advances the vertical line address of the 3-port video memory 310 is sent to the OR circuit 432.

As shown in FIG. 11A, the set value N426 of the vertical read offset counter 426 indicates the vertical start position of the video portion (the area surrounded by the broken line in the figure) read from the 3-port video memory 310. Shows.

The vertical blanking number counter 427 includes a counter (not shown) for deleting the vertical back porch area of the video signal VVS2. This counter counts the number of clocks of the horizontal synchronizing signal RH, and when the vertical back porch area is exceeded, the vertical blanking end signal VB is output.
E is output to the vertical read start counter 428.

The vertical read start counter 428 receives the enable signal (vertical blanking end signal VBE) sent from the vertical blanking number counter 427, counts the number of clocks of the horizontal synchronizing signal RH, and outputs the 3-port video memory 310. A vertical read start permission signal (vertical read start signal) VRS is output to the vertical read number counter 429.

As shown in FIG. 11C, the set value N428 of the vertical read start counter 428 is displayed in the vertical direction when the video read from the 3-port video memory 310 is displayed on the screen of the monitor 16. Define the starting position.

The vertical read number counter 429 receives the permission signal (control signal VRS) sent from the vertical read start counter 428, counts the number of clocks of the horizontal synchronizing signal RH, and outputs the vertical direction from the 3-port video memory 310. To the AND circuit 431.

As shown in FIGS. 11B and 11C, the set value N 429 of the vertical read number counter 429 is the monitor 16
Specifies the number of vertical lines of the image displayed in.

The vertical read offset counter 426, the vertical blanking number counter 427, the vertical read start counter 428, the vertical read number counter 429, and the vertical read line clock generator 430, which have been described above, are used for the vertical direction with respect to the 3-port video memory 310. Read control is performed.

The vertical read offset counter 426
Horizontal reference read dot clock signal HBD counted by
CK clock count N426, vertical blanking counter 427 counts horizontal sync signal RH clock count N
427, the number of clocks N428 of the horizontal synchronizing signal RH counted by the vertical read start counter 428, the number of clocks N429 of the horizontal synchronizing signal RH counted by the vertical read number counter 429, and the PL in the vertical read line clock generator 430.
The value of the N frequency divider in the L circuit is set to a required value by the CPU 620 in the personal computer.

The horizontal read start counter 422 counts the number of clocks of the horizontal reference read dot clock signal HBDCK sent from the horizontal reference read dot clock generator 421, and the read start enable signal ( The horizontal read start signal HRSA) is sent to the horizontal 64 clock counter 423.

As shown in FIG. 11C, the set value N422 of the horizontal read start counter 422 is displayed in the horizontal direction when the image read from the 3-port image memory 310 is displayed on the screen of the monitor 16. Define the starting position.

The horizontal 64 clock counter 423 receives the enable signal (horizontal read start signal HRSA) sent from the horizontal read start counter 422 and outputs the horizontal reference read dot clock signal HBDCK output from the horizontal reference read dot clock generator 421. Count the number of clocks.
Then, when the count value reaches 64 clocks, which is the characteristic when the 3-port video memory 310 is read, the horizontal read reference signal HRSB is set to the horizontal read dot clock generator 42.
5, horizontal read number counter 424 and AND circuit 431
Output to.

The horizontal read number counter 424 counts the number of clocks of the horizontal reference read dot clock signal HBDCK sent from the horizontal reference read dot clock generator 421, and the horizontal read period enable signal of the 3-port video memory 310 ( Horizontal readout frequency signal HRT) is set to AN
It is sent to the D circuit 431.

As shown in FIGS. 11B and 11C, the set value N424 of the horizontal read number counter 424 is the monitor 16
Specifies the number of dots in the horizontal direction of the image displayed in.

Thus, the horizontal read start counter 422,
The horizontal 64 clock counter 423 and the horizontal read number counter 424 perform horizontal read control on the 3-port video memory 310. The set value of the frequency divider in the PLL circuit of the horizontal reference read dot clock generator 421 and the PLL of the horizontal read dot clock generator 425.
The setting value of the frequency divider in the circuit and the horizontal read start counter 42
Horizontal reference read dot clock signal HB counted by 2
DCK clock number N422 and horizontal read number counter 4
Reference dot clock signal HBDCK counted by 24
The number of clocks N424 is C in the personal computer.
It is set to a required value by the PU 620.

Next, the operation of the superimpose control unit 420 will be described with reference to FIGS. 12, 13, 14 and 15. Note that FIG. 12 shows the 3-port video memory 3
10 is a timing chart of vertical read permission of FIG. 10, FIG. 13 is a timing chart of vertical offset of the 3-port video memory 310, and FIG. 14 is a timing chart of horizontal read permission of the 3-port video memory 310. FIG. 15 is a timing chart of horizontal reading from the 3-port video memory 310.

First, horizontal read permission of the 3-port video memory 310 will be described with reference to FIG. When the vertical synchronizing signal RV becomes high level “H” (FIG. 12)
(See (a)), vertical blanking number counter 427, vertical reading start counter 428, and vertical reading number counter 4
29 is reset and the vertical blanking end signal VB
E, vertical read start signal VRS and vertical read number signal VR
T becomes low level “L” (FIG. 12 (d),
(See (e) and (f)), vertical blanking number counter 4
27 counts the number of clocks of the horizontal synchronizing signal RH, and when the vertical back porch area has passed, the vertical blanking end signal VBE is set to the high level "H" (see FIG. 12 (d)). When the vertical blanking end signal VBE becomes high level "H", the vertical read start counter 428 starts counting the number of clocks of the horizontal synchronizing signal RH. When the vertical read start counter 428 counts the value N428 set by the CPU 620, the vertical read start signal VR
S is set to a high level "H" (see FIG. 12 (e)). When the vertical read start signal VRS becomes high level “H”, 3
Since the start of reading the digital RGB signal WLDR is permitted in the vertical direction of the port video memory 310, the vertical read number counter 429 starts counting the number of clocks of the horizontal synchronizing signal RH. When the vertical read number counter 429 counts the value N429 set by the CPU 620, the vertical read number signal VRT is set to the high level "H" (see FIG. 12 (f)).

Therefore, when the horizontal read reference signal HRSB is at the high level "H" and the horizontal read number signal HRT is at the low level "L", the vertical read start signal VRS is at the high level "H" and the vertical read start signal VRS is at the vertical level. A signal VSE for superimposing the high level "H" from the AND circuit 431 only while the read number signal VRT is at the low level "L".
The conditions are satisfied in the vertical direction in which L is output. Therefore,
In the 3-port video memory 310, the digital RGB signal WLDR is read based on the horizontal read permission during this period.

Next, the vertical offset of the 3-port video memory 310 will be described with reference to FIG. When the vertical synchronizing signal RV becomes high level “H” (FIG. 13A)
The vertical read offset counter 426 is reset and starts counting the number of clocks of the horizontal reference read dot clock signal HBDCK. While the vertical read offset counter 426 counts clocks up to the value N426 set by the CPU 620, the vertical read offset signal VROFT is given to the port 1 line increment INC1 of the 3-port video memory 310 via the OR circuit 432. ))) 3-port video memory 310
The vertical read address value of is offset.

At this time, since the NOR circuit 433 is supplied with the vertical synchronizing signal RV and the vertical read offset signal VROFT, the read enable signal RE1 (negative logic).
Is the read enable terminal R of the 3-port video memory 310
The vertical read offset counter 426 stops outputting the vertical read offset signal VROFT until the arrival of the next vertical synchronization signal RV because the vertical offset is made when the value is given to E1 (negative logic) and counted up to the value set by the CPU 620. .

Next, horizontal read permission of the 3-port video memory 310 will be described with reference to FIG.
When the horizontal synchronization signal RH is output, the horizontal read start counter 422, the horizontal 64 clock counter 423, and the horizontal read number counter 424 are reset, and the horizontal read start signal HRSA, the horizontal read reference signal HRSB, and the horizontal read number signal HRT go low. Level "L" (Fig. 14
(D), (e), (f)). Therefore, the horizontal read start counter 422 is used for the horizontal reference read dot clock generator 4
21 output horizontal reference read dot clock signal HBD
The number of CK clocks is counted, and the count value is CP
When the value N421 set in U620 is reached, the horizontal read start signal HRSA is set to high level "H" (see FIG. 14 (d)). When the horizontal read start signal HRSA becomes high level “H”, the horizontal 64 clock counter 423 starts counting the number of clocks of the reference read dot clock signal HBDCK, and when the count value becomes 64, the horizontal read reference signal HRSB is set to high. Set to level "H" (Fig. 14 (e)
reference). Then, the horizontal read dot clock generator 425
Are phase locked to the horizontal read reference signal HRSB. The horizontal 64 clock counter 423 generates a high level "H" of the horizontal read reference signal HRSB at a count value of "64" due to the characteristics of the 3-port video memory 310.
It is not limited to 64.

When the horizontal read reference signal HRSB becomes the high level "H", the horizontal reading of the 3-port video memory 310 is permitted, and the horizontal read number counter 424 indicates the horizontal reference read dot clock signal HBDCK.
Starts counting the number of clocks, and the count value is C
When it reaches the value N424 set by the PU 620, the horizontal read number signal HRT is set to the high level "H" (see FIG. 14 (f)).

When the vertical read start signal VRS is at the high level "H" and the vertical read number signal VRT is at the low level "L", the horizontal read reference signal HRSB is at the high level "H" and the horizontal read number signal. Only when the HRT is at the low level "L", the AND circuit 431 receiving the horizontal read number signal HRT outputs the switching signal VSEL for permitting the superimposition at the high level "H". Therefore, in the 3-port video memory 310, the digital RGB signal WLDR is read based on the read permission in the vertical direction during this period.

Next, in the horizontal reading of the 3-port video memory 310, the superimposing signal VSEL described with reference to FIG. 15 becomes the high level “H” (see FIG. 15C), and the horizontal reading is performed. Based on the clock of the horizontal read dot clock signal HDDA output by the dot clock generator 425 (see FIG. 15B), the digital signal WLDR is read from the 3-port video memory 310 and the analog of the DA converter 410 is read. The conversion is done. Read enable signal RE at this time
1 is also shown (see FIG. 15 (d)).

On the other hand, as shown in FIG. 8, the video signal VVS2
Is input to the point A of the video switch 510, is read from the 3-port video memory 310, and is D-A converter 41.
The video signal VVS3 analog-converted by 0 is input to the point B of the video switch 510. Therefore, the video switch 510 is switched by the switching signal VSEL for superimposing.
Of the video signal VVS4, which is the output of the video signal VVS3, after the phase correction in the image represented by the video signal VVS2.
It represents an image in which the image represented by is embedded (superimposed). The video signal VVS4 is
It is composed of RGB signals output from the video switch 510 to the output terminal 505 and synchronization signals RH and RV output to the output terminals 490 and 491.

The above timing chart is an example, and the above operation can be performed even if each signal has a positive logic or a negative logic.

Further, in FIG. 8, when the switching signal VSEL for superimposing the high level "H" is output to the tri-state circuit 434 via the NOT circuit 436, the tri-state circuit 434 operates. ,
The horizontal read dot clock signal HDDA is sent as the drive clock signal HDCK. On the contrary, when the superimposing signal VSEL is at the low level “L”, the tri-state circuit 435 operates and the horizontal reference read dot clock signal HBDCK outputs the drive clock signal HDCK.
Is given to the 3-port video memory 310 as

That is, when the superimposing is performed with the switching signal VSEL for superimposing being at the high level "H", the horizontal read dot clock generator 4
The 3-port video memory 310 is accessed by the horizontal read dot clock HDDA output from the digital signal 25, and the digital RGB signal W is transmitted at a speed sufficient for superimposing.
The LDR is read. On the other hand, when the superimposing signal VSEL is at the low level “L” and superimposing is not performed, the 3-port video memory 310 is accessed by the horizontal reference read dot clock HBDCK output from the horizontal reference read dot clock generator 421. Then, the address is stepped up to the horizontal read offset point, and the digital RGB signals in the horizontal / vertical region where superimposing is not performed are skipped, so to speak.
The next superimposing signal VSEL is prepared for the timing when it becomes the high level "H".

From the above, as shown in FIG.
The position where the video signal VVS3 is superimposed on the video signal VVS2 is the vertical read start signal VRS from the vertical read start counter 428 in the vertical direction and the horizontal read start signal HR from the horizontal read start counter 422 in the horizontal direction.
Determined by SA. Further, the display size to be superimposed is such that the vertical read number counter 42
The vertical read number signal VRT from the horizontal read number signal HRT from the horizontal read number counter 424 determines the horizontal direction.

Further, as shown in FIGS. 11A and 11B, in order to enlarge / reduce the image by the image signal VVS3, in the vertical direction, the vertical read line clock generator 43 is used.
When the frequency of the vertical read line clock signal VRLCK of 0 and the horizontal read dot clock signal HDDA of the horizontal read dot clock generator 425 in the horizontal direction are lowered, the display is enlarged, and when it is increased, the display is reduced.

FIG. 16 is an explanatory diagram showing an example of the sizes of the two images superimposed according to the first embodiment. Here, the video VVS2 represented by the second video signal VVS2
X is the entire screen of MS-WINDOWS, the first video signal VVS1 is the video signal of MS-DOS, video signal VV
An image VVS3X represented by an image signal VVS3 obtained by phase-correcting S1 is used as a DOS-BOX window. DOS-BOX window VVS3X is MS-
It is possible to easily display the reduced size VVS3XXZ or the enlarged size VVS3XX at an arbitrary position on the WINDOWS screen VVS2X.

Also, when the video VVS3X is displayed as shown in FIG. 16, the CPU 620 can concentrate on the processing of the MS-DOS without being involved in the display of the video VVS3X. Therefore, there is an advantage that a high-speed process can be realized as compared with the case where the CPU 620 performs the process of transferring the DOS-BOX video data from the first video storage unit 12 to the second video storage unit 13 as in the related art.

Note that MS-WINDOWS and MS-DO
Even if the resolution of S is the same, MS-WINDOW
It is possible to easily reduce the screen display size of MS-DOS to a DOS-BOX display screen within the WS display screen. Further, the shape of the DOS-BOX display can be made complicated by using a chroma key.

FIG. 17 is an explanatory diagram showing a case where the image after the phase correction is enlarged / reduced. As shown in FIG. 17A, when the two types of video signals VVS1Y and VVS2Y are video signals having the same image display density (horizontal 640 dots × vertical 480 lines), according to the present invention, FIG.
As shown in (b), the display area can be reduced while displaying a part of the image in an enlarged manner so that the image can be displayed as an image VVS3Y. Further, as shown in FIG. 16C, it is possible to display the image VVS3YY in which the display area is reduced while reducing the entire image.

As another application example, the present invention processes a plurality of video signals introduced into a personal computer as shown in FIG. 1, but an input terminal for inputting an NTSC standard video signal from the outside. And a decoder may be provided. In this case, a second video switch is newly inserted between the output of the first video controller 10 and the phase corrector 14. The second video switch may be the same switch as the video switch 15 shown in FIG. 1, one terminal of this switch is an input terminal of the NTSC signal, and the other terminal is an output terminal of the first video control unit 10. And the both are switched by the second video switch, and the output end thereof is input to the phase correction unit 14. As a result, not only the video signal of the personal computer is subjected to the phase correction, but also the NTSC signal which is similarly used as a general television signal can be applied to the present invention.

D. Second Embodiment: FIG. 18 is a block diagram showing a configuration of a phase correction section and its peripheral circuit in a second embodiment of the present invention. The writing control unit 200a of the phase correction unit is similar to the writing control unit 200 of the phase correction unit of the first embodiment shown in FIG.
30 and a CPU data writing control unit 340 are added. The CPU data writing control unit 340 includes the CPU 62
Video data given from 0 to 3 port video memory 31
Controls when writing to 0. The video memory control signal selection unit 330 selects one of the write control signals supplied from the digitizing control unit 220 and the CPU data write control unit 340 and supplies it to the 3-port video memory 310.

A video data selection section 320 is inserted between the A / D converter 210 and the 3-port video memory 310. The video data selection unit 320 selects one of the video data supplied from the CPU 620 via the CPU data write control unit 340 and the video data WLD output from the AD converter 210 to select 3 ports. Video memory 3
Supply to 10.

In the circuit of FIG. 18, the operation of writing the video data in the 3-port video memory 310 is performed as follows. First, the CPU 620 switches the video data selection unit 320 and the video memory control signal selection unit 330 to the CPU data writing control unit 340 side by causing the CPU data writing control unit 340 to output the switching control signal CC. By this switching, the 3-port video memory 310 does not receive the write control signal WCONT output from the digitize control unit 220 but the CPU data write control unit 34.
The write control signal WEPC output from 0 is applied. That is, the digital RGB signal output by the CPU 620 is transferred to the 3-port video memory 31 via the CPU data write control unit 340 and the video data selection unit 320.
Given to 0. As a result, the 3-port video memory 310
In accordance with the write control signal WEPC sent from the CPU data write control unit 340, the digital RGB signal given by the CPU 620 is written in the. The digital RGB signal thus stored in the 3-port video memory 310 is read out under the control of the superimpose control unit 420.

As described above, in the second embodiment shown in FIG. 16, it is possible to directly write the image supplied from the CPU 620 to the 3-port image memory 310 and display it.

E. Third Embodiment: FIG. 19 is a block diagram showing the configuration of a computer system including a video display device according to a third embodiment of the present invention. This computer system includes n video control units from a first video control unit 10 to an nth video control unit 21 and a first video storage unit 12.
To n-th image storage unit 22 and n-th image storage units from the second phase correction unit 14 to the n-th phase correction unit 23 (n−
1) phase correction units and (n-1) video switches from the second video switch 15 to the nth video switch 24 are provided. When the combination of the image control unit, the image storage unit, the phase correction unit, and the video switch is called an image superimposing unit, it can be said that the computer system in FIG. 19 includes (n-1) sets of image superimposing units.

From the first video storage unit 12 to the nth video storage unit 2
The n video storage units up to 2 are under the control of different OSs, and the videos from the different OSs are displayed on the monitor 1.
6 is displayed within the screen. FIG. 20 is an explanatory diagram showing a state in which the images stored in the first to nth image storage units 12, 13, 18, and 22 are superimposed and displayed on the monitor 16. Note that some of the plurality of video storage units may be under the control of the same OS. In this way, by providing the image superimposing units in multiple stages, it is possible to superimpose and display three or more images. Also in this case, since the CPU 620 does not need to transfer the video data between the video storage units, the superimposed video can be displayed at high speed.
620 can perform processing other than display.

The present invention is not limited to the above embodiments, and can be implemented in various modes without departing from the scope of the invention.

[0134]

As described above, according to the first aspect of the invention, the first phase correction section synchronizes the first video signal with the synchronization signal of the second video signal. The two video signals can be switched and displayed by simply switching the two video signals by the video switch and outputting them to the monitor. Therefore, it is possible to display two images at high speed while switching between two images without transferring the contents of the first image storage unit to the second image storage unit by the CPU.

According to the second aspect of the present invention, the first phase correction section synchronizes the first video signal with the synchronization signal of the second video signal. The video signal can be switched and output to the monitor.

According to the third aspect of the present invention, the first video signal is stored in the frame storage unit in synchronization with the synchronization signal and is read in synchronization with the synchronization signal of the second video signal. The first video signal can be synchronized with the synchronization signal of the second video signal.

According to the invention described in claim 4, two video signals are switched by the first video switch, and
Two images can be displayed in a superimposed state.

According to the invention described in claim 5, it is possible to display a video by processing the first video signal which is an analog video signal.

According to the invention described in claim 6, the image can be scaled when writing the first image signal in the frame storage section.

According to the invention described in claim 7, the image can be scaled when the first image signal is read from the frame storage section.

According to the invention described in claim 8, it is possible to switch and display two video signals representing videos having different display resolutions.

According to the invention described in claim 9, three images can be switched and displayed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system including a video display device as an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing functions of a phase correction unit 14 and a video switch 5.

FIG. 3 is a block diagram showing a schematic configuration of a phase correction unit 14.

FIG. 4 is a block diagram showing the configurations of a phase correction unit 14 and a video switch 15.

FIG. 5 is a detailed block circuit diagram of a digitizing controller 220 and its peripheral circuits.

FIG. 6 is an explanatory diagram showing a function of set values of each circuit in the digitizing control section 220.

FIG. 7 is a timing chart showing the operation of the digitize control unit 220.

FIG. 8 is a detailed block circuit diagram of a superimpose control unit 420 and its peripheral circuits.

9 is an explanatory diagram showing an input / output circuit of a horizontal synchronizing signal RH and a vertical synchronizing signal RV in a superimpose control section 420. FIG.

FIG. 10 is a block diagram showing the configuration of a PLL circuit 63.

11 is an explanatory diagram showing the function of set values of each circuit in the superimpose control unit 420. FIG.

FIG. 12 is a timing chart of vertical read permission of the 3-port video memory 310.

13 is a timing chart of vertical offset of the 3-port video memory 310. FIG.

FIG. 14 is a timing chart of horizontal read permission of the 3-port video memory 310.

FIG. 15 is a timing chart of horizontal reading from the 3-port video memory 310.

FIG. 16 is an explanatory diagram showing an example of sizes of two superimposed images.

FIG. 17 is an explanatory diagram showing a case where an image after phase correction is enlarged or reduced.

FIG. 18 is a block diagram showing the configuration of a phase correction unit in the second embodiment.

FIG. 19 is a block diagram showing the configuration of a computer system including a video display device as a third embodiment of the present invention.

FIG. 20 shows first to n-th video storage units 12, 13, 1.
Explanatory drawing which shows the state in which the video memorize | stored in 8 and 22 was superimposed and displayed on the monitor 16.

FIG. 21 is a block diagram showing the configuration of a conventional computer system.

FIG. 22 is a memory map showing a memory space under the control of MS-Windows.

FIG. 23 shows a first image 1531 in a second image 1530.
Explanatory drawing which shows the state in which is displayed.

[Explanation of symbols]

 2 ... RAM 3 ... ROM 4 ... I / O section 5 ... Video switch 6 ... Mouse 7 ... External storage section 8 ... Communication section 10 ... First video control section 11 ... Second video control section 12 ... First video storage section 13 ... second video storage unit 14 ... phase correction unit 15 ... video switch 16 ... multi-scan monitor 21 ... nth video control unit 22 ... nth video storage unit 24 ... nth video switch 61, 62 ... buffer 63 ... PLL circuit 71 ... phase comparator 72 ... low-pass filter 73 ... VCO 74 ... N minute cycle 1500 ... CPU 1501 ... RAM section 1502 ... ROM section 1503 ... I / O section 1504 ... Keyboard 1505 ... Mouse 1506 ... External storage section 1507 ... Communication section 1510 ... First video control unit 1511 ... Second video control unit 1512 ... First video storage unit 1513 ... Second video storage unit 1514 ... Relay Circuit section 1515 ... Monitor 200 ... Write control section 210 ... A / D converter 220 ... Digitize control section 221 ... Horizontal write dot clock generation circuit 222 ... Horizontal write start counter 223 ... Horizontal write number counter 224 ... Vertical write Input line clock generation circuit 225 ... Vertical writing start counter 226 ... Vertical writing number counter 227 ... Vertical writing offset counter 228 ... OR circuit 229 ... AND circuit 230 ... NOR circuit 310 ... 3-port video memory (frame storage unit) 320 ... video data selection unit 330 ... video memory control signal selection unit 340 ... CPU data write control unit 400 ... read control unit 410 ... DA converter 420 ... superimpose control unit 421 ... horizontal reference read dot clock generator 422 Horizontal read start counter 424 Horizontal read count counter Unter 423 ... horizontal 64 clock counter 425 ... horizontal read dot clock generator 426 ... vertical read offset counter 427 ... vertical blanking number counter 428 ... vertical read start counter 429 ... vertical read number counter 430 ... vertical read line clock generator 431 ... AND circuit 432 ... OR circuit 433 ... NOR circuit 434 ... Tristate circuit 435 ... Tristate circuit 436 ... NOT circuit 490, 491 ... Sync signal terminal 490 ... Sync signal terminal 505 ... Output terminal 506 ... Input terminal 507 ... Sync signal terminal 508 Sync signal terminal 510 Video switch 610 CPU bus 620 CPU BSYNC Basic sync signal C Common terminal CC Switching control signal CKAD Clock signal CKDA Clock signal CNT Switching signal input Input terminal HBDCK ... Horizontal reference read dot clock signal HDCK ... Memory drive clock signal HDDA ... Horizontal read dot clock signal HRDCK ... Horizontal read dot clock signal HRSA ... Horizontal read start signal HRSB ... Horizontal reference start signal HRST ... Horizontal read direction reset signal HRT Horizontal read count signal HWDCK Horizontal write dot clock signal HWS Horizontal write start signal HWT Horizontal write count signal MH1 ... Magnification ratio MH2 ... Magnification ratio MV1 ... Reduction ratio MV2 ... Magnification ratio MRST ... Memory vertical / horizontal reset Signal RADD ... Read address RCONT ... Read control signal RE1 ... Read enable signal RH ... Horizontal sync signal RL ... Luminance signal RSE ... Selection signal RSYNC ... Sync signal RV ... Vertical sync signal VBE ... Vertical blanking end signal VRLCK ... Vertical read line Clock signal VROFT ... vertical read offset signal VRS ... vertical read start signal VRT ... vertical read number signal VSEL ... switching signal VWLCK ... vertical write line clock signal VWOFT ... vertical write offset signal VWS ... vertical write start signal VWT ... vertical Write count signal WADD ... Write address WCONT ... Write control signal WE ... Write enable signal WENBL ... Write enable signal WEPC ... Write control signal WH ... Horizontal synchronization signal WL ... Luminance signal WLD ... Video data to be written (luminance data ) WLDR ... Read out video data (luminance data) WLR ... Luminance signal WV ... Vertical sync signal

Claims (9)

[Claims] 1. A video display device for use in a computer system for displaying a video on a monitor, comprising: a first video storage unit managed by a first operating system; and the first video storage unit. A first video control unit for reading and outputting the first video signal stored in the second video storage unit; a second video storage unit managed by a second operating system; and a second video storage unit stored in the second video storage unit. A second video control unit that reads and outputs a second video signal; a first phase correction unit that synchronizes the first video signal with a synchronization signal of the second video signal; and the second video A video signal and a first video switch for selecting one of the first video signals corrected by the first phase correction unit and outputting the selected video signal to the monitor. . 2. The video display device according to claim 1, wherein the first and second video signals are asynchronous with each other. 3. The video display device according to claim 2, wherein the first phase correction unit uses a frame storage unit that stores the first video signal, and a synchronization signal of the first video signal. A writing control unit for writing the first video signal in the frame storage unit in synchronization, and the first video signal stored in the frame storage unit as a synchronization signal of the second video signal. And a read control unit that reads the data in synchronism with the first video switch and supplies the first video switch with the read control unit. 4. The video display device according to claim 3, wherein the read control unit indicates that the first video signal is selected in the video region of the first video signal, and the display region is displayed. An image display device, further comprising: a selection signal generation unit that gives a selection signal indicating selection of a second video signal to the first video switch outside. 5. The video display device according to claim 3, wherein the first phase correction unit further A / D converts the first video signal, which is an analog signal, to store the frame. A-D converting means for giving to the first section, and the first video signal after the phase correction, which is the digital signal read from the frame storing section, is D-A converted and given to the first video switch. A video display device comprising: a conversion unit. 6. The video display device according to claim 3, wherein the write control unit sets a horizontal timing when writing the first video signal in the frame storage unit. A first PLL circuit for creating a specified horizontal writing dot clock signal from the synchronization signal of the first video signal, and a vertical direction timing when writing the first video signal in the frame storage unit A second PLL circuit for creating a vertical writing line clock signal to be defined from the synchronizing signal of the first video signal, and the horizontal writing dot clock signal by the first and second PLL circuits. A video display device for scaling the video stored in the frame storage unit by adjusting the frequency of each of the vertical write line clock signals. 7. The video display device according to claim 3, wherein the read control unit is a horizontal display device for reading the phase-corrected first video signal from the frame storage unit. A third PLL circuit for creating a horizontal read dot clock signal that defines the timing of the direction from the synchronization signal of the second video signal; and reading the first video signal after the phase correction from the frame storage unit. A fourth PLL circuit for creating a vertical read line clock signal that defines vertical timing when outputting from the synchronizing signal of the second video signal, and by the third and fourth PLL circuits, A video display device for scaling a video read from the frame storage unit by adjusting frequencies of a horizontal read dot clock signal and a vertical read line clock signal, respectively. 8. The video display device according to claim 1, wherein the first and second video signals are video signals representing video images having different display resolutions. 9. The video display device according to claim 1, further comprising a third video storage unit managed by a third operating system, and the third video storage unit. A third video control section for reading and outputting the stored third video signal; and a second phase for synchronizing the video signal output from the first video switch with a synchronization signal of the third video signal. An image display device comprising: a correction unit; a third video signal; and a second video switch that selects one of the video signals corrected by the second phase correction unit and outputs the selected video signal to the monitor. .