JPH0797127B2 - Terminal control device - Google Patents

Description

The present invention relates to a terminal control device that can be applied to, for example, an IC test device.

"Background of the Invention" In an IC tester for testing an IC composed of digital circuits, a pattern signal is applied from a pattern generator 1 to a subject 2 as shown in FIG. The expected value pattern signal output from 1 is compared by the logical comparator 3, the coincidence and non-coincidence are judged, and each time the non-coincidence is detected, the address where the non-coincidence occurs and the information such as the pattern signal are stored in the fail memory 4. The occurrence of a defect and the state of the defect are stored, and the number of defective memory cells and the like are totaled to determine the quality of the subject 2.

As a method of giving a pattern signal to the subject 2, a method of directly giving a pattern signal from the pattern generator 1 to each terminal of the subject 2 and a buffer memory corresponding to each terminal of the subject 2 as shown in FIG. There is a system in which the provided terminal device 5 is installed and a pattern signal is given from the terminal device 5.

That is, the test device using the terminal device transfers the pattern signal to be given to each terminal from the pattern generator 1 to the terminal device 5 in advance, stores the pattern signal in the buffer memory provided in each terminal device 5, and executes the test. At the start, the pattern signals are simultaneously read from the respective terminal devices 5, the pattern signals are given to the respective terminals of the subject 2, and the response output of the subject 2 is taken into another buffer memory to perform the operation.

The response output signal fetched in the buffer memory is sequentially read out, given to the logical comparator 3, and compared with the expected value pattern.

In this way, by giving the pattern signal to the subject 2 from the terminal device 5, the pattern signal can be given to the subject at a high speed, and the test time can be shortened.

The number of terminals of the subject 2 tends to increase, and there are several hundreds. Therefore, the number of terminal devices 5 must be provided in the same number.

Since the pattern signal given to each terminal of the subject 2 is different for each terminal, each terminal device has a pattern generator 1
Must transmit different pattern signals from each. For this purpose, each terminal device 5 must be numbered one by one and must be structured so that it can be accessed separately.

“Prior Art” Conventionally, as shown in FIG. 6, each terminal device 5 is provided with a DIP switch 6, and the DIP switch 6 sets a digital value corresponding to the number assigned to each terminal device 5, Is supplied to the coincidence detector 7, the terminal number sent through the control bus line 9 and the terminal number set in the DIP switch 6 are collated, and in a state of coincidence, for example, a pattern signal sent through the data bus line 11 Is taken into the buffer memory 12 or the response force of the subject 2 taken into the buffer memory 12 is output to the main unit 1 through the data bus line 11.
Reference numeral 8 denotes a latch circuit for temporarily storing the control signal.

[Problems to be Solved by the Invention] Conventionally, each terminal is provided with a DIP switch 6, and the number assigned to each terminal is set by this DIP switch 6. Since the number of terminal devices reaches several hundreds as described above, the number is extremely large. As described above, since the number of a large number of terminals is set by the DIP switch 6, there is a drawback that the setting work is troublesome. In particular, when the board forming the terminal device is replaced, the terminal number of the DIP switch 6 must be reset each time, which is troublesome. In addition, unless the setting is changed properly, it will not operate normally, and management of the terminal number will be very troublesome.

"Means for Solving Problems" In the present invention, in a terminal control device including a main device and a plurality of terminal devices, a clock input terminal and a clock output terminal provided in each terminal device, a clock input terminal and a clock A predetermined number of clock pulses applied to the clock input terminals connected between the clock input terminal and the clock output terminal inside each terminal equipment, and the clock transmission line in which the output terminals are cascaded outside the terminal equipment. Gate means for increasing or decreasing and sending to the clock output terminal, and a counter for counting the number of clock pulses input to the gate means or the number of clock pulses output from the gate means as a terminal number assigned to the terminal device. And a control provided on each terminal device for specifying the terminal device on the control path line. A decoder for detecting the presence of a signal, a latch circuit for fetching data representing a terminal number on a data bus line by the detection signal when the decoder detects a control signal for designating a terminal device, and this latch circuit The terminal control device is configured by a coincidence detector that detects a coincidence between the terminal number taken in by the terminal and the terminal number counted by the counter.

According to the structure of the present invention, by sending a clock pulse from the main device to the clock transmission line, each terminal device increases or decreases the number of clocks by a fixed amount and transmits it to the next terminal device.

As a result, by counting the number of clock pulses input to each terminal device or the number of clock pulses output by the counter, it is possible to know how many stages the clock pulse train has passed through the terminal device. Therefore, the terminal devices can be sequentially numbered according to the count value of the counter.

Further, in the present invention, each terminal device is provided with a decoder, and a control signal is given to this decoder through a control pass line.
The decoder detects the control signal designating the terminal number from the control signals. When the decoder detects the control signal designating the terminal number, this detection signal is given to the latch circuit to cause the latch circuit to latch the terminal number existing on the data bus line. The terminal number latched in the latch circuit is compared with the terminal number counted in the counter, and when they match, it is recognized that the terminal is designated.

Therefore, according to the present invention, the operation of assigning a number to each terminal device can be automatically performed by the clock transmission line, the gate means provided in each terminal device, and the counter.

Further, each terminal device can be controlled individually by the device number assigned to each terminal device.

[Embodiment] FIG. 1 shows an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals.

That is, in the figure, 1 is a pattern generator that functions as a main device, 2 is a subject, and 5 is a plurality of terminal devices. In the example of the figure, the case where six terminal devices 5 are provided is shown. The logical comparator 3 and the fail memory 4 described with reference to FIGS. 5 and 6 are omitted here.

In the present invention, each terminal device 5 has a clock input terminal 14
And a clock output terminal 15 are provided, and the clock input terminal 14 and the clock output terminal 15 are connected in series outside the terminal devices 5 by a clock transmission line 16.

Gate means 17 is provided inside each terminal device 5, and the gate means 17 is connected between the clock input terminal 14 and the clock output terminal 15. The gating means 17 has the function of increasing the number of clock pulses applied by a certain amount or decreasing it by a certain amount. As a concrete example thereof, for example, it can be configured as shown in FIG.

The example shown in FIG. 2 shows a case in which the number of clock pulses input to the clock input terminal 14 is reduced by 1 and output to the clock output terminal 15.

That is, the gate means 17 is a D-type flip prop in this example.
17A and AND GATE 17B. The clock pulse input to the clock input terminal 14 is input to the AND gate 17B through the D-type flip prop 17A. As shown in FIG. 3C, the D-type flip-flop 17A outputs the H logic to the output terminal Q at the falling edge of the _first clock pulse P ₁ .

The output of the D-type flip-flop 17A is given to the AND gate 17B and controls the AND gate 17B to open. Therefore, the pulse after the _second clock pulse P ₂ following the clock pulse P ₁ is output from the AND gate 17B, and these pulses P ₂ , P ₃
Is output to the clock output terminal 15.

Clock pulses P ₂ and P ₃ taken out at clock output terminal 15
... is given to the clock input terminal 14 of the terminal device 5 at the next stage. In the terminal device 5 at the next stage, the leading clock pulse
P ₂ is removed and P ₃ , P ₄ ... Are output as shown in FIG. 3E. In the next terminal device, the first clock pulse
By removing P ₃ , clock pulses P ₄ , P are generated as shown in FIG. 3G.
₅ ... is output.

In this way, the gate means 17 of each terminal device 5 removes the leading one of the clock pulses applied to the clock input terminal 14 and transmits the remaining clock pulses to the next stage. Note that one pulse may be added instead of removing one clock pulse. Further, the number of pulses to be removed or the number of pulses to be added is not limited to one.

On the other hand, each terminal device 5 is provided with a counter 18. The counter 18 counts the clock applied to the clock input terminal 14 of each terminal device 5 or the clock output to the clock output terminal 15. The embodiment shows a case where the clocks applied to the clock input terminal 14 are counted.

When the number of clock pulses output from the main device 1 is M, the number K of clock pulses counted by the counter 18 is K = M- (N-1) according to the number N of stages of the terminal device 5.
That is, K = M is counted in the counter 18 of the terminal device in the first stage. The counter 18 of the second-stage terminal device has K = M
-1 is counted. In this way, the counter 18 of each terminal device can obtain the count value of the value obtained by M- (N-1) the number N of stages of each terminal from the number M of clock pulses output from the main device 1. The number M of clock pulses output from the main device 1 is selected so that M> N with respect to the number N of stages. By selecting in this way, it is possible to add terminal devices. The number Nmax of expandable terminal devices is Nmax = M.

In this way, since the terminal device number can be attached to each counter 18 of each terminal device 5, the numbering setting work is not necessary at all, and the adjustment is easy. Further, the clock pulse output to the clock output terminal 15 of the terminal device at the final stage is fed back to the main unit 1, and the difference MP between the number M of clock pulses sent and the number P of clock pulses fed back is obtained. The total quantity of the terminal devices 5 can be known by.

In the present embodiment, the terminal number 5 is designated by using the device number counted by the counter 18, and each terminal device 5 is individually controlled. The configuration will be described below.

The count value of the counter 18 is supplied to the coincidence detector 19. The latch output signal of the latch circuit 21 is applied to the other input terminal of the coincidence detector 19. The latch circuit 21 executes a latch operation according to the detection signal of the decoder 22. The decoder 22 monitors the control signal output from the main unit 1 to the control bus line 9 and detects a command signal for specifying a terminal from the control signals. In addition to the terminal designation control signal, the control bus line 9 receives a command signal for fetching the pattern data sent from the main device 1 to the data bus line 11 by the designated terminal and the pattern data fetched by the terminal device. A command signal to be sent to the body 2, a command signal to take in the response output of the subject 2 to each terminal device, and a command signal to send the response output of the subject 2 taken in to each terminal device to the main device 1 through the data bus line 11. Etc. are transmitted.

When the decoder 22 detects a command signal for designating a terminal, the detection output is given to the latch circuit 21 and the latch circuit 21 latches the number data of the terminal to be designated sent from the main unit 1 to the data bus line 11. It Therefore, in that state, the same terminal number is latched in each latch circuit 21 of all the terminal devices 5. The latched terminal number is collated with the count value of the counter 18 by the coincidence detector 19 to determine coincidence or non-coincidence.

When a match is detected as a result of the determination, the match detector 19 outputs a match detection signal, recognizes that this terminal device is designated by this match detection signal, and then responds to a command signal output to the control bus line 9. To perform the action.

When the operation of the designated terminal device 5 is completed, a reset signal is given to all the terminal devices through the reset signal line 10 to reset each circuit such as the decoder 22, the counter 18, the latch circuit 21 and the like.

As the operation of the terminal device 5, the main device 1 is stored in the buffer memory 25.
The data output from the data bus line 11 to the subject 2 is output to the subject 2, or the response output signal of the subject 2 is stored in another storage area of the buffer memory 25. Or to transfer the response output data of the subject 25 stored in the buffer memory 25 to the main unit 1 through the data bus line 11. Which of these operations is performed is selected by a control signal sent through the control bus line 9.

Reference numeral 26 denotes a parallel-serial converter that converts a parallel signal stored in the buffer memory 25 into a serial signal when a pattern signal is given from the buffer memory 25 to the subject 2, and 27 also converts a response output signal of the subject 2 into a parallel signal. Then, it is a serial-to-serial converter for writing in the buffer memory 25.

[Operation and Effect of the Invention] As described above, according to the present invention, each terminal device 5 is connected in cascade through the gate means 17, and a clock pulse train is applied from one end side of this cascade connection. The number of clock pulses supplied to the clock input terminal or the clock output terminal of each terminal device 5 is counted by decreasing the number of pulses in the clock pulse train by a predetermined number or by increasing the number by a predetermined number. You can know if you have passed the terminal device.

Therefore, each terminal device can be numbered by counting the number of clock pulses input to or output from each terminal device.

Therefore, according to the present invention, it is not necessary to provide a setting means such as a DIP switch for assigning a number to each terminal device, so that the adjustment can be easily performed. Further, the terminal device can easily manage the terminal device without changing the setting even if the connection position is changed.

Further, when adding a terminal device, there is no need to change the number setting of the existing terminal device. Therefore, there is an advantage that expansion can be easily performed.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, FIG. 2 is a connection diagram for explaining a concrete example of the gate means shown in the embodiment of FIG. 1, and FIG. FIG. 4 is a waveform diagram for explaining the operation of the gate means shown in FIG. 2, FIG. 4 is a block diagram for explaining an IC test device suitable for applying the terminal control device, and FIG. 5 is a conventional IC test. FIG. 6 is a block diagram for explaining an example of a terminal control device in the apparatus, and FIG. 6 is a block diagram for explaining a conventional terminal control device. 1: Main device, 5: Terminal device, 9: Control bus line, 10: Reset signal line, 11: Data bus line, 14: Clock input terminal, 15: Clock output terminal, 16: Clock transmission line, 17: Gate Means, 18: Counter, 19: Match Detector, 21:
Latch circuit, 22: Decoder.

Claims (1)

[Claims] 1. A. A main device and a plurality of terminal devices connected to a control bus line and a data bus line derived from the main device. The main device designates the terminal device, and a plurality of terminal devices are provided. B. Clock input terminal and clock output terminal provided on each terminal device, and C. Clock input terminal and clock output terminal on the outside of each terminal device in sequence. D. a clock transmission line that is provided inside each terminal device, and a gate means that increases or decreases a fixed number of clock pulses to the clock pulse provided to the clock input terminal and sends the clock pulse to the next terminal device. , E. Given to the terminal device the number of pulses input to this gating means or the number of clock pulses output from this gating means. F. A decoder that detects the presence of a control signal for designating the terminal device on the control bus line, and G. A state in which this decoder detects a control signal that designates the terminal device. H. A latch circuit that takes in the data representing the terminal number on the data bus line by the detection signal, and H. A coincidence detector that detects the coincidence between the terminal number taken in this latch circuit and the terminal number counted in the counter. And a terminal control device configured by.