JPH0786580A - High voltage semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a high breakdown voltage MOSFET capable of simultaneously improving breakdown voltage, insulation isolation and ON resistance. A p ^- type active layer 3 provided on a semiconductor substrate 1 via an insulating layer 2, a p ⁺ -type base layer 4a selectively formed on the surface of the p ^- type active layer 3, and n ⁺ type source layer 5 selectively formed on the surface of p ⁺ type base layer 4a
An n-type offset layer 7 selectively formed on the surface of the p ⁻ type active layer 3 and not reaching the insulating layer 2, and an n ⁺ type drain layer selectively formed on the surface of the n type offset layer 7. 6
And a gate electrode 10 provided via a gate oxide film 11 on a region between the n ⁺ type source layer 5 and the n ⁺ type drain layer 6, and the n type offset layer 7 has a diffusion depth thereof. Is 1 to 2 μm, and the dose amount is 2 to 3 × 10 ¹² cm ⁻² .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device composed of a MOSFET.

[0002]

2. Description of the Related Art In recent years, an integrated circuit (IC) formed by integrating a large number of transistors, resistors and the like so as to achieve an electric circuit and forming them on one chip has been widely used in important parts of computers and communication equipment. ing. IC like this
Among them, a device including a high breakdown voltage element is called a power IC. Among the power ICs, the one in which the drive circuit and the control circuit are integrated is a display drive device, an in-vehicle IC, or the like.
It can be used for many purposes. This kind of power IC
In the MOSFET used in the output stage of, the high drain breakdown voltage and the low on resistance are required.

FIG. 8 is a cross-sectional view of an element showing the structure of a high breakdown voltage MOSFET used in a conventional output stage. 7 in the figure
Reference numeral 1 denotes a p-type semiconductor substrate. On this p-type semiconductor substrate 71, a high-resistance n ⁻ -type active layer 72 is epitaxially grown. On the surface of the n ⁻ type active layer 72,
p-type base layer 74a and low-resistance p ⁺ -type base layer 74
b are selectively formed, and these base layers 74a,
An n ⁺ type source layer 75 is selectively formed on the surface of 74b. A source electrode 78 is provided on the p ⁺ type base layer 74 b and the n ⁺ type source layer 75.

An n-type offset layer 73 is selectively formed on the surface of the n ^-- type active layer 72, and an n ⁺ -type drain layer 76 is selectively formed on the surface of the n-type offset layer 73. Is formed in. A drain electrode 79 is provided on the n ⁺ type drain layer 76.

A gate electrode 80 having a field plate is provided on a region sandwiched by the n ⁺ type drain layer 76 and the n ⁺ type source layer 75 with a gate oxide film 81 interposed therebetween.

High breakdown voltage MOSFET configured as described above
According to the description, the n ⁺ -type drain layer 76 is the n-type offset layer 7
Since it is formed inside 3, the breakdown voltage becomes higher than that of a normal MOSFET.

However, this type of high voltage MOSFE
In T, the p-type semiconductor substrate 71 and the n ⁻ -type active layer 72
Although the pn junction isolation is performed by the method described above, there is a problem in that the elements cannot be sufficiently insulated and isolated and weak against noise.

Further, when used as a high side switch, in the ON state, the p type semiconductor substrate 71 and the n ⁺
Since the power supply potential is applied between the drain layer 76 and the drain layer 76, p
There is a problem that a depletion layer spreads in the vertical direction from the junction between the type semiconductor substrate 71 and the n ⁻ type active layer 72, and the on-resistance increases.

[0009]

As described above, the conventional high breakdown voltage MOSFET can secure the required breakdown voltage, but the insulation isolation between elements is insufficient. Further, when used as a high-side switch, there is a problem that a depletion layer spreads in the element and the on-resistance increases.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a high breakdown voltage semiconductor device capable of simultaneously improving breakdown voltage, insulation isolation, and on-resistance.

[0011]

In order to achieve the above object, a high breakdown voltage semiconductor device of the present invention has a high resistance semiconductor layer on a substrate whose surface is an insulating layer, and a high resistance semiconductor layer formed on the surface of the high resistance semiconductor layer. A first conductive type base layer selectively formed, a first second conductive type semiconductor layer selectively formed on the surface of the first conductive type base layer, and a surface of the high resistance semiconductor layer Second conductive type offset layer that is formed selectively and does not reach the insulating layer, a second second conductive type semiconductor layer selectively formed on the surface of the second conductive type offset layer, and the first A gate electrode provided via a gate insulating film on a region between the second conductive type semiconductor layer and the second second conductive type semiconductor layer, wherein the second conductive type offset layer is a diffusion layer thereof. The depth is 1-2 μm and the dose is 2-3 × 10 ^12.
It is characterized by being cm ⁻² .

[0012]

According to the present invention, since the elements are formed on the insulating layer, the elements can be separated more reliably than the conventional pn junction separation. Further, according to the research conducted by the present inventors, it has been found that, when the impurity concentration and the depth of the second conductivity type offset layer are selected as described above, good results can be obtained with respect to the breakdown voltage and the on-resistance. Therefore, according to the present invention, the insulation isolation, the breakdown voltage and the on-resistance can be improved at the same time.

[0013]

Embodiments will be described below with reference to the drawings. FIG. 1 shows a high breakdown voltage MO according to the first embodiment of the present invention.
It is an element sectional view showing an element structure of SFET.

In the figure, reference numeral 1 denotes a semiconductor substrate, on which a high resistance p ⁻ is provided via an insulating layer 2.
A mold active layer 3 is provided. The p ⁻ type active layer 3 is
For example, it is formed by an epitaxial growth method. This p
^- The surface of the mold active layer 3, p for low resistance p ⁺ -type base layer 4a, and p-channel formation for preventing punch Sulu
The type base layer 4b is selectively formed, and the n ⁺ type source layer 5 is selectively formed on the surfaces of these base layers 4a and 4b. A source electrode 8 is provided on the p ⁺ type base layer 4b and the n ⁺ type source layer 5.

An n-type offset layer 7 is selectively formed on the surface of the p ^-- type active layer 3. The n-type offset layer 7 has a dose amount of 2 to 5 × 10 ¹² cm ⁻² , for example.
After implanting the ion serving as the donor under the condition of 1., shallow diffusion is performed by heat treatment. The n ⁺ type drain layer 6 is selectively formed on the surface of the n type offset layer 7. A drain electrode 9 is formed on the n ⁺ -type drain layer 6.
Is provided.

A gate electrode 10 is provided on a region sandwiched by the n ⁺ type source layer 5 and the n ⁻ type drain layer 6 with a gate oxide film 11 having a thickness of about 15 nm interposed therebetween. This gate electrode 10 has a field plate,
This field plate serves to weaken the electric field at the drain end of the gate portion.

High breakdown voltage MOSFET configured as described above
According to the above, since the n ⁺ -type drain layer 6 is formed in the n-type offset layer 7, the breakdown voltage is higher than that of a normal MOSFET, and the insulating layer 2 is formed on the semiconductor substrate 1 via the insulating layer 2. Since the elements are formed by using the SOI substrate, that is, the elements are formed on the SOI substrate, the isolation between the elements becomes more complete than in the conventional case.

Furthermore, since the impurity concentration and the depth of the n-type offset layer 7 are selected as described above, both the breakdown voltage and the on-resistance can be improved. 5 and 6 are experimental data showing this.

FIG. 5 is a characteristic diagram showing the relationship between the dose amount to the offset region and the breakdown voltage when the diffusion depth is used as a parameter. From FIG. 5, the dose amount is 3 × 10 ¹² cm ^-2
With the above conditions, the breakdown voltage sharply decreases regardless of the diffusion depth. Further, when the diffusion depth is 1 μm or less, the peak of breakdown voltage is low and the region of the optimum dose amount is narrow. Therefore, a diffusion depth of at least 1 μm, more preferably 1.5 μm or more is required to obtain the required breakdown voltage. If the dose amount is in the range of 2 × 3 × 10 ¹² cm ⁻² , it is possible to obtain a sufficient breakdown voltage.

FIG. 6 is a characteristic diagram showing the relationship between the diffusion depth and the on-resistance when the dose amount is 2.7 × 10 ¹² cm ^-2 . It can be seen from FIG. 6 that the on-resistance decreases as the diffusion depth increases to 1.5 to 2 μm, but increases above that.

To summarize the above results, the n-type offset layer 7 has a diffusion depth of 1 to 2 μm and a dose of 2 to 3 × 1.
If it is 0 ¹² cm ^-2, it is possible to achieve both improvement in on-resistance and breakdown voltage.

FIG. 7 is a characteristic diagram showing the relationship between the dose amount and the breakdown voltage when the concentration of the p-type substrate is used as a parameter. When the dose is increased, it is about 2 × 10 ¹² cm ^-2
If the voltage exceeds, the breakdown voltage will drop rapidly. When the concentration of the p-type substrate is increased, the dose amount at which the breakdown voltage decreases can be increased, and the on-resistance can be reduced. However, when the concentration of the p-type substrate exceeds 1 × 10 ¹⁶ cm ^-2 , the breakdown voltage decreases, so p
The concentration of the mold substrate is preferably around 1 × 10 ¹⁶ cm ^-2 .

As described above, according to this embodiment, the SO
By adopting the I substrate and optimizing the n-type offset layer 7,
High breakdown voltage MO that can achieve high drain breakdown voltage without increasing the on-resistance even when used for high-side switching.
SFET is obtained.

FIG. 2 is an element cross-sectional view showing the element structure of the high breakdown voltage MOSFET according to the second embodiment of the present invention.
The high-voltage MOSFET of this embodiment differs from that of the previous embodiments in that the n-type offset layer 7a is a p ⁺ -type base layer 4b.
It extends to the bottom of the. Such an n-type offset layer 7a can be easily formed by implanting ions on the entire surface of the substrate. The high withstand voltage MOSFET configured as described above can also obtain the same effect as that of the above-described embodiment.

FIG. 3 is a device sectional view showing a device structure of a high breakdown voltage MOSFET according to a third embodiment of the present invention.
The high withstand voltage MOSFET of this embodiment is different from that of the first embodiment in the concentration profile of the n-type offset layer 7b. That is, the concentration peak of the n-type offset layer 7b is located deeper than the surface. Such an n-type offset layer 7b can be formed by increasing the acceleration energy and implanting ions. Since the concentration peak of the n-type offset layer 7b becomes deep, the n ⁺ drain layer 6a is also deeply formed.

According to the present embodiment, since the current flows in a region deeper than the surface, the influence of the surface resistance is eliminated, and the on-resistance can be further reduced while maintaining the breakdown voltage. FIG. 4 is a device sectional view showing the device structure of a high breakdown voltage MOSFET according to the fourth embodiment of the present invention.

The high withstand voltage MOSFET of this embodiment is different from that of the first embodiment in that the n-type offset concentration of the n-type offset layer 7c at the edge portions of the gate and field plate is different from that of the other portions. It is lower than that of 7. Such an n-type offset layer 7
Can be formed, for example, by applying a mask to the portion of the n-type offset layer 7c and performing ion implantation.

According to this embodiment, the n-type offset layer 7c
Function as a guard ring, the n-type impurity concentration of the offset layer 7 can be increased. Therefore, the total dose of the offset layer 7 can be increased, and the on-resistance can be further reduced while maintaining the breakdown voltage.

In place of the n-type offset layer 7c,
A low concentration p ⁻ type semiconductor layer may be used. Although the four embodiments have been described above, the present invention is not limited to the above embodiments.

For example, all the conductivity types of the source layer, the drain layer and the other semiconductor layers may be reverse conductivity types. The conductivity type of the active layer is p regardless of the conductivity types of other semiconductor layers.
Either type or n-type may be used. Further, the above embodiments may be combined. In addition, various modifications can be made without departing from the scope of the present invention.

[0031]

As described in detail above, according to the present invention, it is possible to obtain a high breakdown voltage MOSFET capable of improving insulation isolation and ON resistance while maintaining the breakdown voltage.

[Brief description of drawings]

FIG. 1 is a high breakdown voltage MOSF according to a first embodiment of the present invention.
Element sectional view showing the element structure of ET

FIG. 2 is a high breakdown voltage MOSF according to the first embodiment of the present invention.
Element sectional view showing the element structure of ET

FIG. 3 is a high breakdown voltage MOSF according to the first embodiment of the present invention.
Element sectional view showing the element structure of ET

FIG. 4 is a high breakdown voltage MOSF according to the first embodiment of the present invention.
Element sectional view showing the element structure of ET

FIG. 5 is a characteristic diagram showing the relationship between the dose amount and the breakdown voltage.

FIG. 6 is a characteristic diagram showing a relationship between diffusion depth and ON resistance.

FIG. 7 is a characteristic diagram showing the relationship between the dose amount and the breakdown voltage of the mushroom with the concentration of the p-type substrate as a parameter.

FIG. 8: High breakdown voltage MOSFET used in a conventional output stage
Element cross-sectional view showing the structure of

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Insulating layer 3 ... P ^- type active layer (high resistance semiconductor layer) 4a ... P ⁺ type base layer (first conductivity type base layer) 4b ... P type base layer (first conductivity type base layer) 5 ... N ⁺ type source layer (first second conductivity type semiconductor layer) 6, 6a ... N ⁺ type drain layer (second second conductivity type semiconductor layer) 7, 7a, 7b, 7c ... N type offset layer (Second conductivity type offset layer) 8 ... Source electrode 9 ... Drain electrode 10 ... Gate electrode 11 ... Gate oxide film

Claims (1)

[Claims] 1. A high resistance semiconductor layer on a substrate whose surface is an insulating layer, a first conductivity type base layer selectively formed on the surface of the high resistance semiconductor layer, and a first conductivity type base layer. A first second conductivity type semiconductor layer selectively formed on the surface; a second conductivity type offset layer selectively formed on the surface of the high resistance semiconductor layer and not reaching the insulating layer; A second second conductivity type semiconductor layer selectively formed on the surface of the conductivity type offset layer, and a region between the first second conductivity type semiconductor layer and the second second conductivity type semiconductor layer. A second conductive type offset layer having a diffusion depth of 1 to 2;
A high breakdown voltage semiconductor device, characterized in that the dose amount is 2 to 3 × 10 ¹² cm ⁻² in μm.