JP3114592B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a surface electric field relaxation type M
The present invention relates to a semiconductor device having an OS transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, N-channel LDMOS (Latera)
l Diffused MOS transistor (hereinafter simply LDMOS)
FIG. 8). This LDMOS
As shown in the figure, an N well 2 is formed in an N type substrate 1, a channel P well 3 is formed in the N well 2, and an N type diffusion layer 4 is formed in the channel P well 3. Further, an N-type diffusion layer 5 is formed in the N well 2. A gate electrode 7 is formed on the substrate surface via a gate oxide film 6.
Is formed, and a channel region 8 is formed in a surface region of the channel P well 3 immediately below the gate electrode 7.

The N-type diffusion layer 4 is used as a source region, the N-type diffusion layer 5 is used as a drain region, and the N well 2 below the LOCOS oxide film 9 is used as a drift region. In addition, 10, 1
1 is a source electrode and a drain electrode, 12 is a diffusion layer for taking the potential of the channel P well 3, and 13 is an interlayer insulating film. In such an LDMOS, if the concentration of the N-well 2 is increased in order to reduce the on-resistance and facilitate the flow of current, the depletion layer is less likely to expand in the drift region and a high breakdown voltage cannot be obtained. Conversely, if the concentration of the N-well 2 is reduced, a higher breakdown voltage can be achieved, but there is a problem that a current does not easily flow and the on-resistance increases.

In order to solve such a problem, Japanese Patent Publication No. 59-24550 and Japanese Patent Application Laid-Open No. Hei 5-267652 have been proposed. FIG. 9 shows a schematic configuration of this device. This is obtained by forming an N well 2 in a P-type substrate 14. In this case, if the N well 2 is formed by diffusion, the concentration on the surface of the N well 2 increases,
Since the current easily flows on the surface of the well 2 and the depletion layer easily spreads over the entire N well 2, the withstand voltage can be increased. Such an LDMOS is called a surface electric field relaxation type (RESURF) LDMOS.
The dopant concentration of the drift region of the N well 2 is set so as to satisfy the so-called RESURF condition as described in the above publication.

[0005]

The above-mentioned surface electric field relaxation type L
In the DMOS, the source electrode 10 and the P-type substrate 14 are electrically connected. Therefore, FIG.
As shown in FIG. 0, when the L load 15 such as a coil is connected to the drain electrode 11 to drive the L load 15, when the voltage applied to the gate electrode 7 is turned off, the back electromotive force of the L load 15 decreases. 11 is applied. This back electromotive voltage is
Often very high voltages can occur.

In this case, the above-described surface electric field relaxation type LDM
In the OS, since a current escape path for the back electromotive voltage is not taken into consideration, the PN junction between the channel P well 3 and the N well 2 breaks down when the back electromotive voltage is applied, and the P ⁺ diffusion layer When a current flows through the source electrode 10 through the source electrode 12, the potential of the channel P-well 3 rises above the potential of the N-type diffusion layer 4. N
A parasitic transistor having the well 2 as a collector operates, and a large current flows in a narrow area in the direction of the arrow. Therefore, a large current flows in this narrow region, so that the element tends to generate heat, and even if the back electromotive voltage is small, the element is destroyed in the channel forming portion. Therefore, the breakdown strength of the element is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to prevent element breakdown at a channel forming portion in a surface electric field relaxation type LDMOS even when a voltage such as a back electromotive voltage is applied to a drain. This is the purpose of 1. The above-described surface electric field relaxation type LDMOS is formed on a P-type substrate 14. Accordingly, a V-NPN transistor having better current characteristics than a PNP transistor (hereinafter simply referred to as NPNTr)
) And the surface electric field relaxation type LDMOS are formed on the same substrate, there is a problem that the N layer which forms the collector layer of the NPN Tr is formed deeply, so that both cannot be formed on the same substrate. is there. In this case, if the LDMOS having the structure shown in FIG.
r can be formed on the same substrate, but it is not possible to achieve both high breakdown voltage and on-resistance in the LDMOS as described above.

The present invention relates to a surface electric field relaxation type LDMOS and NMOS.
A second object is to form a PNTr on the same substrate.

[0009]

In order to achieve the first object, according to the first aspect of the present invention, a first conductive type semiconductor layer (1) is provided in a first conductive type well (2). 16)
Are formed and the first well (16) is formed in the first well (16).
A second well (2) of the first conductivity type is formed shallower than the well (16), and a source region (4), a channel region (8) and a drain region (5) are formed in the second well (2). And a gate electrode (7) is formed on the channel region (8) to form a surface electric field relaxation type MOS transistor using the second well (2) as a drift region. And said
The source region (4) and the semiconductor layer (1) are set at the same potential.
When a voltage that renders the MOS transistor inactive is applied to the gate electrode (7) and a high voltage equal to or higher than a predetermined voltage is applied to the drain region (5), the second well (2) ) To said first well (16)
And a current path is formed via the semiconductor layer (1).

[0010] In the invention described in claim 2, in the semiconductor device according to claim 1, wherein the second well (2), said first well (16) and said semiconductor layer (1) the parasitic bipolar transistor between ( 18) is formed, and the current path is formed by the parasitic bipolar transistor (18).

According to a third aspect of the present invention, in the semiconductor device according to the first aspect , the current path is formed by punching through between the second well (2) and the semiconductor layer (1). It is characterized by. According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the channel region (8) includes the second wafer.
Channel well of the second conductivity type formed in the channel (2)
(3) formed in a surface region immediately below the gate electrode (7);
And a base (17) reaching the first well including the source region (4) is formed. According to the invention described in claim 5, the first
A first well of a second conductivity type is formed in a semiconductor layer (1) of a conductivity type.
(16) is formed and the first well (16) is formed.
The second well of the first conductivity type is shallower than the first well (16).
A well (2) is formed in the second well (2).
Source region (4), channel region (8) and drain
Channel region (5) is formed, and the channel region is further formed.
(8) A gate electrode (7) is formed on the second wafer.
Surface electric field relaxation type MO with well (2) as drift region
A semiconductor device comprising an S transistor,
The channel region (8) is formed in the second well (2).
The gate of the formed second conductivity type channel well (3)
Is formed in the surface area directly below the gate electrode (7).
And the first well (1) including the source region (4).
The base (17) of the second conductivity type is shaped so as to reach 6).
And the MOS transistor is brought into a non-operation state.
Voltage applied to the gate electrode (7) and the drain
When a high voltage higher than a predetermined voltage is applied to the application region (5)
The second well (2) to the first well (16)
And a current flows through the semiconductor layer (1).
And the base (17) from the first well (16).
Characterized by the fact that the current flows through
I have.

According to a sixth aspect of the present invention, the semiconductor device has a source region (4), a channel region (8), and a drain region (5), and a gate electrode (7) is formed on the channel region. A semiconductor device having a MOS transistor in which a drift region is formed between the channel region and the drain region (5);
A first well (16) of the second conductivity type is formed in the semiconductor layer (1) of the conductivity type, and the first well (16) is formed.
A second well (2) of a first conductivity type shallower than the first well (16) is formed therein, and at least the drift region and the drain region (5) are formed in the second well (2). And the source region (4)
And the semiconductor layer (1) is set to the same potential.

According to the invention described in claim 7, the first conductivity type is
A first well of the second conductivity type is formed in the first semiconductor layer (21a).
(16) is formed and the first well (16) is formed.
The second well of the first conductivity type is shallower than the first well (16).
A well (2) is formed in the second well (2).
Source region (4), channel region (8) and drain
Channel region (5) is formed, and the channel region is further formed.
(8) A gate electrode (7) is formed on the second wafer.
Surface electric field relaxation type MO with well (2) as drift region
An S transistor is formed, and the MOS transistor
A semiconductor device for driving an L load, wherein the first half
The first semiconductor layer (21a) is located below the conductor layer (21a).
The second semiconductor layer (21b) of the first conductivity type is disposed at a higher concentration.
And the second semiconductor layer (21b) from the substrate surface.
At a higher concentration than the first semiconductor layer (21a).
Deep layer of the first conductivity type (26) are formed, prior to
The voltage for deactivating the MOS transistor is applied to the gate.
The L load generates a back electromotive force when applied to the gate electrode (7).
The first well (16), the first semiconductor
Body layer (21a), said second semiconductor layer (21b) and
A current path through the deep layer (26) is formed.
It is characterized by. In order to achieve the second object, in the invention according to claim 8 , the N-type first semiconductor layer (21a) is separated into first and second element regions, A semiconductor device in which a surface electric field relaxation type MOS transistor (LDMOS) is formed in an element region, and a bipolar transistor (NPNTr) is formed in the second element region using the first semiconductor layer (21a) as a collector layer. In the first element region, a P-type first well (16) is formed in the first semiconductor layer (21a).
Are formed and the first well (16) is formed in the first well (16).
An N-type second well (2) shallower than the well (16) is formed, and a source region (4), a channel region (8) and a drain region (5) are formed in the second well (2).
There is formed, further wherein the gate electrode on the channel region (8) (7) is formed, being the said surface field relaxation type MOS transistor in which the second well (2) and a drift region is formed, and the Under the first semiconductor layer (21a)
An N-type second semiconductor layer (21b) is disposed on
N-type data from the plate surface to the second semiconductor layer (21b)
And a deep layer (26) is formed.
(26) and the potential due to the second semiconductor layer (21b)
By setting, the source region (4) and the first semiconductor layer
(21a) is characterized by having the same potential .

[0014]

According to the ninth aspect of the present invention, the N-type
An N-type first semiconductor layer (21) is formed on the second semiconductor layer (21b).
a) is formed and the first semiconductor layer (21a) is
2. A semiconductor substrate in which the semiconductor layer (21b) has a high concentration
Forming first and second element regions separated from each other, forming a surface electric field relaxation type MOS transistor (LDMOS) in the first element region, and forming a bipolar transistor (NPNTr) in the second element region. to form a method for manufacturing a semiconductor device, in the first element region, group
From the plate surface to the second semiconductor layer (21b),
An N-type deice having a higher concentration than the first semiconductor layer (21a).
And forming a semiconductor layer (21a) on the semiconductor layer (21a).
First well of mold (16) and second well of N mold (2)
Is implanted and simultaneously diffused to form the first well (16), and the second well (16) is shallower in the first well (16) than the first well (16). 2), and then the second
Forming a source region (4), a channel region (8) and a drain region (5) in the well (2), and forming a gate electrode (7) on the channel region (8); Forming the MOS transistor (LDMOS) having (2) as a drift region;
In the second element region, the first semiconductor layer (2
1a) as a collector layer and a bipolar transistor (N
(PNTr).

The reference numerals in parentheses of the above means indicate the correspondence with the concrete means described in the embodiments described later. According to the first to sixth aspects of the present invention, the semiconductor device has a double well structure in which a first well of the second conductivity type and a second well of the first conductivity type are formed in the semiconductor layer of the first conductivity type. The drift region and the drain region of the MOS transistor are formed in the second well.

Here, when a back electromotive voltage is applied to the drain region, a current path is formed in a large area from the second well through the first well and the semiconductor layer. Therefore, even if such a back electromotive voltage is applied, the destruction of the element in the channel forming portion can be prevented by securing the current path. Claim 7,
According to the invention described in Item 8, the P-type first semiconductor layer is formed on the N-type semiconductor layer.
Since the surface electric field relaxation type MOS transistor has a double well structure in which a well and an N-type second well are formed, NPNT having an N-type semiconductor layer as a collector layer
r can be formed on the same substrate.

According to a ninth aspect of the present invention, there is provided a manufacturing method of forming such a MOS transistor and a NPN Tr on the surface electric field reduction side on the same substrate, wherein the first and second wells are simultaneously diffused. Since it is formed, the first and second wells can be formed with one mask.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an embodiment shown in the drawings. FIG. 1 shows a sectional configuration of a surface electric field relaxation type LDMOS showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, a P well 1 is provided in an N-type substrate 1.
6 and a double well structure in which an N well 2 is formed. Further, the source electrode 10 and the N-type substrate 1 are configured to have the same potential. The dopant concentration of the drift region of the N well 2 is set so as to satisfy the so-called RESURF condition. Further, the same reference numerals as those shown in FIGS. 8 and 9 indicate the same or equivalent configurations.

The surface electric field relaxation type LDMOS shown in FIG.
This has the essential effects of high withstand voltage and low on-resistance, and can prevent destruction of a channel forming portion when a back electromotive voltage is applied when an L load is connected to the drain electrode 11. This will be described with reference to FIG. When the L load 15 is connected to the drain electrode 11, when the voltage applied to the gate electrode 7 is reduced to switch off, a back electromotive voltage is applied to the drain electrode 11. Here, the parasitic diode VZ1 formed between the N well 2 and the P well 16, the N well 2 and the channel P
Although there is a parasitic diode VZ2 formed between the N-well 2 and the well 3, the parasitic diode VZ1 breaks down first due to a rise in the potential in the N-well 2.

That is, when the back electromotive voltage as described above is applied, the potential distribution in the N well 2 and the P well 16 becomes as shown in FIG. 3, and the potential distribution in the lateral direction from the drain region 5 to the source region 4 is obtained. The potential gradient in the vertical direction toward the substrate is steeper than that in the vertical direction.
Breaks down first. In this case, the voltage in P-well 16 increases due to resistance R2 in P-well 16, and parasitic diode VZ between P-well 16 and N-type substrate 1 is increased.
3 is turned on, the parasitic bipolar transistor 18 formed by the N well 2, the P well 16 and the N-type substrate 1 is turned on, and current flows in the direction of the substrate having a large area, so that the current can be dispersed. Heat generation due to flowing can be suppressed. Thus, destruction of the element in a channel formation portion having a low withstand voltage can be prevented, and the withstand voltage of the element can be improved.

The P well 16 including the source region 4
Is provided, and a current I flows from the P well 16 to the source side. This makes it more difficult for a current to flow through the channel forming portion.
If a sufficient current can flow through the current path toward the substrate, the base 17 may be omitted. In the above configuration, the parasitic bipolar transistor 18 allows a current to flow in the direction of the substrate. However, when the P-well 16 is formed sufficiently thin in the direction of the substrate, the parasitic bipolar operation is not performed. A current can flow in the direction of the substrate by punch-through.

Next, the above-mentioned surface electric field relaxation type LDMOS
Is formed on the same substrate together with CMOS and NPN Tr in FIG. The one shown in FIG.
It has an I (Silicon On Insulator) structure. Ie, N on N ⁺ substrate 21b ^- layer (N-type substrate 1 of FIG. 1
A trench groove 23 is formed on a bonded substrate obtained by bonding an N-type substrate 21 and a P-type substrate 20 on which an a) is formed via an insulating film 22 such as SiO ₂ , and oxidation is performed in the groove. A film is formed, a plurality of device regions separated from each other are formed, and LDMOS,
CMOS and NPN Tr are formed.

The method for manufacturing the structure shown in FIG.
This will be described with reference to the process chart shown in FIG. First, the above-mentioned bonded substrate is prepared, a trench groove 23 is formed therein, an oxide film is formed in the groove, and polycrystalline silicon 24 is buried. In this state, the N-type substrate 2
An oxide film 25 is formed on one surface. And FIG.
As shown in FIG. 1A, a deep N ⁺ layer 26 is formed in an LDMOS formation region, and thereafter, ion implantation for forming a P well 16 and an N well 2 is performed, and these are simultaneously diffused. In this case, boron (B) is used for the P well and arsenic (As) is used for the N well, and the P well is formed deep and the N well is formed shallow due to the difference in diffusion coefficient between the two. In this step, boron and arsenic are simultaneously diffused, so that only one mask is required.

[0025] In the above ion implantation, the boron dose is 3 × 10 ¹² ~1 × 10 ¹³ atoms / cm ^2, the dose of arsenic is 3 × 10 ¹² ~1 × 10 ¹³ atoms / c
m ² . When diffusing implanted ions,
Drive-in is performed at 1200 ° C. for about 600 minutes. Note that as a condition of the RESURF structure, the impurity concentration in the depth direction from the surface of the N-well layer 2 to the PN junction with the P-well layer 16 needs to satisfy the relationship shown in Expression 1.

[0026]

(Equation 1)

Here, N _d (x) represents an impurity concentration per unit volume, x represents a depth, and x _j represents a PN junction depth between the N well layer 2 and the P well layer 16. . next,
As shown in FIG. 5B, ion implantation for forming a P-well 27 and an N-well 28 is performed in a CMOS formation region and diffused. Thereafter, as shown in FIG.
Ions are implanted into the formation region of the PNTr, and drive-in is performed to form the base 28. At this time, if necessary, LD
The base 17 is similarly formed in the MOS region.

Next, as shown in FIG.
Perform S oxidation. By this step, the LOCOS oxide film 9 is formed in the LDMOS formation region. After this, LDMO
As shown in FIG. 6B , the gate oxide film 6 of S is formed .
As described above, the surface of the substrate is oxidized. Then, Poly Si is formed on the surface of the substrate, and after phosphorus is doped, patterning is performed by photoetching, and the pattern is formed as shown in FIG.
Thus, the gate electrode 7 of the LDMOS is formed.

Thereafter, L is formed by a normal element forming process.
DMOS, CMOS, NPNTr are sequentially formed,
Finally, the structure shown in FIG. 4 is formed. Note that LDMOS
In the formation region, channel P well 8 and source region 4 are diffused and formed in N well 2 using the gate as a mask. According to the above manufacturing method, the length of the LOCOS oxide film 9 is set to 2 μm, and the outermost surface concentration of the P well 16 is set to 8 × 1.
0 ^{15 to} 2 × 10 ¹⁶ / cm ³ , a surface with an outermost surface concentration of the N well 2 of 3 × 10 ^{16 to} 6 × 10 ¹⁶ / cm ³ and a depth of the N well 2 of about 1.5 to 2.0 μm Electric field relaxation type LDMO
S was formed. In this case, the withstand voltage between the source and the drain could be about 70 to 80 V, and the withstand voltage between the N well 2 and the P well 16 could be about 65 V.

Although the device shown in FIG. 4 has an SOI structure and uses the insulating film 22 and the trench 23 to perform device isolation, as shown in FIG. 7, the device isolation buried layer 30 and the device isolation The element isolation may be performed by the isolation P layer 31. Further, the LDMOS shown in FIG. 4 or FIG. 7, a path to flow a breakdown current in the substrate direction when the counter electromotive force generated, as shown in FIG. 4, N ⁺ diffusion layer in contact with the insulating film 22 27, When a current flows from the bottom electrode B formed on the substrate surface to the ground via the deep N ⁺ layer 26 to the ground, or as shown in FIG. 7, the embedded N ⁺ 30 and the deep N ⁺ layer 32 In the case where the current flows from the bottom electrode B to the ground, the following effects are obtained in addition to the effects described above.

That is, also in the conventional surface electric field relaxation type LDMOS shown in FIG. 9, the drain electrode is adjusted by adjusting the distance of the drift region from the drain region 5 to the channel P well 3 and the concentration and depth of the N well 2. Eleven,
It is considered that when a back electromotive force is applied so that a reverse bias is applied between the drain region 5 and the channel P well region 3, a current can flow in the substrate direction as in the above embodiment.

However, the LDMO shown in FIGS.
When a breakdown current is to flow from the substrate surface to the ground as in S, the current path includes a current path to the bottom electrode as shown in FIG. 4 and FIG. A current path is formed in the short channel P well 3. As a result, as described in the description of the related art, a large current caused by the parasitic transistor flows through the channel region, so that the element is thermally damaged on the substrate surface even if the back electromotive force is small. .

Therefore, when a configuration is adopted in which a breakdown current flows from the substrate surface to the ground as shown in FIG. 4 or FIG. 7, the N-type layer 1 is provided below the P well 16 and
If a parasitic transistor is generated in the direction of the substrate and a current flows through an N layer having a conductivity type different from that of the channel P well, a breakdown current does not flow through the channel P well 3. Can be prevented from thermal destruction.

As another example of obtaining an electrode from the substrate surface, a similar effect can be obtained when a bump electrode used for a flip chip or the like is used.

[Brief description of the drawings]

FIG. 1 shows a surface electric field relaxation type LDM showing one embodiment of the present invention.
FIG. 3 is a sectional view of an OS.

FIG. 2 is an explanatory diagram for explaining an operation when a back electromotive voltage is applied in the configuration shown in FIG. 1;

FIG. 3 is an explanatory diagram for disconnecting a potential state when a back electromotive voltage is applied in the configuration shown in FIG. 1;

FIG. 4 shows the configuration shown in FIG.
It is sectional drawing of what was comprised on the same board | substrate with r.

FIG. 5 is a process chart showing a manufacturing process of the one shown in FIG. 4;

FIG. 6 is a process chart showing a manufacturing process following the manufacturing process shown in FIG. 5;

FIG. 7 is a sectional view showing another embodiment shown in FIG. 4;

FIG. 8 is a cross-sectional view showing a configuration of a conventional LDMOS.

FIG. 9 is a sectional view showing a configuration of a conventional surface electric field relaxation type LDMOS.

FIG. 10 is an explanatory diagram for explaining a problem when a back electromotive voltage is applied in a conventional configuration.

[Explanation of symbols]

1 ... N-type substrate, 2 ... N well, 3 ... Channel P well,
4 source region, 5 drain region, 6 gate oxide film, 7 gate electrode, 8 channel region, 9 LOCO
S oxide film, 10: source electrode, 11: drain electrode, 1
3 ... interlayer insulating film, 16 ... P well.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Maeda 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Inside Denso Corporation (72) Inventor Makio Iida 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Japan Denso Stock In-company (56) References JP-A-59-119864 (JP, A) JP-A-58-16572 (JP, A) European Patent Application 677876 (EP, A1) (58) Fields investigated (Int. . ^7, DB name) H01L 21/8249 H01L 21/822 H01L 27/06 H01L 29/78

Claims (9)

(57) [Claims] 1. A first well of a second conductivity type is formed in a semiconductor layer of a first conductivity type, and a second well of a first conductivity type is formed in the first well and shallower than the first well. A source field, a channel region, and a drain region are formed in the second well; and a gate electrode is formed on the channel region. Wherein the source region and the semiconductor layer are set to the same potential.
Cage, when the MOS transistor is a voltage to the non-operating state is applied to the gate electrode a high voltage higher than a predetermined voltage to the drain region is applied, via the first well and the semiconductor layer from the second well Wherein a current path is formed. Wherein said second well, the parasitic bipolar transistor is formed in the first well and the semiconductor layers, a semiconductor according to claim 1, characterized in that the current path by the parasitic bipolar transistor is formed apparatus. 3. The semiconductor device according to claim 1 , wherein said current path is formed by punching through said second well and said semiconductor layer. 4. The semiconductor device according to claim 1 , wherein the channel region is in the second well.
The gate of the channel well of the second conductivity type formed at
The base of the second conductivity type is formed in a surface region immediately below an electrode, and further includes a second conductivity type including the source region and reaching the first well.
3. The semiconductor device according to any one of 3 . 5. A semiconductor device according to claim 1 , wherein said first conductive type semiconductor layer has a second conductive type.
A first well is formed and a first well is formed in the first well.
A second well of the first conductivity type is formed shallower than one well.
A source region, a channel region, and a drain in the second well.
A rain region is formed, and a gate region is formed on the channel region.
A second electrode formed in the drift region,
MOS transistor of surface electric field relaxation type
A semiconductor equipment comprising Te, the channel region, the formed within the second well
Surface of the two-conductivity type channel well immediately below the gate electrode
Region, and further including the source region
The base of the second conductivity type is moved so as to reach the first well.
Is formed, the voltage of the MOS transistor inoperative state the
A predetermined voltage applied to the gate electrode and applied to the drain region
When a high voltage is applied to the second well,
When a current flows through one well and the semiconductor layer,
In addition, a current flows from the first well through the base.
A semiconductor device characterized in that it is adapted to be used. 6. A MOS transistor having a source region, a channel region, and a drain region, a gate electrode formed on the channel region, and a drift region formed between the channel region and the drain region. A first well of a second conductivity type is formed in a semiconductor layer of a first conductivity type, and a second well of a first conductivity type that is shallower than the first well is formed in the first well. The semiconductor device, wherein the drift region and the drain region are formed at least in the second well, and the source region and the semiconductor layer are set to the same potential. 7. The method according to claim 1, wherein the first conductive type first semiconductor layer has a second conductive type.
Forming a first well of the mold and in the first well;
Forming a second well of the first conductivity type shallower than the first well
And a source region, a channel region and a drain in the second well.
A rain region is formed, and a gate region is formed on the channel region.
A second electrode formed in the drift region,
Surface electric field relaxation type MOS transistor
And a semiconductor driving an L load by the MOS transistor.
A device having a higher concentration below the first semiconductor layer than the first semiconductor layer;
A second semiconductor layer of the first conductivity type is disposed, and further, a substrate surface
The first half conductor layer to reach the second semiconductor layer from
A deep layer of the first conductivity type is formed at a higher concentration, and the voltage for disabling the MOS transistor is applied to the MOS transistor.
The L load applied to the gate electrode generates a back electromotive voltage.
The first well, the first semiconductor layer, and the
2 The current path through the semiconductor layer and the deep layer is shaped
A semiconductor device characterized by being formed. 8. An N-type first semiconductor layer is separated into first and second element regions, and a surface electric field relaxation type MOS transistor is formed in the first element region. A bipolar transistor, wherein the first semiconductor layer is a collector layer and a bipolar transistor is formed.
A first well is formed, and a second well of N type is formed in the first well and shallower than the first well. A source region, a channel region and a drain region are formed in the second well. is, the more the gate electrode on the channel region is formed, the are the surface electric field relaxation type MOS transistor of the second well and a drift region is formed, the N type under the first semiconductor layer Two semiconductor layers are arranged
And an N-type from the substrate surface to the second semiconductor layer.
A deep layer is formed, this deep layer and the front
The source region and the source region are set by the potential setting by the second semiconductor layer.
A semiconductor device, wherein the first semiconductor layers have the same potential . 9. An N-type first semiconductor on an N-type second semiconductor layer.
A body layer is formed and the second semiconductor layer is replaced by the first semiconductor layer.
On a semiconductor substrate with a high concentration of
(1) forming a second element region; forming a surface electric field relaxation type MOS transistor in the first element region;
A method of manufacturing a semiconductor device in which a bipolar transistor is formed in an element region of the semiconductor device, wherein the first element region includes a first semiconductor region extending from a substrate surface to the second semiconductor layer.
Forming an N-type deep layer with a higher concentration than the semiconductor layer, and performing ion implantation for forming a P-type first well and an N-type second well in the first semiconductor layer;
Simultaneous diffusion forms the first well and forms the second well shallower than the first well in the first well. Thereafter, a source region, a channel region and a drain are formed in the second well. Forming a gate electrode on the channel region to form the MOS transistor having the second well as a drift region; and forming the first semiconductor layer in the second element region. And forming a bipolar transistor using the collector layer as a collector layer.