JPH0775124B2 - Thin film deposition method - Google Patents
Thin film deposition methodInfo
- Publication number
- JPH0775124B2 JPH0775124B2 JP2015734A JP1573490A JPH0775124B2 JP H0775124 B2 JPH0775124 B2 JP H0775124B2 JP 2015734 A JP2015734 A JP 2015734A JP 1573490 A JP1573490 A JP 1573490A JP H0775124 B2 JPH0775124 B2 JP H0775124B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- internal stress
- substrate
- deposition method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
- Physical Vapour Deposition (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路、特に超伝導集積回路で用いられる
薄膜の堆積方法に関するものである。Description: FIELD OF THE INVENTION The present invention relates to a method for depositing thin films used in integrated circuits, especially superconducting integrated circuits.
〔従来の技術〕 基板１上に堆積された薄膜の内部応力としては、第３図
（ａ）に示すように、圧縮応力を持つ薄膜２の場合と、
第３図（ｂ）に示すように、引っ張り応力を持つ薄膜３
の場合がある。基板に堆積された状態では、圧縮応力の
場合は、上に凸となり、引っ張り応力の場合は、下に凸
となる。従来、内部応力の強い薄膜については、集積回
路の作製工程の途中で、特に超音波洗浄やスクラバーな
どの工程中に剥離する問題が、知られており、その対策
としては、薄膜の堆積工程に関する諸条件を検討して、
内部応力そのものを減らすような方法が行なわれてい
た。[Prior Art] As for the internal stress of the thin film deposited on the substrate 1, as shown in FIG.
As shown in FIG. 3 (b), the thin film 3 having tensile stress
In some cases. In the state of being deposited on the substrate, it becomes convex upward in the case of compressive stress and convex downward in the case of tensile stress. Conventionally, there has been known a problem that a thin film having a strong internal stress is peeled off during the process of manufacturing an integrated circuit, particularly during a process such as ultrasonic cleaning or a scrubber. Consider the various conditions,
Methods were used to reduce the internal stress itself.
しかしながら、一般に、高い超伝導臨界温度を示す超伝
導薄膜は、内部応力が強い。従って、内部応力の強い薄
膜がどうしても必要な超伝導集積回路の場合には、上述
した従来技術では対応できなかった。また、内部応力の
強い薄膜を使用した場合、基板が湾曲するため、集積回
路の作製工程におけるリソグラフィ工程のように平坦性
を要求する工程について、焦点が狂うといった問題があ
った。However, in general, a superconducting thin film exhibiting a high superconducting critical temperature has high internal stress. Therefore, in the case of a superconducting integrated circuit in which a thin film having a strong internal stress is absolutely necessary, the above-mentioned conventional technique cannot handle it. In addition, when a thin film having a strong internal stress is used, the substrate is curved, and there is a problem that the focus is lost in a process requiring flatness such as a lithography process in a manufacturing process of an integrated circuit.
本発明はこのような従来の問題を解決し、内部応力が緩
和される薄膜堆積法を提供することを目的とする。It is an object of the present invention to solve such conventional problems and provide a thin film deposition method in which internal stress is relaxed.
本発明は、基板に薄膜を堆積する方法において、基板の
上に第２の薄膜を設け、前記第２の薄膜の上に、前記第
２の薄膜の有する内部応力とは反対の方向の内部応力を
有する第１の薄膜を設けることを特徴とする。The present invention relates to a method of depositing a thin film on a substrate, wherein a second thin film is provided on the substrate, and internal stress in a direction opposite to the internal stress of the second thin film is provided on the second thin film. Is provided.
本発明では、第１図に示すように、集積回路中で内部応
力の強い第１の薄膜４を使用する際に、その薄膜４の内
部応力はそのままにして、それとは反対の内部応力を持
つ第２の薄膜５を直下に配置して、内部応力の影響を緩
和するものである。According to the present invention, as shown in FIG. 1, when the first thin film 4 having a strong internal stress is used in an integrated circuit, the internal stress of the thin film 4 is left as it is and has an internal stress opposite to that. The second thin film 5 is arranged immediately below to alleviate the effect of internal stress.
内部応力の強い薄膜が、集積回路の作製工程の途中で、
剥離する原因は、基本的には、薄膜と基板の密着が悪い
ことにより、内部応力は、それを加速する要因と考えら
れる。第１図のような構造を考えた場合、第１の薄膜４
と第２の薄膜５は、同質の材料（例えば、金属膜には金
属膜、絶縁膜には絶縁膜）であれば、それらの間での密
着は良く、従って、それらの薄膜の間で、内部応力を相
殺するため、基板１と薄膜５の間には、剥離を加速する
要因がなくなる。このように、比較的薄膜と基板の密着
が悪い場合でも、剥離が生じにくくなる。A thin film with a strong internal stress, during the manufacturing process of the integrated circuit,
It is considered that the cause of the peeling is basically that the adhesion between the thin film and the substrate is poor, and the internal stress accelerates it. Considering the structure shown in FIG. 1, the first thin film 4
If the second thin film 5 and the second thin film 5 are of the same material (for example, a metal film for a metal film and an insulating film for an insulating film), the adhesion between them is good, so that between these thin films, Since the internal stress is canceled out, there is no factor that accelerates peeling between the substrate 1 and the thin film 5. Thus, even if the adhesion between the thin film and the substrate is relatively poor, peeling is less likely to occur.
基板１として、Siウエハー、第１の膜４として、NbN
膜、第２の膜５として、Nb膜を用いた場合について、本
発明の実施例を示す。この場合、NbN膜は、圧縮応力を
持ち、Nb膜は、引っ張り応力を持つ。直径5cm,厚さ350
μｍのSi基板上に、スパッタ装置を用いて、アルゴンガ
ス圧力8mTorr,高周波電力450Wの条件で15cm径のNbター
ゲットをスパッタして厚さ150nmのNb膜を堆積し、続い
てアルゴンガスと窒素ガスの混合ガス圧力8.5mTorr、高
周波電力400Wの条件で15cmのNbターゲットをスパッタし
て厚さ100nmのNbN膜を堆積した。一方、比較のため、直
径5cm、厚さ350μｍのSi基板上に同じ条件で厚さ100nm
のNbN膜をスパッタ堆積した。このようにして堆積した
２種類の薄膜の応力を測定した。The substrate 1 is a Si wafer, and the first film 4 is NbN.
An example of the present invention will be described for the case where an Nb film is used as the film and the second film 5. In this case, the NbN film has a compressive stress and the Nb film has a tensile stress. Diameter 5 cm, thickness 350
A 150 cm thick Nb film was deposited by sputtering a 15 cm diameter Nb target on a μm Si substrate using an argon gas pressure of 8 mTorr and a high frequency power of 450 W, followed by argon gas and nitrogen gas. A Nb target of 15 cm was sputtered under the conditions of a mixed gas pressure of 8.5 mTorr and a high frequency power of 400 W to deposit a 100 nm thick NbN film. On the other hand, for comparison, on a Si substrate with a diameter of 5 cm and a thickness of 350 μm, the thickness is 100 nm under the same conditions.
Of NbN film was sputter deposited. The stress of the two kinds of thin films thus deposited was measured.
表面荒さ計（Tencor社製Alpha-Step）を用いて、試料の
表面を特定の（2mm）範囲で触針で走査することによっ
て、その断面形状を測定した結果を第２図に示す。第２
図（ａ）は150nm厚Nb膜（下層）と100nm厚NbN膜（上
層）の場合の測定結果である。2mmスキャンしてもほと
んど高低がなく、内部応力が緩和されていることを示し
ている。一方、第２図（ｂ）はNbN膜100nmのみの場合
で、2mmスキャンする間に上に凸に10nm高さが変化して
いる。これは内部応力が圧縮応力であることを意味して
いる。このように、本発明方法によって、二つの膜の内
部応力は相殺され、かつ表面の平坦な膜を得ることがで
きる。FIG. 2 shows the result of measuring the cross-sectional shape by scanning the surface of the sample with a stylus in a specific (2 mm) range using a surface roughness meter (Alpha-Step manufactured by Tencor). Second
Figure (a) shows the measurement results for the 150 nm thick Nb film (lower layer) and the 100 nm thick NbN film (upper layer). Even with a 2 mm scan, there was almost no difference in height, indicating that the internal stress was relaxed. On the other hand, FIG. 2B shows the case where only the NbN film has a thickness of 100 nm, and the height changes 10 nm in a convex shape during 2 mm scanning. This means that the internal stress is compressive stress. As described above, according to the method of the present invention, the internal stresses of the two films are canceled out and a film having a flat surface can be obtained.
本発明の方法を用いれば、従来、内部応力が強く利用が
難しいような薄膜の場合については、容易に、剥離の問
題を解決できるため、集積回路へのその利用が可能とな
る。また、本発明によれば、基板の湾曲が減少するの
で、集積回路の作製工程において、特にリソグラフィ工
程のように平坦性を要求する工程について、有利にな
る。By using the method of the present invention, in the case of a thin film which is conventionally difficult to use due to strong internal stress, the problem of delamination can be easily solved, and therefore it can be used for an integrated circuit. Further, according to the present invention, the curvature of the substrate is reduced, which is advantageous in a manufacturing process of an integrated circuit, particularly in a process such as a lithography process which requires flatness.
第１図は本発明方法による堆積膜の模式的断面図、 第２は堆積膜の反りを示す図、 第３図は従来法による堆積膜の模式的断面図である。 １……基板、 2,3……薄膜、 ４……第１の薄膜、 ５……第１の薄膜と内部応力が反対の第２の薄膜。 FIG. 1 is a schematic sectional view of a deposited film formed by the method of the present invention, FIG. 2 is a diagram showing warpage of the deposited film, and FIG. 3 is a schematic sectional view of a deposited film formed by a conventional method. 1 ... Substrate, 2,3 ... Thin film, 4 ... First thin film, 5 ... Second thin film whose internal stress is opposite to that of the first thin film.
フロントページの続き (56)参考文献 特開 昭50−68684（ＪＰ，Ａ) 特開 昭60−91506（ＪＰ，Ａ) 特開 昭63−279521（ＪＰ，Ａ) 特開 平１−59887（ＪＰ，Ａ) 特開 平１−120715（ＪＰ，Ａ) 特開 平１−298089（ＪＰ，Ａ) 特開 平２−44781（ＪＰ，Ａ) 特開 平２−217462（ＪＰ，Ａ) 特開 平３−138817（ＪＰ，Ａ) 特開 平３−150147（ＪＰ，Ａ) 特公 昭45−19536（ＪＰ，Ｂ１)Continuation of front page (56) Reference JP-A-50-68684 (JP, A) JP-A-60-91506 (JP, A) JP-A-63-279521 (JP, A) JP-A-1-59887 (JP , A) JP-A 1-120715 (JP, A) JP-A 1-298089 (JP, A) JP-A 2-44781 (JP, A) JP-A 2-217462 (JP, A) JP-A 3-138817 (JP, A) JP-A-3-150147 (JP, A) JP-B-45-19536 (JP, B1)
Claims (2)
（１）の上に第２の薄膜（５）を設け、前記第２の薄膜
の上に、前記第２の薄膜の有する内部応力とは反対の方
向の内部応力を有する第１の薄膜（４）を設けることを
特徴とする薄膜の堆積方法。1. A method for depositing a thin film on a substrate, wherein a second thin film (5) is provided on the substrate (1), and an internal stress possessed by the second thin film is provided on the second thin film. Is provided with a first thin film (4) having an internal stress in the opposite direction.
膜（４）がNbN薄膜であり、第２の薄膜（５）がNb薄膜
であることを特徴とする請求項第１項記載の薄膜の堆積
方法。2. The substrate (1) is a Si wafer, the first thin film (4) is a NbN thin film, and the second thin film (5) is a Nb thin film. A method for depositing a thin film as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015734A JPH0775124B2 (en) | 1990-01-25 | 1990-01-25 | Thin film deposition method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015734A JPH0775124B2 (en) | 1990-01-25 | 1990-01-25 | Thin film deposition method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03219506A JPH03219506A (en) | 1991-09-26 |
| JPH0775124B2 true JPH0775124B2 (en) | 1995-08-09 |
Family
ID=11896997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015734A Expired - Lifetime JPH0775124B2 (en) | 1990-01-25 | 1990-01-25 | Thin film deposition method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0775124B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2652797A (en) | 1997-05-13 | 1998-12-08 | Mitsubishi Denki Kabushiki Kaisha | Dielectric thin film element and method for manufacturing the same |
| JP4732162B2 (en) * | 2005-12-27 | 2011-07-27 | 株式会社フジクラ | Oxide superconducting conductor and manufacturing method thereof |
| JP2009253275A (en) * | 2008-04-03 | 2009-10-29 | Xi Max Co Ltd | Original plate of ceramic printed circuit board, and method of manufacturing original plate |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745931A (en) * | 1980-09-04 | 1982-03-16 | Fujitsu Ltd | Semiconductor device with multilayer passivation film and manufacture thereof |
| JPS60126839A (en) * | 1983-12-13 | 1985-07-06 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP2615751B2 (en) * | 1988-02-04 | 1997-06-04 | ミノルタ株式会社 | Electrophotographic photoreceptor |
-
1990
- 1990-01-25 JP JP2015734A patent/JPH0775124B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03219506A (en) | 1991-09-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |