JPH0770717B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more specifically, to a high breakdown voltage field effect transistor structure, in which irreversible breakdown occurs when a bias voltage is applied to the drain. The present invention relates to an improved structure for preventing.

[Conventional technology]

As a high breakdown voltage field effect transistor structure of this type according to a conventional example, a schematic structure of a semiconductor device disclosed in, for example, JP-A-60-83348 (Japanese Patent Application No. 58-190777) is shown in FIG. Shown in.

That is, in the field effect transistor configuration according to the conventional example of FIG. 3, reference numeral 1 is a P-type silicon substrate (or,
P-type well) and 2, 2a are thick field oxide films for element isolation formed on the main surface of the P-type silicon substrate 1.

Further, 3 is a P ⁺ -type isolation region for a channel stopper provided directly under the field oxide film 2, and 4 is an N ⁺ formed on the main surface of the P-type silicon substrate 1.
A type source region, 5 is a thin gate oxide film formed on the same main surface, 6 is a gate electrode formed thereon and extending on the thick oxide film 2a to form a gate region, and 7 is Reference numeral 8 denotes an N + -type drain region formed so as to face the N ⁺ -type source region 4 with a gate region sandwiched between the gate region and the N ⁺ -type drain region 7. The thick oxide film 2a is formed between the gate region and the N ⁺ -type drain region 7. The first N ⁻ -type impurity diffusion region 9 formed so as to be covered is the N ⁺ except for the first N ⁻ -type impurity diffusion region 8.
The drain region 7 is surrounded and is adjacent to the P ⁺ region.
This is a second N ⁻ -type impurity diffusion region formed with a predetermined distance from the type isolation region 3.

Therefore, in the case of this conventional configuration, in order to turn on the transistor, the P-type silicon substrate 1 and the N ⁺ -type source region 4 are
While holding and at 0V, a predetermined positive bias voltage (usually about 5V) is applied to the N ⁺ drain region 7, and the gate electrode 6
When a predetermined positive bias voltage (usually about 5 V) is applied to the electrons, electrons pass from the N ⁺ type source region 4 through the channel region formed directly below the gate oxide film 5 and the first N ^−. After passing through the type impurity diffusion region 8, it reaches the N ⁺ type drain region 7, and a current flows in this way.

On the other hand, the P-type silicon substrate 1, the N ⁺ type source region 4 and the gate electrode 6 are kept at 0 V, and a positive bias voltage is applied to the N ⁺ type drain region 7 in this state. ,
The electric field is concentrated on the left end or the right end of the first N ⁻ type impurity diffusion region 8, and so-called avalanche breakdown occurs.

[Problems to be Solved by the Invention]

In the conventional device having the above-mentioned configuration, as described above, when a positive bias voltage is applied to the N ⁺ type drain region 7, the left end portion or the right end portion of the first N ⁻ type impurity diffusion region 8 is formed. However, if the impurity concentration is increased to avoid the electric field concentration in the first N ⁻ type impurity diffusion region 8, the device itself may be irreversibly destroyed. There is, also, while the first N ^-
When the impurity concentration of the type impurity diffusion region 8 is lowered, this causes a high resistance, which causes a problem that the gm (transconductance) of the device itself is deteriorated.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to prevent irreversible breakdown in a high breakdown voltage field effect transistor structure and also to reduce gm and breakdown voltage. It is an object of the present invention to provide a semiconductor device of this type in which the value can be held properly.

[Means for Solving the Problems]

In order to achieve the above object, a semiconductor device according to the present invention is provided with at least one of high-concentration source / drain regions of opposite conductivity type, which is provided on a substrate of a predetermined conductivity type or a well. Thus, a low-concentration impurity diffusion region of the opposite conductivity type is provided to form a junction with the high-concentration impurity region of the same conductivity type as the channel stopper.

That is, the present invention relates to a substrate or well of the first conductivity type, a thin gate oxide film on an element isolation oxide film, and a main surface separated by a high-concentration impurity region of the first conductivity type immediately below the element isolation oxide film. , In a field effect transistor structure in which a gate region formed of a gate electrode thereabove and a high-concentration source region of the second conductivity type and a drain region are provided with the gate region sandwiched between the source region and the drain region. A first low-concentration impurity diffusion region of the second conductivity type covered with a thick oxide film is provided between at least one of them and the gate region, and a source provided with the first low-concentration impurity diffusion region. The semiconductor device is characterized in that a second low-concentration impurity diffusion region of the second conductivity type is formed adjacent to the region and the drain region to form a junction with the high-concentration impurity region.

[Action]

Therefore, in the device of the present invention, the first conductivity type substrate,
Alternatively, with the gate region and the high-concentration source / drain regions of the second conductivity type sandwiching the gate region provided on the well, at least one of the high-concentration regions and the gate region A first low-concentration impurity diffusion region of the second conductivity type is provided between the source and drain regions adjacent to the source / drain regions, and a junction is formed between the high-concentration impurity region of the first conductivity type. Of the second conductivity type forming the
Since the low-concentration impurity diffusion region of is formed, the electric field concentration generated when a bias voltage is applied to the drain region side is set by optimizing the impurity concentration of each region forming these junctions. It can be moved from the left end or the right end of the first low concentration impurity diffusion region to the junction between the high concentration impurity region and the second low concentration impurity diffusion region. In this case, the first low concentration impurity diffusion region If the withstand voltage at the junction is set to be somewhat lower than the withstand voltage at 1, the device's withstand voltage and the value of gm can be properly maintained to prevent irreversible destruction.

〔Example〕

Hereinafter, different embodiments of the semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a schematic sectional view showing the outline of a field effect transistor to which an embodiment of the device of the present invention is applied. In the structure of the embodiment of FIG. The same or corresponding parts are shown.

That is, in the configuration of the embodiment shown in FIG. 1, reference numeral 1 is a P-type silicon substrate (or well),
Reference numeral 2a is a thick field oxide film formed on the main surface of the P-type silicon substrate 1 for element isolation.

Further, 3 is a P ⁺ -type isolation region (high-concentration impurity diffusion region) for a channel stopper, which is provided in a portion just below the field oxide film 2, and 4 is formed on the main surface of the P-type silicon substrate 1. 5 is an N ⁺ type source region, 5 is a thin gate oxide film formed on the same main surface, 6 is a gate electrode formed thereon and extending on the thick oxide film 2a, which forms a gate region, 7 Is an N ⁺ type drain region formed facing the N ⁺ type source region 4 with the gate region sandwiched therebetween.

Further, 8 is a first N ⁻ formed between the gate region and the N ⁺ type drain region 7 and covered with the thick oxide film 2a.
A type impurity diffusion region 9 is adjacent to the N ⁺ type drain region 7 except the first N ⁻ type impurity diffusion region 8 and is formed adjacent to the P ⁺ type isolation region 3. 2 is an N ⁻ -type impurity diffusion region.

Therefore, in the structure of this embodiment, in order to turn on the transistor, the P ⁺ type silicon substrate 1 and the N ⁺ type source region 4 are held at 0 V, and the N ⁺ type drain region 7 has a predetermined positive bias voltage ( When a predetermined positive bias voltage (usually about 5 V) is applied to the gate electrode 6 by applying a voltage of about 5 V), electrons are generated in the N ⁺ type source region 4 as in the case of the conventional configuration described above. Through the channel region formed immediately below the gate oxide film 5, the first N ⁻ type impurity diffusion region 8 and then the N ⁺ type drain region 7.
The current flows in this way.

On the other hand, the P-type silicon substrate 1, the N ⁺ -type source region 4 and the gate electrode 6 are kept at OV, and in this state, a positive bias voltage is applied to the N ⁺ -type drain region 7. ,
In this case, by optimizing the impurity concentrations of the P ⁺ -type isolation region 3 and the second N ⁻ -type impurity diffusion region 9, the first N ⁻ -type impurity in the case of the above-mentioned conventional configuration is used. The electric field concentration generated at the left end or right end of the diffusion region 8 can be moved to the junction between the second N ⁻ type impurity diffusion region 9 and the P ⁺ isolation region 3, and in this case, The breakdown voltage at the junction between the second N ⁻ type impurity diffusion region 9 and the P ⁺ isolation region 3 is higher than the breakdown voltage at the left end or right end portion of the first N ⁻ type impurity diffusion region 8. If it is set to a low level, the irreversible destruction can be prevented without significantly lowering the withstand voltage of the device itself, and thus the gm value.

In the configuration of the embodiment of FIG. 1, the thick oxide film 2a and the first and second N ⁻ are formed only on the N ⁺ type drain region 7 side.
Although the type impurity diffusion regions 8 and 9 are formed, they may be formed on the N ⁺ type source region 4 side or in the same manner as shown in the structure of the embodiment of FIG. In this case, it does not matter which of the two regions 4 and 7 is used as the source or the drain.

Although the P-type silicon substrate 1 is used in each of the embodiments, a P-type well formed on the N-type silicon substrate may be used. In each of the embodiments, an N-channel field effect transistor is used. However, it is needless to say that the same operation and effect can be obtained by setting the conductivity type in the opposite manner and applying to a P-channel field effect transistor.

〔The invention's effect〕

As described above in detail, according to the present invention, an electric field in which a gate region and a high-concentration source / drain region of the second conductivity type are provided on a substrate or a well of the first conductivity type with the gate region interposed therebetween. In the effect transistor, at least one of these source / drain regions,
A first low-concentration impurity diffusion region of the second conductivity type is provided between the gate region and the source / drain region provided with the first conductivity type high-concentration impurity region as a channel stopper. And a second low-concentration impurity diffusion region of the second conductivity type that forms a junction between the first and second conductivity types.
Since the second low-concentration impurity diffusion region of the conductivity type is adjacently formed by forming a junction, by optimizing the impurity concentration of each of these regions, a bias voltage is applied to the drain region side. The electric field concentration that occurs when
From the left end or right end of the low concentration impurity diffusion region of
It can be easily transferred to the junction between the high-concentration impurity region and the second low-concentration impurity diffusion region. In this case, the withstand voltage at the junction is lower than the withstand voltage at the first low-concentration impurity diffusion region. If set low enough, the breakdown voltage of this type of field-effect transistor and its gm value are hardly reduced, and irreversible destruction of the device can be effectively prevented, which helps improve its reliability. Moreover, when compared with the conventional example, it has excellent features such as a simple structure and easy implementation.

[Brief description of drawings]

1 and 2 are schematic sectional views showing the outline of a field effect transistor to which another embodiment of the device of the present invention is applied, and FIG. 3 is a field effect transistor according to a conventional example. FIG. 3 is a cross-sectional configuration diagram schematically showing the outline of FIG. 1 ... P-type silicon substrate (type well), 2,2a ... thick field oxide film, 3 ... P ⁺ type isolation region (high-concentration impurity diffusion region), 4 ... N ⁺ type source region, 5
And 6 ...... thin gate oxide film, and a gate electrode (gate region), 7 ...... N ⁺ -type drain region, 8 ...... first N ^-
Type impurity diffusion region, 9 ... Second N ⁻ type impurity diffusion region.

Claims (1)

[Claims] 1. A substrate or well of the first conductivity type,
A thin gate oxide film, a gate region composed of a gate electrode on the thin gate oxide film, and this gate region are sandwiched between the element isolation oxide film and the main surface separated by the first-conductivity-type high-concentration impurity region immediately below. In a field effect transistor structure provided with a high-concentration source region and a drain region of the second conductivity type,
A first low-concentration impurity diffusion region of the second conductivity type covered with a thick oxide film is provided between at least one of the source region and the drain region and the gate region, and A second low-concentration impurity diffusion region of the second conductivity type, which is adjacent to the source region and the drain region provided with the low-concentration impurity diffusion region and forms a junction with the high-concentration impurity region, is provided. Characteristic semiconductor device.