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JPH0770653B2 - High power hybrid integrated circuit assembly method - Google Patents

High power hybrid integrated circuit assembly method

Info

Publication number
JPH0770653B2
JPH0770653B2 JP61286657A JP28665786A JPH0770653B2 JP H0770653 B2 JPH0770653 B2 JP H0770653B2 JP 61286657 A JP61286657 A JP 61286657A JP 28665786 A JP28665786 A JP 28665786A JP H0770653 B2 JPH0770653 B2 JP H0770653B2
Authority
JP
Japan
Prior art keywords
power semiconductor
semiconductor chip
heat sink
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61286657A
Other languages
Japanese (ja)
Other versions
JPS63141355A (en
Inventor
千葉　　裕
義男 阿部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61286657A priority Critical patent/JPH0770653B2/en
Publication of JPS63141355A publication Critical patent/JPS63141355A/en
Publication of JPH0770653B2 publication Critical patent/JPH0770653B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高出力混成集積回路組立方法に係り特にパワ
ー半導体チップをヒートシンクに取り付けることに好適
な組立方法に関する。The present invention relates to a high-power hybrid integrated circuit assembling method, and more particularly to an assembling method suitable for mounting a power semiconductor chip on a heat sink.

〔従来の技術〕[Conventional technology]

すでに高出力混成集積回路組立方法に関しては、パワー
半導体チツプを個々に樹脂封止したデイスクリート部品
を使用しないで、パワー半導体の裸のチツプを直接混成
集積回路内に組み込み、デイスクリート部分を仕上げる
のに要する工数を、混成集積回路製造工数の中に吸収
し、二度の手間を排除し、かつ実装効率を上げて混成集
積回路装置の実装密度を向上させる考慮がなされてい
る。As for the high-power hybrid integrated circuit assembly method, the bare chip of the power semiconductor is directly incorporated in the hybrid integrated circuit without using the discrete components in which the power semiconductor chips are individually resin-sealed, and the discrete portion is finished. It is considered that the man-hours required for manufacturing the hybrid integrated circuit device are absorbed in the man-hours for manufacturing the hybrid integrated circuit to eliminate the trouble of twice and improve the packaging efficiency to improve the packaging density of the hybrid integrated circuit device.

しかし、当然のことながらさらに一層、構造や工数を単
純化し、工数削減や歩留向上を図りより安価で、かつパ
ワー半導体チツプ特有の熱放散の問題に起因する信頼性
も十分に考慮された構造を有する高出力混成集積回路組
立方法を提供する必要がある。However, as a matter of course, the structure and man-hours are further simplified, the man-hours are reduced and the yield is improved, the cost is lower, and the reliability due to the heat dissipation problem peculiar to the power semiconductor chip is sufficiently taken into consideration. There is a need to provide a high power hybrid integrated circuit assembly method having

そこで、まず従来のパワー半導体チツプを取り付けた放
熱用ヒートシンクを有する高出力混成集積回路組立方法
を第２図により説明する。Therefore, first, a conventional method for assembling a high-power hybrid integrated circuit having a heat sink for heat radiation to which a conventional power semiconductor chip is attached will be described with reference to FIG.

第２図において、１はパワー半導体チツプであり放熱を
良好ならしめるために、銅のヒートシンク２の上に固定
されている。この両者の固定は半田シート，リボン，デ
イスクなどの半田材３を間に挟み込んで、N2ガスなどの
雰囲気炉中で加熱溶融させることによつて行なわれる。In FIG. 2, reference numeral 1 is a power semiconductor chip, which is fixed on a copper heat sink 2 in order to improve heat dissipation. The two are fixed by sandwiching a solder material 3 such as a solder sheet, a ribbon, or a disk, and heating and melting in an atmosphere furnace of N 2 gas or the like.

このようにして出来上つたパワー半導体チツプアセンブ
リと表面に通常の厚膜混成集積回路方式，即ち導体，抵
抗体，誘電体の印刷，焼成，その他能動素子，受動素子
の組み込み等、公知の技術により構成された絶縁基板６
とを銅などの放熱板７に、半田付などにより取り付け
る。The power semiconductor chip assembly thus completed and the usual thick film hybrid integrated circuit system on the surface, that is, printing, firing of conductors, resistors and dielectrics, and the incorporation of other active devices and passive devices, etc. Insulated substrate 6 configured
And are attached to a heat sink 7 such as copper by soldering or the like.

その後パワー半導体チツプ１上の電極と絶縁基体上の導
体部５とを超音波ボンデイングなどの方法により、相互
に細線８によつて接続する。さらにコーテイング等を施
し、外部導出リードの取り付けを行ない、適当な蓋体で
覆えば完成する。After that, the electrode on the power semiconductor chip 1 and the conductor portion 5 on the insulating substrate are connected to each other by a thin wire 8 by a method such as ultrasonic bonding. Further, coating is applied, external lead-outs are attached, and the leads are covered with an appropriate lid to complete the process.

なお、この種の組立方法に関連するものには特公昭51−
46901号が上げられる。In addition, Japanese Patent Publication No. 51-
No. 46901 is raised.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記従来技術は工数と歩留および信頼性の点でもうひと
つ配慮がされておらず、次のような問題を残している。The above-mentioned prior art does not give consideration to man-hours, yield and reliability, and leaves the following problems.

第１の問題はヒートシンク２へのパワー半導体チツプ１
の組付けを行うときに半田シートなどの半田材３を両者
の間に挟み込むという余分な工数を必要とすることであ
る。またその作業はヒートシンク２上に正確な位置精度
でパワー半導体チツプ１と半田材３を重ね合わせる必要
があり大変面倒なものなつている。しかも半田加熱溶融
前の一時固定時にパワー半導体チツプ１と半田材３の安
定性が著しく悪く、細心の注意を払つた正確な作業が必
要ともなつていた。The first problem is the power semiconductor chip 1 to the heat sink 2.
This requires an extra man-hour for sandwiching the solder material 3 such as a solder sheet between the two when assembling. Further, the work is very troublesome because it is necessary to overlap the power semiconductor chip 1 and the solder material 3 on the heat sink 2 with accurate position accuracy. Moreover, the stability of the power semiconductor chip 1 and the solder material 3 is remarkably poor at the time of temporary fixing before the solder is melted by heating, and it is necessary to carry out precise work with great care.

第２の問題は前述のような作業のため歩留が悪くなると
いうことである。つまり第２図（ロ）に示すように、ヒ
ートシンク２上にパワー半導体チツプ１が水平に取り付
けられなかつたり、ずれたり、あるいは回転したりする
ものがあつた。またそのために配線作業が面倒になるの
みならず、配線が長くなつたり、短くなつたりすること
も避けられず、作業ミスによる配線作業の失敗が増大す
る。また線長が一定にならないことは、特にUHF帯など
の高周波領域においては、装置の電気性能のばらつきと
なり歩留低下につながつていた。The second problem is that the above-mentioned work results in poor yield. That is, as shown in FIG. 2B, the power semiconductor chip 1 is not mounted horizontally on the heat sink 2 and may be displaced, or rotated. Therefore, not only is the wiring work troublesome, but it is also unavoidable that the wiring becomes long or short, and the failure of the wiring work due to a work mistake increases. In addition, the non-uniform line length leads to variations in the electrical performance of the device, especially in the high-frequency region such as the UHF band, leading to a decrease in yield.

さらに第３の問題は半田材３がパワー半導体チツプ１の
裏面からある程度ずれて取り付けられた場合、パワー半
導体チツプ１からヒートシンク２への熱放散が低下し、
パワー半導体チツプ１の寿命が短くなり信頼性が低下す
るということである。A third problem is that when the solder material 3 is attached to the back surface of the power semiconductor chip 1 with some deviation, heat dissipation from the power semiconductor chip 1 to the heat sink 2 decreases,
This means that the life of the power semiconductor chip 1 is shortened and the reliability is lowered.

本発明の目的はこれら従来の問題を克服し、工数と歩留
および信頼性をよりいつそう向上させた高出力混成集積
回路組立方法を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a high power hybrid integrated circuit assembly method that overcomes these conventional problems and improves man-hours, yield and reliability.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、下記の方法により達成される。ひとつは放
熱用ヒートシンクにあらかじめ半田材が、パワー半導体
チツプを取り付けるのに十分な厚さでクラツドされたも
のを使用することである。ふたつ目はヒートシンクの半
田クラツド面にパワー半導体チツプを指示し、動きを拘
束できるくぼみを設けることである。The above object is achieved by the following method. One is to use a heat sink for heat radiation, which is pre-clad with solder material in a thickness sufficient to attach the power semiconductor chip. The second is to provide an indentation on the solder-clad surface of the heat sink to direct the power semiconductor chip and restrain its movement.

〔作用〕[Action]

このように半田クラツドが施されたヒートシンクを使用
することで、半田シートなどの半田材を両者の間に挟み
込むという余分な工数を必要としなくなり、さらにパワ
ー半導体チツプを指示し、かつ動きを拘束できるくぼみ
に嵌め込むだけでヒートシンク上に正確な位置精度でパ
ワー半導体チツプをきわめて容易に搭載でき、しかも半
田加熱溶融前の一時固定時の安定性も著しく向上し、作
業性が大変に良くなるのみならず、半田材を加熱溶融し
固定したあとの状態も良好で、配線作業の失敗も少く、
歩留が大幅に向上する。さらにヒートシンクとパワー半
導体チツプの半田付が確実となるのでパワー半導体チツ
プの熱放散も良く、信頼性も向上する。By using the heat sink with the solder cladding in this way, it is not necessary to put extra solder material such as a solder sheet between the two, and it is possible to direct the power semiconductor chip and restrain the movement. If the power semiconductor chip can be extremely easily mounted on the heat sink with accurate positioning accuracy just by fitting it in the recess, and the stability during temporary fixing before solder heating and melting is significantly improved, and workability is greatly improved. In addition, the state after heating and melting and fixing the solder material is also good, there are few wiring work failures,
The yield is greatly improved. Further, since the heat sink and the power semiconductor chip are reliably soldered, the heat dissipation of the power semiconductor chip is good and the reliability is improved.

〔実施例〕〔Example〕

以下、本発明の一実施例を第１図により説明する。 An embodiment of the present invention will be described below with reference to FIG.

第１図（ロ）は本発明の高出力混成集積回路組立方法の
要部断面図、第１図（イ）はそのパワー半導体チツプと
ヒートシンクを拡大した斜視図である。同図において１
は例えば高周波パワーMOSFETチツプなどのパワー半導体
チツプである。２は例えば無酸素銅等のヒートシンクで
あり、該ヒートシンク２の上面、すなわちパワー半導体
チツプ半田付面には適当な厚さの半田材３がクラツドさ
れている。これは、例えば無酸素銅板の上に冷間圧延圧
接法により半田を必要な厚さにクラツドしたものを適当
な形状にプレス成形することで得られる。このプレス成
形時にパワー半導体チツプを指示し、かつ動きを拘束で
きるようなくぼみ４を形成しておく。FIG. 1 (B) is a cross-sectional view of an essential part of a method for assembling a high-power hybrid integrated circuit according to the present invention, and FIG. 1 (A) is an enlarged perspective view of a power semiconductor chip and a heat sink. 1 in the figure
Is a power semiconductor chip such as a high frequency power MOSFET chip. Reference numeral 2 denotes a heat sink made of oxygen-free copper or the like, and a solder material 3 having an appropriate thickness is clad on the upper surface of the heat sink 2, that is, the power semiconductor chip soldering surface. This can be obtained, for example, by pressing an oxygen-free copper plate with solder to a required thickness by a cold rolling pressure welding method and press-molding it into an appropriate shape. At the time of this press molding, the recess 4 is formed so as to indicate the power semiconductor chip and restrain the movement.

ここでパワー半導体チツプ１とヒートシンク２とを一体
化するには、半田材３の上面にフラツクスを塗布して一
時的に固定し、その後半田材３をN2ガスなどの雰囲気炉
中で加熱溶融させたのち固体化してパワー半導体チツプ
１とヒートシンク２とを半田付する。Here, in order to integrate the power semiconductor chip 1 and the heat sink 2, a flux is applied to the upper surface of the solder material 3 and temporarily fixed, and then the solder material 3 is heated and melted in an atmosphere furnace of N 2 gas or the like. After that, the power semiconductor chip 1 and the heat sink 2 are solidified and soldered.

このようにして出来上つたパワー半導体アセンブリ部分
と絶縁基板６を放熱板７に取り付ける。この取り付けは
前記半田材３より融点の低い半田材を挟んで、N2ガスな
どの雰囲気炉中で行う。このとき前記絶縁基板６はパワ
ー部以外の低出力部分であり、表面に通常の混成集積回
路が構成されている。これは即ち導体，抵抗体，誘電体
の印刷，焼成，能動素子のボンデイングなどの公知の技
術を使用して回路が形成されている。パワー半導体チツ
プ上の電極と低出力部の導体５とを超音波圧着ボンデイ
ングなどの方法により、細線８によつて相互に接続され
て回路は完成するが、さらに外部導出リードの取付けや
樹脂等によるコーテイングを行い、適当な蓋体で覆えば
完成する。The power semiconductor assembly portion thus completed and the insulating substrate 6 are attached to the heat sink 7. This attachment is performed in an atmosphere furnace of N 2 gas or the like with a solder material having a melting point lower than that of the solder material 3 being sandwiched. At this time, the insulating substrate 6 is a low output portion other than the power portion, and a normal hybrid integrated circuit is formed on the surface thereof. Circuits are formed using known techniques such as printing conductors, resistors, dielectrics, firing, bonding active devices, and the like. The electrode on the power semiconductor chip and the conductor 5 of the low output portion are connected to each other by a thin wire 8 by a method such as ultrasonic pressure bonding bonding to complete the circuit. Complete by coating and covering with a suitable lid.

すなわち、本実施例によれば、パワー半導体チツプとヒ
ートシンクとの両者の間に半田シートなどの半田材を挟
み込むという余分な工数を不要とし、さらにパワー半導
体チツプをくぼみに嵌め込むだけでヒートシンク上に正
確な位置精度でパワー半導体チツプをきわめて容易に搭
載でき、作業性が大変良くなるのみならず、半田材を加
熱溶融し固定したあとのヒートシンク上へのパワー半導
体チツプの固定位置および水平精度も良好で歩留が大幅
に向上する。さらにヒートシンクとパワー半導体チツプ
間の半田付が確実となることでパワー半導体チツプが動
作時に発生する熱をヒートシンクに確実に伝えることが
でき、信頼性の高い装置となりうる。That is, according to the present embodiment, an extra man-hour of sandwiching a solder material such as a solder sheet between both the power semiconductor chip and the heat sink is unnecessary, and further, the power semiconductor chip is simply fitted into the indentation so that the power semiconductor chip is mounted on the heat sink. The power semiconductor chip can be mounted very easily with accurate position accuracy, and not only the workability is greatly improved, but also the fixing position and horizontal accuracy of the power semiconductor chip on the heat sink after the solder material is heated and melted and fixed are good. The yield is greatly improved. Further, since the soldering between the heat sink and the power semiconductor chip is reliable, the heat generated during the operation of the power semiconductor chip can be surely transmitted to the heat sink, which can be a highly reliable device.

〔発明の効果〕〔The invention's effect〕

以上のように本発明によれば、パワー半導体チツプをヒ
ートシンク上に固定する際に、むずかしい作業であると
ころの半田シート等を両者の間に挟み込むという工程を
排除でき、ヒートシンク上におけるパワー半導体チツプ
の水平精度，取付位置精度も向上させることができるた
め歩留が向上することでコスト低減となる。さらにパワ
ー半導体チツプとヒートシンクの両者を、機械的かつ放
熱効果的に充分な状態で固着することができるため信頼
性をもよりいつそう向上させた高出力混成集積回路組立
方法を提供することができる。As described above, according to the present invention, when fixing the power semiconductor chip on the heat sink, the step of sandwiching a solder sheet or the like between them, which is a difficult work, can be eliminated, and the power semiconductor chip on the heat sink can be removed. Since the horizontal accuracy and the mounting position accuracy can be improved, the yield is improved and the cost is reduced. Further, since both the power semiconductor chip and the heat sink can be fixed mechanically and effectively in heat dissipation in a sufficient state, it is possible to provide a high output hybrid integrated circuit assembling method with improved reliability. .

【図面の簡単な説明】[Brief description of drawings]

第１図は、本発明による高出力混成集積回路組立方法を
説明する一実施例の要部断面図およびそのパワー半導体
チツプとヒートシンクを拡大した斜視図である。第２図
は従来の高出力混成集積回路組立方法を説明する為の斜
視図，断面図である。 １……パワー半導体チツプ ２……ヒートシンク、３……半田材 ４……くぼみ、５……導体部 ６……絶縁基板、７……放熱板 ８……細線FIG. 1 is a cross-sectional view of an essential part of an embodiment for explaining a method for assembling a high-power hybrid integrated circuit according to the present invention and an enlarged perspective view of a power semiconductor chip and a heat sink. FIG. 2 is a perspective view and a sectional view for explaining a conventional high-power hybrid integrated circuit assembling method. 1 ... Power semiconductor chip 2 ... Heat sink, 3 ... Solder material 4 ... Dimple, 5 ... Conductor part, 6 ... Insulating substrate, 7 ... Heat sink, 8 ... Fine wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】ヒートシンクにパワー半導体チップを取り
付けたパワー半導体アセンブリを放熱板に取付ける高出
力混成集積回路組立方法において、前記ヒートシンクに
半田材を板状に接着してクラッド化し、前記半田材を加
熱溶融して前記パワー半導体チップと前記ヒートシンク
とを固定してパワー半導体アセンブリとし、 前記半田材より低融点の半田材を前記パワー半導体アセ
ンブリと前記放熱板との間に挟んで、加熱溶融して取付
けることを特徴とする高出力混成集積回路組立方法。1. A method for assembling a high-power hybrid integrated circuit in which a power semiconductor assembly having a power semiconductor chip attached to a heat sink is attached to a heat sink. A solder material is adhered to the heat sink in a plate shape to form a clad, and the solder material is heated. The power semiconductor chip and the heat sink are melted and fixed to each other to form a power semiconductor assembly, and a solder material having a melting point lower than that of the solder material is sandwiched between the power semiconductor assembly and the heat dissipation plate, heated, melted, and attached. A method for assembling a high-power hybrid integrated circuit, comprising: 【請求項２】上記ヒートシンクに上記パワー半導体チッ
プを落し込むくぼみを設けたことを特徴とする特許請求
の範囲第１項記載の高出力混成集積回路組立方法。2. The method for assembling a high-power hybrid integrated circuit according to claim 1, wherein the heat sink is provided with a recess for dropping the power semiconductor chip.
JP61286657A 1986-12-03 1986-12-03 High power hybrid integrated circuit assembly method Expired - Lifetime JPH0770653B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61286657A JPH0770653B2 (en) 1986-12-03 1986-12-03 High power hybrid integrated circuit assembly method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61286657A JPH0770653B2 (en) 1986-12-03 1986-12-03 High power hybrid integrated circuit assembly method

Publications (2)

Publication Number Publication Date
JPS63141355A JPS63141355A (en) 1988-06-13
JPH0770653B2 true JPH0770653B2 (en) 1995-07-31

Family

ID=17707265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61286657A Expired - Lifetime JPH0770653B2 (en) 1986-12-03 1986-12-03 High power hybrid integrated circuit assembly method

Country Status (1)

Country Link
JP (1) JPH0770653B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783033B2 (en) * 1988-11-30 1995-09-06 太陽誘電株式会社 Semiconductor element fixing plate sheet and method of using the same
DE3922485C1 (en) * 1989-07-08 1990-06-13 Doduco Gmbh + Co Dr. Eugen Duerrwaechter, 7530 Pforzheim, De
JPH03135053A (en) * 1989-10-20 1991-06-10 Sumitomo Metal Mining Co Ltd Heat-sink material
DE19605302A1 (en) * 1996-02-14 1997-08-21 Fraunhofer Ges Forschung Heatsink with a mounting surface for an electronic component
JP3241639B2 (en) * 1997-06-30 2001-12-25 日本電気株式会社 Multi-chip module cooling structure and method of manufacturing the same

Also Published As

Publication number Publication date
JPS63141355A (en) 1988-06-13

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