JPH0770497B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to selective diffusion of Sb (antimony).

(Prior Art) A conventional Sb selective diffusion will be described with reference to FIGS.

First, on the surface of the P-type silicon substrate 1, SiO _{2 having a} thickness of about 1 μm
The film 2 is grown (FIG. 2 (a)).

Next, using a known photolithography technique, a window 3 is opened in the SiO ₂ film 2 on the region where Sb is to be diffused (FIG. 2 (b)).

Then, on the entire surface of the SiO ₂ film 2 including the window 3, Sb silica film (SbCl ₃ and Si (OH) ₄ dissolved in a solvent such as ethanol, for example, SiO ₂ concentration 2%, SbCl ₃ concentration 2gr /
A 100 cc composition silica film 4 is spin-coated to a thickness of about 1000Å (Fig. 2 (c)).

After that, heat treatment is performed in an inert gas atmosphere at 1200 ° C. containing about 5% oxygen. Then, Sb is diffused from the Sb silica film 4 in the window 3 portion into the silicon substrate 1, and Sb is spread on the substrate 1.
The diffusion layer 5 is selectively formed (FIG. 2 (d)).

The Sb selective diffusion by the spin coating method of the Sb silica film has been described above, but the Sb diffusion layer is used as, for example, the N type buried diffusion layer of the bipolar type integrated circuit. A structural sectional view of this bipolar integrated circuit is shown in FIG.

In FIG. 3, 11 is a P-type silicon substrate, 12 is an N-type (S
b) buried diffusion layer, 13 N ^- type epitaxial layer, 14 P type isolation region, 15 oxide film, 16 collector (N type) extraction diffusion layer, 17 collector electrode, 18 base (P type) ) Diffusion layer,
Reference numeral 19 is a base electrode, 20 is an emitter (N type) diffusion layer, and 21 is an emitter electrode.

(Problems to be Solved by the Invention) However, in the above-described conventional Sb selective diffusion method, during the heat treatment, a defect flower-shaped defect layer called Sb rosette, which is crystallized SiO ₂ glass, is formed into the SiO ₂ film. However, there is a problem in that Sb is diffused into a region other than the selected region through the defective layer portion and causes an electrical failure. this
The occurrence of electrical defects due to the occurrence of Sb rosettes will be described below with reference to FIGS. 4 and 5 by taking a bipolar integrated circuit as an example.

FIG. 4 (a) shows a silicon substrate in which Sb silica film is spin-coated. In the figure, 31 is a P-type silicon substrate, 32 is a SiO ₂ film, 33 is a window, and 34 is an Sb silica film. When this is heat-treated for 8 hours in a quartz reaction tube of 1200 ° C. N ₂ 4 / M, O ₂ 200 CC / M atmosphere, as shown in FIG. 4 (b), the selected substrate corresponding to the window 33 is selected. An Sb diffusion layer 35 as a buried diffusion layer is formed in the region. At this time, a SiO ₂ crystallized material 36 (hereinafter referred to as Sb rosette) called Sb rosette is formed.
A rosette) is generated in the SiO ₂ film 32. And
When the Sb rosette 36 is generated, the state of the SiO ₂ is different from that of the surrounding SiO ₂ when the SiO ₂ is crystallized, and thus a crack or a gap is generated, and Sb is diffused into the silicon substrate 31 through the crack or the gap, and the silicon substrate 31 The Sb diffusion layer 37 is formed in a region other than the selected region.

Then, when Sb is diffused in a region other than the selected region in this way, when a bipolar integrated circuit is formed as shown in FIG. 5, the Sb diffusion layer 37 and the P-type isolation region 38 other than the selected region are separated. It collides with each other, resulting in poor withstand voltage. In addition, the Sb diffusion layer 37
If the area is large, problems such as separation cannot occur.

The present invention has been made in view of the above points, and its purpose is to eliminate the occurrence of rose-shaped crystal defects called Sb rosettes that occur at the time of Sb diffusion, and the subsequent manufacturing of semiconductor integrated circuits has been completed. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can obtain an integrated circuit free from electrical defects at the time.

(Means for Solving Problems) This invention is a method for manufacturing a semiconductor device in which Sb silica film is used to selectively diffuse Sb using a SiO ₂ film as a mask, and the Sb silica film is applied to a film thickness of 500 Å or less. It is something that is done.

(Operation) The present inventor conducted the following experiment in order to investigate the cause of the occurrence of the Sb rosette.

Instead of the Sb silica film 4 shown in FIG. 2 (c), a non-dove (Sb-free) silica film was coated to the same thickness and the same heat treatment was performed. As a result, it was confirmed that no rosette was generated, and it was found that the rosette has a close relationship with Sb in the silica film.

In addition, the film thickness of the spin-coated Sb silica film
As a result of investigating the relationship with the number of rosettes, it was found that the tendency was as shown in FIG. The tendency is that the number of Sb rosettes generated is extremely reduced when the film thickness is 500 Å or less, and is not related to the concentrations of SbCl ₃ and Si (OH) _{4 in} the Sb silica film. .

The present invention arose from these experiments, and Sb
By applying silica film to a film thickness of 500 Å or less and performing Sb selective diffusion, the generation of Sb rosettes is almost eliminated as in the case of the experiment. Therefore, in addition to the selective diffusion area
Sb will not be spread.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG.

First, as shown in FIG. 1 (a), a P-type silicon substrate 41
An SiO ₂ film 42 is grown to a thickness of 1 μm on the SiO ₂ film 42, and a window 43 is opened at a desired position of the SiO ₂ film 42 (position where Sb diffusion is performed) by using a known photolithography technique.

Next, as shown in FIG. 1B, the entire surface of the SiO ₂ film 42 including the window 43 is covered.
Sb silica film 44 (SiO ₂ concentration 1%, SbCl ₃
(Silica film with composition of concentration 4gr / 100cc was used)
Is spin-coated to a film thickness of 400Å.

After that, baking is performed at 200 ° C. for about 10 minutes in the atmosphere to evaporate the residual solvent in the Sb silica film 44.

Then, by heat treatment in an inert gas atmosphere of 1200 ° C. containing 5% of oxygen, as shown in FIG. 1 (c),
In the window 43 portion, the Sb diffusion layer 45 is formed in the silicon substrate 41 by Sb diffusion from the Sb silica film 44. At this time, no Sb rosette was generated in the SiO ₂ film 42.

(Effects of the Invention) As described in detail above, according to the method of the present invention,
Since the film thickness of Sb silica film is less than 500Å, S
It is possible to almost prevent Sb rosettes from being generated in the SiO ₂ film during the b diffusion. Therefore, it is also possible to prevent Sb from diffusing in areas other than the selective diffusion area under the SiO ₂ film,
When a bipolar integrated circuit is formed, there is an advantage that neither a breakdown voltage defect nor a separation defect occurs. Therefore, an effect of improving the yield of the integrated circuit can be expected.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device of the present invention, FIG. 2 is a process sectional view showing a conventional Sb selective diffusion, and FIG. 3 is a buried diffusion layer formed by Sb selective diffusion. Structural sectional view of formed bipolar integrated circuit, FIG. 4 is a sectional view showing generation of Sb rosette, FIG. 5 is a structural sectional view of bipolar integrated circuit showing defect due to generation of Sb rosette, and FIG. 6 is Sb FIG. 6 is a characteristic diagram showing the relationship between the silica film thickness and the number of Sb rosettes generated. 41 …… P-type silicon substrate, 42 …… SiO ₂ film, 43 …… Window, 44
...... Silica film, 45 …… Sb diffusion layer.

Claims (3)

[Claims] 1. A step of forming a mask layer on a semiconductor substrate, a step of opening a window at a desired position of the mask layer to expose a part of the semiconductor substrate, and the exposed semiconductor substrate and the mask layer. Characterized in that it has a step of forming a diffusion source layer containing Sb with a film thickness of 500 Å or less, and then diffusing Sb from the diffusion source layer into the semiconductor substrate by performing a heat treatment. Of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion source layer containing Sb is a Sb silica film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the mask layer is SiO ₂ .