JPH0765053A - Interactive layout verifying device - Google Patents

Abstract

PURPOSE:To shorten the analyzing time of the verifying result by providing a function to support a job that specifies an error part. CONSTITUTION:The layout verifying device is provided with an interactive control means 11 which controls an input means 19 and a graphic display 18, a partial data generating means 12 which generates the verifiable partial data from the layout data 15 and a net list 16, a verifying means 13 which applies the comparison and verification to the partial data based on a verifying rule 17, and a result holding means 14 which holds the verifying result that is used for the second verification.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for performing layout verification in the process of LSI design.

[0002]

2. Description of the Related Art The configuration of a conventional layout verification device is shown in FIG.
Shown in. The dialogue control means 41 instructs the start of verification by the input means 19, and displays the error obtained as a result of the verification on the graphic display 18, and the verification means 42 uses the layout data 15 and the netlist 16 to execute the device information according to the verification rule 17. The result holding unit 43 is a unit that holds the verification result generated by the verifying unit 42. The result holding unit 43 holds the verification result.

FIG. 5 is a diagram showing a flow of processing. The processing flow will be described with reference to FIGS. 4 and 5. When the dialogue control means 41 gives an instruction to start the process, the verification means 42 causes the verification rule 17 in the data input step 51.
And the layout data 15 and the netlist 16 are read according to the verification rule 17. In the verification step 52, the verification means 42 extracts the device information and the device connection information from the layout data 15 and the netlist 16 according to the verification rule 17 and performs comparative verification. In the error data generation step 53, the verification means 42 extracts the error data from the verification result and stores it in the result holding means 43. The error display step 54 displays the error data by the dialogue control means 41.

[0004]

In the conventional verification device,
Only the error part was displayed as a result of the verification. However, in general, the layout and the netlist are matched so that the number of matching devices is maximized and the number of errors is minimized by tracing the connections of the devices. Therefore, if there is a complicated and similar structure, incorrect matching occurs, and the position displayed as an error is often displaced from the position considered by the layout designer to be an error. Therefore, there is a problem that the designer needs to check the layout data and the netlist from the error display and specify the error position. In this case, if you look only around the error position, matching is performed, though it is incorrect.Therefore, in both the layout data and the netlist, the connections of the devices around the error position as a result of verification are tracked thoroughly and incorrect The time consuming task of getting the true error position by inferring the point where the matching occurred has had to be done.

In order to solve the above problems, the present invention provides
The first purpose is to shorten the analysis time of the verification result by providing the function of supporting the work for specifying the error location.

A second object is to provide a function of performing the matching semi-automatically in order to accurately display the error portion, reduce the matching amount and shorten the verification processing time.

[0007]

In order to achieve the above object, the layout verification apparatus of the present invention does not limit the verification result to error information and stores all the results including a set of devices that have been successfully matched. To do. Furthermore, in order to realize the first object, a function of displaying individual devices and wirings that have succeeded in matching in a form of being compared on the layout data and the netlist is provided.

Further, in order to achieve the second object, the correspondence between the layout data and the device and wiring of the netlist is partially provided in advance, and a function of performing matching based on the correspondence is provided. In addition, a part of the verification result is discarded, the device correspondence is added to the remaining verification result, and the partial data generation means is used to reduce the data amount when performing the matching again using the verification result and the additional information. To provide.

[0009]

By displaying the layout data and the netlist for each matched device and wiring, the designer can easily find the error when the device laid out by himself is matched with another device. As a result, the time required to identify the error location is shortened. Also, by giving the device correspondence as a part of the verification result as additional information and performing verification by using them, an accurate error according to the designer's intention can be obtained and the verification time at the time of re-verification can be shortened. It Also,
By generating partial data using the verification result, the verification time at the time of re-verification can be shortened.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the layout verification apparatus of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a layout verification apparatus of the present invention. In FIG. 1, the dialogue control means 11
Layout data 1 on the graphic display 18
5, the net list 16 and the verification result are combined and displayed, and the data instructed by the input means 19 is selected or the start of the verification is instructed. The partial data generating means 12 is means for generating partial data from the layout data 15 and the netlist 16 according to an instruction from the dialogue control means 11.
The verification unit 13 receives the partial data of the layout data 15 and the netlist 16 from the partial data generation unit 12, extracts the device information and connection information according to the verification rule 17, and refers to the verification result stored in the result holding unit 14. However, it is a means for performing comparative verification and generating a new verification result. Result holding means 14 is verification means 13
It is a means for holding the verification result generated by.

FIG. 2 is a processing flow chart of the layout verification apparatus of the present invention. The processing flow of this embodiment will be described below with reference to FIGS. 1 and 2.

First, in the data input step 21, the dialogue control means 11 uses the input means 19 to instruct the partial data generation means 12 to start verification. The partial data generation means 12 uses the layout data 15 and the netlist 16
To the verification means 13, and the verification means 13 sends the verification rule 1
After reading 7, the layout data 15 and the netlist 16 are read according to the verification rule 17.

In the verification step 22, the verification means 13 extracts the device information and the device connection information from the data input according to the verification rule 17, performs comparative verification, and holds the verification result in the result holding means 14.

In the result retrieval step 23, the dialogue control means 1
According to the instruction 1, the layout data 15 and the netlist 16 are displayed side by side on the graphic display 18, and the corresponding devices and wirings are selectively combined and displayed. FIG. 3 is an example of the display. The layout display unit 31 and the netlist display unit 32 are arranged on the same screen, and the verification result can be confirmed while comparing the layout data 15 and the netlist 16. Layout display 31
By instructing one or more devices and wirings therein, a marker 33 is displayed overlaid on the instructed devices and wirings. At the same time, the corresponding device and wiring in the netlist are highlighted 34. Similarly, when the device and wiring are instructed in the net list display unit 32, the marker 33 is displayed on the corresponding device and wiring in the layout display unit 31. If the corresponding device and wiring do not exist, this is displayed and it can be confirmed that an error has occurred.

If there is an erroneous match in the verification result, after the deletion range of the verification result is specified from the dialogue control means 11 in the additional data input step 25, the correspondence of the device used in the next verification is used as additional information. input.

Further, in the partial data creating step 26, the partial data generating means 12 uses the additional information from the dialogue control means 11 and the verification result of the result holding means 14 to generate the partial data from the layout data 15 and the netlist 16. . Generated partial data is verified again Step 2
A more accurate error position is obtained by performing the verification in 2.

It is possible to facilitate the selection by making the correspondence between the layout data and the netlist not only in units of devices but also in the unit of the hierarchical structure of layout data and netlists.

(Embodiment 2) FIG. 6 shows the layout verification apparatus of Embodiment 1 in which the layout data 15 and the netlist 1 are added.
6 is a block diagram of the layout verification device to which the correction means of 6 is added,
FIG. 7 is a processing flow chart of the same. 1 and 2
Means having the same function as are given the same reference numerals, and description thereof will be omitted.

In FIG. 6, the data correction means 61 is means for correcting the layout data or the netlist which has been confirmed to be an error as a result of the verification. When the verification result is searched and the position of the error can be specified, the layout data or the netlist is corrected using the data correction means 61 in the data correction step 71. At that time, the verification result obtained from the neighborhood of the corrected data is
It is discarded from the result holding means 14 according to the instruction obtained by the dialogue control means 11 or a predetermined rule. At the time of re-verification, the remaining verification result is used, so that the verification time can be shortened.

[0021]

As described above, the layout verification apparatus of the present invention makes it possible to easily confirm that the device and the wiring are correctly matched from the result of the comparative verification of the layout data and the netlist. Since the layout data and the device and wiring of the netlist are displayed in association with each other at the same time, it is possible to quickly identify the location of the problem from the location output as the error.

Further, it is possible to output an error at an accurate position by creating partial data by utilizing the correspondence between the previous verification result and the device given as the additional information and executing the verification on the partial data. At the same time, the verification time can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a layout verification device according to a first embodiment of the present invention.

FIG. 2 is a flowchart of layout verification processing in the same embodiment.

FIG. 3 is a view showing layout data and a netlist side by side on a graphic display in the same embodiment.

FIG. 4 is a configuration diagram of a layout verification device in a conventional example.

FIG. 5 is a flowchart of layout verification processing in a conventional example.

FIG. 6 is a configuration diagram of a layout verification device according to a second embodiment of the present invention.

FIG. 7 is a flowchart of layout verification processing in the same embodiment.

[Explanation of symbols]

 11 Dialogue Control Means 12 Partial Data Generation Means 13 Verification Means 14 Result Holding Means 18 Graphic Display 21 Data Input Step 22 Verification Step 23 Result Search Step 24 Error Judgment Step 25 Additional Data Input Step 26 Partial Data Creation Step 31 Layout Data Display Section 32 Net list display section 61 Data generation means 71 Data correction step

Claims (3)

[Claims] 1. A dialogue control means for controlling an input means and a graphic display, a verification means for performing a comparative verification from layout data and a netlist using a verification rule, and a result holding for holding a verification result used for another verification. A layout verification apparatus comprising: 2. An interactive control means for controlling the input means and the graphic display, a partial data generation means for generating partial data that can be verified from the layout data and the netlist, and a verification rule for this partial data. A layout verification apparatus comprising: verification means for performing comparative verification and result holding means for holding a verification result used for another verification. 3. The layout verification apparatus according to claim 1, further comprising a correction unit that corrects the layout data and the netlist.