JPH0764849A - Shared memory controller for processor - Google Patents

Abstract

PURPOSE:To provide a shared memory controller which enables an MPU with the standby function and an MPU without the standby function to simultaneously access a shared memory. CONSTITUTION:An MPU 2 with the standby function, an MPU 3 without the standby function, a shared memory controller 10 provided with not only chip select circuits 5 and 6 which receive the use request signals sent from MPUs 2 and 3, but also a busy generation circuit which sends a standby signal to one MPU during the write operation of the other MPU, and a shared memory 4 which is shared between MPUs 2 and 3 to read and write information, are provided, and, the shared memory controller 10 is provided with an access time counter 1 which counts the time to the end of write of one of MPUs 2 and 3 and sends time information resulting from addition of a prescribed margin to this time to MPUs 2 and 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory control device for a processor, and more particularly, to efficiently use the shared memory by controlling the use priority of the shared memory when accessing the shared memory from a plurality of microprocessor units (MPUs). The present invention relates to a shared memory control device of a processor capable of sharing various memories.

[0002]

2. Description of the Related Art Generally, in a shared memory (for example, dual port RAM) in which a plurality of MPUs are the same resource,
In order to avoid contention when the MPUs 2 and 3 simultaneously access the same address at least in the write stage, each MPU is given an appropriate priority and shared memory is allocated for use, so-called arbitration.
Ion) is performed. On the other hand, as a method of giving a usage priority right to a plurality of MPUs, there are a first-come-first-served method and a fixed priority method in which a usage right is given priority to an MPU having a high priority. In the first-come-first-served system, the first-arrival MPU occupies the shared memory and other M
The PU enters the standby state by the standby signal.

As shown in FIG. 2, a shared memory control device adopting the conventional first-come-first-served system has two MPUs.
Standby circuits 8 and 9 are provided in 2 and 3, and the first-arrival MPU
Uses the shared memory 4 via the shared memory control device 11. The shared memory control device 11 includes chip select circuits 5 and 6 and a busy generation circuit 7, which will be described later. In the operation of this conventional example, when the MPU 2 outputs the use request signal 6A to the chip select circuit 6, the shared memory 4 is occupied and at least the write operation to the shared memory is started.
On the other hand, the busy generation circuit 7 provided in the shared memory control device 11 sends the busy signal 7A during use of the shared memory 4 to the MPU3.
And waits until the writing of MPU2 is completed. On the other hand, when the MPU 3 sends the use request signal 5A to the chip select circuit 5, the busy signal 7B is sent to the MPU 2 to wait, and then the shared memory 4 is occupied to perform the write operation or the like. Further, when the dual port RAM is used, the read operation can be simultaneously accessed by both MPUs. However, when one write operation is completed and the standby signal is released, another MP
When U starts writing, the read data may change in the middle, so it is necessary to read the output data after a predetermined time has elapsed after the standby signal was reset.

[0004]

This conventional shared memory control device has the drawback that both MPUs both require a standby circuit. Further, since there is no timing information for the standby circuit to reset the standby signal indicating the completion of writing and the other MPU starts writing, the read timing is unsuitable especially when reading is performed simultaneously like the dual port RAM. There is also a drawback.

[0005]

A shared memory control device for a processor according to the present invention comprises at least two microprocessor units (MPU), a chip select circuit for receiving a use request signal sent from the MPU, and one MPU. A shared memory control device provided with a busy generation circuit for sending a standby signal to the other MPU during a write operation, and a shared memory for writing and reading storage information shared by the MPU via the shared memory control device. In the shared memory control device of the processor having, the shared memory control device counts the time until the end of writing one of the MPUs, and count time information obtained by adding a predetermined extra time to the time until the end of writing. An access time counter for sending to the other MPU is provided.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, the same reference numerals as those in the conventional example of FIG. 2 have the same configuration and function. That is, in the embodiment of FIG. 1, the shared memory control device 10 is provided with the access time counter 1 for counting the write time of one of the MPUs, and the other MPU is configured by deleting the standby circuit.

The access time counter 1 shown in FIG.
The writing time of U3 is counted, and after the writing time ends, a predetermined time (reading time margin) is added and the count signal 1A is sent to the MPU3 to recognize the readability. Further, the count signal 1A indicating that the writing of MPU3 is completed and the writing of MPU2 is possible is also sent to MPU2.

Next, a case where this embodiment operates as a fixed priority system will be described. MP for shared memory controller 10
When the use request signal 5A is input from U3, the access time counter 1 starts counting via the chip select circuit 5 and outputs the count signal 1B to the MPU 3 to start writing. After that, when the usage request signal 6A is input from the MPU 2, the access time counter 8 stops counting and holds the access time of the usage request signal 5A. This is because the continuous access time disappears due to the input of the use request signal 6A. Then, the usage request signal 6A of the MPU 2 having a higher fixed priority is enabled and the count signal 1A is output, and at the same time, the busy signal 7 is sent from the busy generation circuit 7 to the MPU 3.
Output A. When the write access from the MPU 2 is completed, the access time disappeared by the input of the use request signal 6A is added to the busy signal 7A. The MPU 3 continues the operation extended by the temporary stop.

[0011]

As described above, according to the present invention, by providing the access time counter, the priority order of two MPUs is fixed and shared between the MPU having the standby function and the MPU having no standby function. This has the effect of enabling simultaneous access to the specified memory.

[0012]

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

 1 Access time counter 2 MPU (master) 3 MPU (slave) 4 Shared memory 5,6 Chip select circuit 7 Busy generation circuit 8 Standby circuit 10 Shared memory control device

Claims (3)

[Claims] 1. At least two microprocessor units (MPU), a chip select circuit for receiving a use request signal sent from the MPU, and one MP
A shared memory control device provided with a busy generation circuit that sends a standby signal to the other MPU during a write operation by the U, and a shared memory device that writes and reads stored information shared by the MPU via the shared memory control device In a shared memory control device of a processor having a memory, the shared memory control device counts a time until the end of writing of one of the MPUs, and a count time obtained by adding a predetermined free time to the time until the end of writing. A shared memory control device for a processor, comprising an access time counter for sending information to the other MPU. 2. One of the MPUs is provided with a standby circuit for receiving a standby signal of the busy generation circuit, and the use priority of the shared memory is given to the other of the MPUs not provided with the standby circuit. A shared memory control device for a processor according to claim 1. 3. The shared memory is a dual port RAM
3. The shared memory control device for a processor according to claim 1, wherein: