JPS62107492A - Memory control method - Google Patents

Abstract

PURPOSE:To decrease the number of signal lines by requesting data reading/ writing between a memory using circuit and a memory control circuit while classifying according to the size of length of on time of one signal line. CONSTITUTION:A read/write common control circuit 5 in a memory using circuit (ADP) 1 turns on a memory using signal MRQ 1 for a prescribed one machine cycle (m) time at the time of the data reading request and turns it on for two machine cycles (m) time at the time of the data writing request. A memory control circuit 6 sends a busy displaying signal BUSY 1 to an ADP 2 by the MRQ 1, simultaneously, the reading/writing request is judged by the on time of the MRQ 1 and a memory (RAM) 4 is accessed. Thus, the data reading/ writing request can be executed by one signal line and the signal line can be decreased.

Description

[Detailed Description of the Invention] [Summary] This is a memory control method in which data read/write requests to a memory between a memory use circuit and a memory control circuit are conventionally made using a data read request line or a data write request. By making data read/write requests to the memory based on the difference in the ON time of one signal line, the memory usage circuit and the memory control circuit can be It is possible to reduce the number of signal lines between the two.

[Industrial application field]

The present invention relates to a memory control method when a memory that stores data is shared by a plurality of memory-using circuits.

For example, when the memory that constitutes the central processing unit of a computer is shared and accessed by multiple memory-using circuits, it is common practice to physically define access requests through multiple signal lines. There is.

However, as the usage of electronic computers becomes more sophisticated and complex, the physical number of signal lines used between internal functional blocks tends to increase. In view of this situation, there are expectations for the development of a method that allows memory access requests to be defined using fewer signal lines.

[Prior art and problems to be solved by the invention] Fig. 4 is a system diagram explaining the conventional example, Fig. 5 is a block diagram explaining the conventional example, and Fig. 6 is a time chart of the conventional example. Figures are shown respectively.

FIG. 4 is a diagram showing a conventional memory (RAM) 4 control method, in which a memory usage circuit (which sends out a request to use the memory (RAM) 4 and makes a data read/write request).
(hereinafter referred to as 〇P) 1.2 and multiple ADPIs,
The instructions from 2 are selected based on a predetermined priority order, and the selected ADPI is stored in memory (RAM) according to the request from 2.
4, and a memory (RAM) 4 that is accessed by the memory control circuit 3 and writes and stores data.

Note that (11 to (3) in ADPI 2 and (a) to (C1 and (a)' to (C)' in memory control circuit 3 indicate pin terminals of signal lines, and (1) and ( a) ((al'
) means data read request signals 1QIR, MRQ2R, (
2) and (b) ((b) ') are data write request signals MRQIW, MRQ2W, (3) and fc) ((
C) ”) is the in-use display signal BUSY2. BUSY
These are pin terminals corresponding to I and I, respectively.

FIG. 5 is a block diagram showing a conventional example of the memory control circuit 3, which includes flip-flop circuits (hereinafter referred to as F and F) that set data read request signals MRQIR, MRQ2R and data write request signals 1 IW, MRQ2-. 301～
304, F, F2O3, 0R that takes the logical sum condition of 302
A plurality of write data (i.e., write data from ADPI, 2) are input by output signals from N0R309, 0R305. (
A multiplexer (hereinafter referred to as MPX) 307.0R3 that selects and outputs one of the RITE DATA))
X308 selects and outputs one of a plurality of input addresses (i.e., the address of ADPI, 2) according to the output signal from ADP2.
N0R309 sets the counter 311 to the initial value at the fall of the in-use display signal BUSYI for ADPI, and when the data write request signal MRQ2W is on, the counter 312 is set at the fall of the in-use display signal BUSY2 for ADPI.
N0R310 to set to the initial value Counters 311, 312 and +1 circuits 313, 314, counters 311, 312 that count up by +1 from the initial set value
The negative polarity of the counter value "2" (i.e., C2) from the count value of
Inverter 315.316 to take out, “C2” signal from inverter 315.316 to NAN
0R317 sent to D318, write enable signal (hereinafter referred to as WE) pulse and 0R3
Taking the NAND condition with the sending signal from 17, *WI
It is composed of a NAND 318 that sends out the li signal.

Figure 6 (A) is a time chart for data read (READ) requests, and Figure 6 (B) is for data write (WRITE) requests.
) Time chart at the time of request 1. Figure 6 (C) is ADP1
FIG. 6(D) shows a time chart when data read (READ) requests from ADPI, 2 conflict, and FIG. 6(D) shows a time chart when data write (WRITE) requests from ADPI, 2 conflict.

For example, in the case of FIG. 6(A), when the data read request signal MRQIR from ADPI is turned on via the signal line consisting of (1) and (a), the F in the memory control circuit 3
, F2O3 is set to the signal MRQIR.

MPX30B uses ADPI (7
)7)' Select the response and send the memory address specified by this to the memory (RAM) 4.

At the same time, a chip select signal *C3 is sent to the memory (RAM) 4 by No. 13 from F, F2O3, the memory chip at the designated memory address is selected, and data is read from it.

Next, in the case of the write request shown in FIG. 6(B), for example, A
Data write request signal MRQIW from DPI is (2
) and crest), the signal MRQI- is set in F and R 302 in the memory control circuit 3.

Based on this signal MRQI-, the MPX307 selects the write data side RITE DATA from ADPI and transfers it to the memory (RAM) 4, and the IPX308 selects the address of ADP1 based on this signal MRQIW-2.
The memory address specified by this is stored in memory (RAM).
) is sent for 4.

At the same time, a chip select signal *C3 is sent to memory (RAM) 4 by signals from F and R302.
The memory chip at the specified memory address is selected.

On the other hand, the counter 312, which was set to the initial state by the previous access end signal END, starts counting, and the count value becomes "
2'', a write enable signal *WE is sent to the memory (RAM) 4, and data writing is started. It is assumed that the counting start control of the counters 311 and 312 is performed by a circuit not shown.

In the case of FIG. 6(C), there is a conflict between the data read request signals MRQIR and MRQ2R from ADPI2, and the memory address selection at this time is determined by ADPI2 in MPX308.
It is set so that requests from the PI take priority.

Therefore, a signal BUSYI indicating that ADPI is currently being accessed is sent to ADP2 via signal lines (3) and (C)'. During this time, ADP2 is in a standby state, and when access from ADPI ends, access from ADP2 is started.

Similarly, when data write request signals MRQIW and MR02- from ADPI2 shown in FIG. 6(D) conflict, the request from ADPI is given priority, and the request from ADP2 is placed in a standby state.

Note that this example uses the data write request signal MR from ADP2.
02- is first, and before the count value of the counter 311 reaches "2", the data write request signal MR port 1 from ADPI is received.
This is the case if there was a hut.

At this time, the count of the counter 311 continues as it is until the falling edge of the in-use display signal BUSYI (that is, the end of access from ADP1) is detected.

It is cleared to the initial state by a signal from R309, starts counting anew, and when the counted value reaches "2", access from ADP2 is started.

As described above, at least three signal lines are required to define access control to the memory (RAM) 4 between the ADPI 2 and the memory control circuit 3.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

This principle block diagram is composed of ADPs 1 and 2, a memory control circuit 6, and a memory (RAM) 4, as in FIG.

Further, a memory (RAM) 4 use request signal between ADPI, 2 and memory control circuit 6 is a memory use signal MR.
QI.

This memory use signal MRQI, 2 is performed using a signal line consisting of (1) and (a) ((a)''').

Note that the memory use signal MRQI, 2 from ADPI, 2 is a read/write common control that controls data read requests and write requests based on the difference in the time when the signal line is on (i.e., the number of on cycles). The information is configured to be transmitted through the means 5.

[Effect]

A data read/write request to the memory between the ADP and the memory control circuit is made by a read/write common control means that physically requests the read/write of data to the memory based on the difference in on-time of one signal line. By providing and controlling the ADP in the ADP, it is possible to physically reduce the number of signal lines between the ADP and the memory control circuit.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 to 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating a time chart of an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

FIG. 2 is a block diagram mainly showing an embodiment of the memory control circuit 6 in the present invention.
Data reading from the memory (RAM) 4 is performed using a time difference (difference in the number of on-time cycles) when the memory use signals MR01 and 2 are turned on (difference in the number of cycles of the on time), which is newly provided in the read/write common control circuit 5. Distinguish whether it is a request or a write request.

The memory use signal MRQI, 2 sent out from the read/write common control circuit 5 is controlled so that its on time is an integral multiple of a preset machine cycle m.

For example, in this embodiment, one machine cycle m time memory use signal 1'! An example will be explained in which it is defined that when RQI, 2 is turned on, it is a data read request, and when 2 machine cycles m time is defined as a data write request.

The memory control circuit 6 uses this memory use signal MRQI.

2 to F, F61, 62, and NAND6
3.65 and 0R67, or NAND64.66 and 0
The a1'' signal is sent to the input terminal of NAND69 through R67.

On the other hand, F, which has set the memory use signal MRQI, 2,
The MPX307 or MPX30B is controlled based on the difference in machine cycle m times during which the output signals of F61 and F62 are turned on.

For example, F, F set by memory use signal MRQI
If the ON time of the output signal 61 is equivalent to 2 machine cycles m, the MPX307 transfers the write data (RITE DATA) from ADPI to the memory (1?AM).
) Send to 4.

Also, MPX308 reads the memory (R
At the same time, the address of AM) 4 is sent out, and the chip at the address where the data is to be written is designated by the chip select signal *C8 from the 0R68, and the data is written to the designated location by the write permission signal *row from the NAND69.

Note that when the memory use signal MRQI is on for one machine cycle m time, it is regarded as a data read request.

An example of its operation is shown in FIG. 3(A). Further, FIG. 3(B) shows the case of the above-mentioned data writing system '41'.

FIG. 3(C) is an example where data read requests from ADP1 and ADP2 conflict, and the memory control circuit 6 is
It is set to give priority to access from
At the same time as it receives the memory use signal MRQI from ADPI, it sends the in-use display signal BUSYI to ADP2 and puts it in a standby state.

Next, FIG. 3(D) is an example of a case where data write requests from ADPI,2 conflict. In addition, in this case as well, A
An example is shown in which the memory use signal MR port 1 from ADPI is received before the on time of the memory use signal l port 2 from DP2 reaches the equivalent of 2 machine cycles m hours.

In this case, the access from ADP2 to the memory use signal MRQ2 is interrupted and put on hold, and after the access from ADPI is completed, the access from ADP2 is performed again.

〔Effect of the invention〕

According to the present invention as described above, regarding access control to memory, it is possible to reduce the number of physical signal lines between the memory use circuit and the memory control circuit.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram explaining the present invention in detail, Fig. 3 is a diagram explaining a time chart of an embodiment of the present invention, and Fig. 4 is a diagram explaining a conventional example. 5 is a block diagram illustrating a conventional example, and FIG. 6 is a diagram illustrating a time chart of the conventional example. In the figure, 1.2 is the memory use circuit (ADP), 301 to 304, 6L62 is F, F, 305, 3
17,67.68 is OR. 306, 309, 310 are NOR, 307, 308 are MPX. 311.312 is a counter, 313.314 is a +1 circuit, 315.316 is an inverter,

Claims (1)

[Claims] The first and second memory use circuits (1, 2) access the memory (4) via the memory control circuit (6), and
Or the memory (
The access order for 4) is a memory control method that gives priority to the first memory usage circuit (1), and the memory (4) is in the first and second memory usage circuits (1, 2). read/write common control means (5) for controlling data read requests and write requests to the first and second memory use circuits (MRQ1, 2) by controlling on-time lengths of memory use signals (MRQ1, 2); ) to the memory control circuit (6), the data write/read requests for the memory (4) are distinguished by the length of the ON time of the memory use signals (MRQ1, MRQ2). control method.