JPH0754838B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0754838B2 JPH0754838B2 JP62002314A JP231487A JPH0754838B2 JP H0754838 B2 JPH0754838 B2 JP H0754838B2 JP 62002314 A JP62002314 A JP 62002314A JP 231487 A JP231487 A JP 231487A JP H0754838 B2 JPH0754838 B2 JP H0754838B2
- Authority
- JP
- Japan
- Prior art keywords
- cap
- face
- type semiconductor
- ceramic substrate
- down type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 56
- 239000000919 ceramic Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 28
- 238000002844 melting Methods 0.000 claims description 26
- 230000008018 melting Effects 0.000 claims description 25
- 230000002093 peripheral effect Effects 0.000 claims description 12
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 11
- 230000005855 radiation Effects 0.000 claims description 4
- 238000005219 brazing Methods 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 238000004512 die casting Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔概要〕 セラミック基板上に、フェースダウン型半導体素子が実
装されたモノリシック集積回路、或いは混成集積回路
を、キャップで封止した半導体装置において、セラミッ
ク基板の表面に蝋付け実装されるフェースダウン型半導
体素子は、裏面にアース電極を有し、天井板部の内面が
フェースダウン型半導体素子の裏面に直接，或いは台座
を介して密着して低融点蝋材で接着され、且つ周縁部が
セラミック基板の周縁部近傍に形成したほぼ環状のアー
スパターンに低融点蝋材で固着される熱伝導性・導電性
に優れたキャップで、フェースダウン型半導体素子を封
止する構造とすることにより、フェースダウン型半導体
素子の接地特性、及び放熱性の向上をはかる。DETAILED DESCRIPTION OF THE INVENTION [Outline] In a semiconductor device in which a monolithic integrated circuit in which a face-down type semiconductor element is mounted on a ceramic substrate or a hybrid integrated circuit is sealed with a cap, the surface of the ceramic substrate is brazed. The face-down type semiconductor element to be mounted has a ground electrode on the back surface, and the inner surface of the ceiling plate portion is adhered to the back surface of the face-down type semiconductor element directly or through a pedestal and adhered with a low melting point wax material, And a structure in which a face-down type semiconductor element is sealed by a cap excellent in thermal conductivity and conductivity, which is fixed to a substantially annular ground pattern whose peripheral portion is formed in the vicinity of the peripheral portion of a ceramic substrate with a low melting point wax material. By doing so, the grounding characteristics and heat dissipation of the face-down type semiconductor element can be improved.
〔産業上の利用分野〕 本発明は、フェースダウン型半導体素子が実装されたモ
ノリシック集積回路、或いは混成集積回路を、金属キャ
ップで封止した半導体装置の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device in which a monolithic integrated circuit in which a face-down type semiconductor element is mounted or a hybrid integrated circuit is sealed with a metal cap.
近年は、半導体ウエハの回路形成面の所望の個所に、電
極ダンプを突出して設け、この電極ダンプをセラミック
基板の表面に形成したパターンに蝋付け固着する構造の
半導体素子、所謂フェースダウン型半導体素子を有する
モノリシック集積回路、或いは混成集積回路よりなる半
導体装置が、電子装置に広く使用されている。In recent years, a semiconductor element having a structure in which an electrode dump is provided at a desired position on a circuit formation surface of a semiconductor wafer and the electrode dump is brazed and fixed to a pattern formed on the surface of a ceramic substrate, a so-called face-down type semiconductor element A semiconductor device including a monolithic integrated circuit or a hybrid integrated circuit having is widely used in electronic devices.
第３図は従来の半導体装置の側断面図であって、モノリ
シック集積回路を構成するフェースダウン型半導体素子
１の回路形成面1aの端部に、所望数の電極ダンプ２を設
け、フェースダウン型半導体素子１を逆さにして、電極
ダンプ２をセラミック基板３の表面に形成したパターン
４に、半田７で半田付けして実装してある。FIG. 3 is a side sectional view of a conventional semiconductor device, in which a desired number of electrode dumps 2 are provided at an end of a circuit forming surface 1a of a face-down type semiconductor element 1 which constitutes a monolithic integrated circuit. The semiconductor element 1 is turned upside down, and the electrode dump 2 is mounted on the pattern 4 formed on the surface of the ceramic substrate 3 by soldering with the solder 7.
そして、それぞれのパターン４の端末は、セラミック基
板３を貫通するリード端子５の頭部に、それぞれ半田付
け接続してある。The ends of each pattern 4 are soldered to the heads of the lead terminals 5 that penetrate the ceramic substrate 3.
そして、深さが、フェースダウン型半導体素子１の実装
高さよりも充分に深い皿形の金属キャップ６を、セラミ
ック基板３に冠着させ、縁部をセラミック基板３の周縁
の上面に、半田８で固着することにより、フェースダウ
ン型半導体素子１を気密に封止し、保護している。Then, a dish-shaped metal cap 6 having a depth sufficiently deeper than the mounting height of the face-down type semiconductor element 1 is capped on the ceramic substrate 3, and an edge portion is soldered on the upper surface of the peripheral edge of the ceramic substrate 3. The face-down type semiconductor element 1 is hermetically sealed and protected by being fixed by.
しかしながら上記従来例の半導体装置は、フェースダウ
ン型半導体素子１の接地部分が電極ダンプ２だけである
ので、接地特性が低いという問題点がある。However, the semiconductor device of the conventional example has a problem that the grounding characteristics are low because the grounded portion of the face-down type semiconductor element 1 is only the electrode dump 2.
また、フェースダウン型半導体素子１の熱が、電極ダン
プ２を介してセラミック基板３に伝達され、セラミック
基板３の裏面より放熱される構造であって、熱伝達抵抗
が大きくて、冷却性が劣るという問題点がある。In addition, the heat of the face-down type semiconductor element 1 is transferred to the ceramic substrate 3 via the electrode dump 2 and radiated from the back surface of the ceramic substrate 3, and the heat transfer resistance is large and the cooling property is poor. There is a problem.
本発明はこのような点にかんがみて創作されたもので、
放熱性が良好で、且つ接地特性が高い、半導体装置を提
供することを目的としている。The present invention was created in view of these points.
It is an object of the present invention to provide a semiconductor device having good heat dissipation and high grounding characteristics.
上記従来の問題点を解決するため本発明は、第１図に例
示したように、セラミック基板３の表面に蝋付け実装さ
れる、裏面1bにアース電極を有するフェースダウン型半
導体素子１と、天井板部の内面がフェースダウン型半導
体素子１の裏面1bに直接，或いは台座20を介して密着し
て低融点蝋材11で接着され、且つ周縁部がセラミック基
板３の周縁部近傍に形成したほぼ環状のアースパターン
に、低融点蝋材11で固着される熱伝導性・導電性に優れ
たキャップ16とを備えた構造とする。In order to solve the above-mentioned conventional problems, the present invention is, as illustrated in FIG. 1, a face-down type semiconductor element 1 having a ground electrode on a back surface 1b, which is mounted by brazing on the surface of a ceramic substrate 3, and a ceiling. The inner surface of the plate portion is adhered to the back surface 1b of the face-down type semiconductor element 1 directly or in close contact with the pedestal 20 with the low melting point wax material 11, and the peripheral portion is formed near the peripheral portion of the ceramic substrate 3. A structure is provided in which an annular ground pattern is provided with a cap 16 excellent in thermal conductivity and conductivity fixed by a low melting point wax material 11.
さらに冷却能力を高めるために、キャップ16の天井板部
の外面に、放熱フィン15を低融点蝋材12で固着したもの
である。In order to further enhance the cooling capacity, the heat radiation fins 15 are fixed to the outer surface of the ceiling plate portion of the cap 16 with the low melting point wax material 12.
また、第２図に例示したように、フェースダウン型半導
体素子１を含んだ混成集積回路の場合には、高融点蝋材
21でフェースダウン型半導体素子１の裏面1bに密着させ
た、熱伝導性・導電性に優れた台座20を介して、キャッ
プ16の天井板部の内面とフェースダウン型半導体素子１
の裏面1bとを、密着させるようにしたものである。Further, as illustrated in FIG. 2, in the case of a hybrid integrated circuit including the face-down type semiconductor element 1, a high melting point wax material
The face down type semiconductor element 1 and the inner surface of the ceiling plate portion of the cap 16 are attached to the back surface 1b of the face down type semiconductor element 1 with the pedestal 20 having excellent thermal conductivity and conductivity.
The back surface 1b of the above is closely contacted.
上記本発明の手段によれば、フェースダウン型半導体素
子１の裏面1bにアース電極を設けることにより、直接或
いは金属台座20を介して、熱伝導性・導電性に優れたキ
ャップ16に接地することができ、接地抵抗が極めて小さ
くなる。According to the above-mentioned means of the present invention, by providing the ground electrode on the back surface 1b of the face-down type semiconductor element 1, it is possible to ground directly or through the metal pedestal 20 to the cap 16 having excellent thermal conductivity and conductivity. And the ground resistance becomes extremely small.
また、フェースダウン型半導体素子１の熱が、熱伝達面
積の大きいフェースダウン型半導体素子１の裏面1bから
直接に、又は金属台座20を介してキャップ16に伝達さ
れ、放熱面積を大きいキャップ16の表面から放熱される
ので、放熱性が向上する。In addition, the heat of the face-down type semiconductor element 1 is transferred to the cap 16 directly from the back surface 1b of the face-down type semiconductor element 1 having a large heat transfer area or via the metal pedestal 20, so that the heat dissipation area of the cap 16 is large. Since the heat is radiated from the surface, the heat dissipation is improved.
さらにまた、キャップ16の天井板部の外面に、放熱フィ
ン15を固着することにより、冷却能力がさらに高くな
る。Furthermore, by fixing the heat radiation fins 15 to the outer surface of the ceiling plate portion of the cap 16, the cooling capacity is further enhanced.
なお、フェースダウン型半導体素子１の裏面1bとキャッ
プ16、及びキャップ16とセラミック基板３とは、電極ダ
ンプ２とパターン４とを接着する蝋材10よりも、融点が
低い低融点蝋材11で蝋付けする構造であるので、キャッ
プ16の蝋付け作業が容易で、半導体装置の製造コストが
低い。The back surface 1b of the face-down type semiconductor element 1 and the cap 16, and the cap 16 and the ceramic substrate 3 are made of a low melting point wax material 11 having a lower melting point than the wax material 10 for bonding the electrode dump 2 and the pattern 4. Since the structure is brazing, the operation of brazing the cap 16 is easy and the manufacturing cost of the semiconductor device is low.
以下図を参照しながら、本発明を具体的に説明する。な
お、全図を通じて同一符号は同一対象物を示す。The present invention will be specifically described below with reference to the drawings. The same reference numerals denote the same objects throughout the drawings.
第１図は本発明の一実施例の側断面図、第２図は本発明
の他の実施例の側断面図である。FIG. 1 is a side sectional view of an embodiment of the present invention, and FIG. 2 is a side sectional view of another embodiment of the present invention.
第１図において、モノリシック集積回路を構成するフェ
ースダウン型半導体素子１の回路形成面1aの端部に、所
望に電極ダンプ２を設け、さらに、裏面1bにアース電極
を設けてある。In FIG. 1, an electrode dump 2 is provided at an end of a circuit forming surface 1a of a face-down type semiconductor element 1 which constitutes a monolithic integrated circuit, and a ground electrode is further provided on a back surface 1b.
このようなフェースダウン型半導体素子１を逆さにし
て、電極ダンプ２をセラミック基板３の表面に形成した
パターン４のパット部分に、Sn−Pb系の蝋材10（融点18
3℃）で蝋付けし実装してある。The face-down type semiconductor device 1 is turned upside down, and the Sn-Pb-based brazing material 10 (melting point 18) is applied to the pad portion of the pattern 4 in which the electrode dump 2 is formed on the surface of the ceramic substrate 3.
Soldered at 3 ℃) and mounted.
そして、それぞれのパターン４の端末は、セラミック基
板３を貫通するリード端子５の頭部に、それぞれ蝋付け
して接続してある。The terminals of each pattern 4 are brazed and connected to the heads of the lead terminals 5 penetrating the ceramic substrate 3.
キャップ16は熱伝導性・導電性に優れ、熱膨張係数がセ
ラミック基板３の熱膨張係数に近い材料、例えばFe−Ni
合金（42−アロイ）よりなり、皿形に形成してある。The cap 16 has excellent thermal conductivity and conductivity, and has a coefficient of thermal expansion close to that of the ceramic substrate 3, such as Fe-Ni.
It is made of alloy (42-alloy) and is shaped like a dish.
このキャップ16の深さはフェースダウン型半導体素子１
の実装高さよりもわずかに大きいものとする。The depth of the cap 16 is the face-down type semiconductor device 1
It shall be slightly larger than the mounting height of.
上述のような、キャップ16を、セラミック基板３に冠着
させ、フェースダウン型半導体素子１の裏面1bとキャッ
プ16の天井板部の内面、及びキャップ16の縁とセラミッ
ク基板３の周縁部近傍に形成したほぼ環状のアースパタ
ーンとを、例えばビスマス半田よりなる低融点蝋材11
（融点150℃）で蝋付けし、フェースダウン型半導体素
子１を気密に封止してある。As described above, the cap 16 is capped on the ceramic substrate 3, and the back surface 1b of the face-down type semiconductor element 1 and the inner surface of the ceiling plate portion of the cap 16 and the edge of the cap 16 and the vicinity of the peripheral edge of the ceramic substrate 3 are provided. The formed substantially circular earth pattern is connected to the low melting point wax material 11 made of, for example, bismuth solder.
The face-down type semiconductor element 1 is hermetically sealed by brazing with a melting point of 150 ° C.
なお、上述の蝋付けは、低融点蝋材11のシートをフェー
スダウン型半導体素子１の裏面1bと、セラミック基板３
の周縁の上面とに載せた後に、キャップ16をセラミック
基板３に冠着し、キャップ16の天井板部の外側に、ヒー
ターを押し当て、160℃〜170℃にキャップ16を加熱する
ことにより、容易に蝋付けできるものである。In addition, in the above brazing, the sheet of the low melting point wax material 11 is attached to the back surface 1b of the face-down type semiconductor element 1, the ceramic substrate 3
After being placed on the upper surface of the peripheral edge of the cap 16, the cap 16 is attached to the ceramic substrate 3, a heater is pressed against the outside of the ceiling plate portion of the cap 16, and the cap 16 is heated to 160 ° C. to 170 ° C. It can be easily brazed.
上述のように構成されているので、フェースダウン型半
導体素子１は、フェースダウン型半導体素子の表面に形
成されたアース電極−電極ダンプ−セラミック基板３の
表面に形成されたアースパットという従来よりある接地
回路に加えて、フェースダウン型半導体素子の裏面に形
成されたアース電極−低融点蝋材11−キャップ16−セラ
ミック基板の周縁部近傍に形成したほぼ環状のアースパ
ターン−接地用端子（図示せず）という接地回路が構成
される。よって、接地特性が向上する。Since the face-down type semiconductor device 1 is configured as described above, the face-down type semiconductor device 1 has a conventional structure including a ground electrode formed on the surface of the face-down type semiconductor device, an electrode dump, and a ground pad formed on the surface of the ceramic substrate 3. In addition to the ground circuit, a ground electrode formed on the back surface of the face-down type semiconductor element-low melting point wax material 11-cap 16-a substantially annular ground pattern formed near the peripheral edge of the ceramic substrate-grounding terminal (not shown). The ground circuit called "z)" is configured. Therefore, the grounding characteristics are improved.
また、フェースダウン型半導体素子１は、面積の大きい
裏面1bとキャップ16とが密着しているので、放熱性が良
好である。Further, in the face-down type semiconductor element 1, since the back surface 1b having a large area and the cap 16 are in close contact with each other, the heat dissipation is good.
なお、第１図においては、さらに放熱性を向上させるた
めに、キャップ16の天井板部の外側に例えばアルミニュ
ウムがダイキャストされてなる、多数の突出した板片が
並列した放熱フィン15を、低融点蝋材12（例えばIn半田
−融点100℃）で蝋付けして接着してある。In addition, in FIG. 1, in order to further improve heat dissipation, a radiator fin 15 formed by die-casting aluminum, for example, on the outside of the ceiling plate portion of the cap 16 and having a large number of protruding plate pieces arranged in parallel is shown in FIG. A melting point wax material 12 (for example, In solder-melting point 100 ° C.) is brazed and adhered.
また、キャップ16の材料を、セラミック基板３の熱膨張
係数に近い熱膨張係数の材料に選定してあるので、環境
温度変化により、セラミック基板3,キャップ16が膨張或
いは収縮しても、蝋付け部分に、応力が附加されること
がなく、蝋材に亀裂が発生する恐れがなくて、気密封止
の信頼度が高いものである。Moreover, since the material of the cap 16 is selected to be a material having a thermal expansion coefficient close to that of the ceramic substrate 3, even if the ceramic substrate 3 and the cap 16 expand or contract due to environmental temperature changes, brazing is performed. No stress is applied to the part, there is no risk of cracks in the wax material, and the reliability of hermetic sealing is high.
第２図に示す実施例は、混成集積回路に本発明を適用し
たものであって、セラミック基板３には、フェースダウ
ン型半導体素子１の他に受動素子であるチップ部品30が
搭載されている。The embodiment shown in FIG. 2 is one in which the present invention is applied to a hybrid integrated circuit, and a chip component 30 which is a passive element is mounted on the ceramic substrate 3 in addition to the face-down type semiconductor element 1. .
このチップ部品30の実装高さは、フェースダウン型半導
体素子１の実装高さよりも大きいので、第１図のように
フェースダウン型半導体素子１の裏面1bを直接、キャッ
プ16に低融点蝋材11で蝋付けすることができない。Since the mounting height of this chip part 30 is larger than the mounting height of the face-down type semiconductor element 1, the back surface 1b of the face-down type semiconductor element 1 is directly attached to the cap 16 as shown in FIG. Can not be brazed with.
したがって、フェースダウン型半導体素子１をセラミッ
ク基板３に実装する前に、予めフェースダウン型半導体
素子１の裏面1bに、裏面1bと平面形状が等しく、厚さが
チップ部品30の実装高さと、キャップ16の深さより定ま
る所定の厚さの角板状の、熱伝導性・導電性に優れた材
料、例えばFe−Ni合金（42−アロイ）よりなり台座20
を、高融点蝋材21（例えばAu−Sn系半田、融点280℃）
で蝋付け固着しておき、キャップ16をセラミック基板３
に冠着し、台座20の上面とキャップ16の天井板部の内面
とを、低融点蝋材11で蝋付け固着したものである。Therefore, before mounting the face-down type semiconductor element 1 on the ceramic substrate 3, the back side 1b of the face-down type semiconductor element 1 has the same planar shape as the back side 1b in advance, and the thickness is the mounting height of the chip component 30 and the cap. A pedestal made of a square plate-shaped material having a predetermined thickness determined by the depth of 16 and having excellent thermal conductivity and conductivity, for example, Fe-Ni alloy (42-alloy)
High melting point wax material 21 (eg Au-Sn solder, melting point 280 ° C)
Braze and fix with the cap 16 on the ceramic substrate 3
The upper surface of the pedestal 20 and the inner surface of the ceiling plate portion of the cap 16 are brazed and fixed with the low melting point wax material 11.
なお本発明は図示例に限定されるものでなく、例えばセ
ラミック基板３を上部が開口した箱形に形成し、その上
面に板状のキャップ（例えばFe−Ni合金，セラミックよ
りなるキャップ）を低融点蝋材11で固着した構造のもの
も、含まれるものである。The present invention is not limited to the illustrated example, and for example, the ceramic substrate 3 is formed in a box shape with an upper opening, and a plate-shaped cap (for example, a cap made of Fe-Ni alloy or ceramic) is provided on the upper surface thereof. A structure in which the melting point wax material 11 is fixed is also included.
以上説明したように本発明は、天井板部の内面を、フェ
ースダウン型半導体素子の裏面に直接，或いは台座を介
して密着させ、低融点蝋材で接着し、且つ周縁部をセラ
ミック基板の周縁の上面に低融点蝋材で固着し防止した
半導体装置であって、フェースダウン型半導体素子の接
地特性、及び放熱性が高い等、実用上で優れた効果があ
る。As described above, according to the present invention, the inner surface of the ceiling plate portion is brought into close contact with the back surface of the face-down type semiconductor element directly or via the pedestal, and is adhered with a low melting point wax material, and the peripheral portion is the peripheral edge of the ceramic substrate. It is a semiconductor device in which the upper surface of the semiconductor device is fixed by a low melting point wax material and is prevented, and has a practically excellent effect such as a grounding characteristic of a face-down type semiconductor element and high heat dissipation.
第１図は本発明の一実施例の側断面図、 第２図は本発明の他の実施例の側断面図、 第３図は従来例の側断面図である。 図において、 １はフェースダウン型半導体素子、 1aは回路形成面、 1bは裏面、 ２は電極ダンプ、 ３はセラミック基板、 ５はリード端子、 ６は金属キャップ、 7,8,は半田、 10は蝋材、 11,12は低融点蝋材、 15は放熱フィン、 16はキャップ、 20は台座、 21は高融点蝋材、 30はチップ部品をそれぞれ示す。 FIG. 1 is a side sectional view of an embodiment of the present invention, FIG. 2 is a side sectional view of another embodiment of the present invention, and FIG. 3 is a side sectional view of a conventional example. In the figure, 1 is a face-down type semiconductor element, 1a is a circuit forming surface, 1b is a back surface, 2 is an electrode dump, 3 is a ceramic substrate, 5 is a lead terminal, 6 is a metal cap, 7,8, is solder, and 10 is A wax material, 11,12 are low melting point wax materials, 15 is a radiation fin, 16 is a cap, 20 is a pedestal, 21 is a high melting point wax material, and 30 is a chip part.
Claims (2)
る、裏面（1b）にアース電極を有するフェースダウン型
半導体素子（１）と、 天井板部の内面が、該フェースダウン型半導体素子
（１）の裏面に直接，或いは台座（20）を介して密着し
て低融点蝋材（11）で接着され、且つ周縁部が該セラミ
ック基板（３）の周縁部近傍の上面に形成したほぼ環状
のアースパターンに、低融点蝋材（11）で固着される熱
伝導性・導電性に優れたキャップ（16）とを、備えたこ
とを特徴とする半導体装置。1. A face-down type semiconductor element (1) mounted on the front surface of a ceramic substrate (3) and having a ground electrode on the back surface (1b), and an inner surface of the ceiling plate portion (1). 1) directly attached to the back surface of the ceramic substrate (3) or in close contact with the pedestal (20) with a low melting point wax material (11) and having a substantially annular shape whose peripheral edge is formed on the upper surface near the peripheral edge of the ceramic substrate (3) The semiconductor device characterized in that the ground pattern of (1) is provided with a cap (16) which is fixed with a low melting point wax material (11) and has excellent thermal conductivity and conductivity.
低融点蝋材（12）で固着された放熱フィン（15）を有す
ることを特徴とする、特許請求の範囲第１項に記載の半
導体装置。2. The outer surface of the ceiling plate portion of the cap (16),
The semiconductor device according to claim 1, further comprising a radiation fin (15) fixed with a low melting point wax material (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62002314A JPH0754838B2 (en) | 1987-01-08 | 1987-01-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62002314A JPH0754838B2 (en) | 1987-01-08 | 1987-01-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63169749A JPS63169749A (en) | 1988-07-13 |
| JPH0754838B2 true JPH0754838B2 (en) | 1995-06-07 |
Family
ID=11525875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62002314A Expired - Lifetime JPH0754838B2 (en) | 1987-01-08 | 1987-01-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0754838B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275580A (en) * | 1992-03-25 | 1993-10-22 | Nec Corp | Semiconductor device |
| KR100209782B1 (en) * | 1994-08-30 | 1999-07-15 | 가나이 쓰도무 | Semiconductor device |
| JP4832334B2 (en) * | 2001-07-30 | 2011-12-07 | 日立プラズマディスプレイ株式会社 | Plasma display device |
| JP2016039213A (en) * | 2014-08-06 | 2016-03-22 | ローム株式会社 | Substrate built-in package, semiconductor device, and module |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5965458A (en) * | 1982-10-05 | 1984-04-13 | Mitsubishi Electric Corp | Manufature of semiconductor device |
| JPS60253248A (en) * | 1984-05-30 | 1985-12-13 | Hitachi Ltd | Heat conductive cooling module device |
-
1987
- 1987-01-08 JP JP62002314A patent/JPH0754838B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63169749A (en) | 1988-07-13 |
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