JPH0744445B2 - Digital PLL circuit - Google Patents

Description

The present invention relates to a digital PLL (Phase Locked Loop) circuit that obtains an output signal in synchronization with an input signal, and more particularly to widen the range of a fraction of the input signal. The present invention relates to a possible digital PLL circuit.

Configuration of Conventional Example and Problems Thereof The digital PLL circuit is widely used for vertical and horizontal synchronizing circuits, tuning circuits, frequency conversion circuits, etc. of televisions and video devices, and its configuration is schematically shown in FIG. As shown in the circuit configuration diagram, it is roughly divided into a clock frequency dividing circuit unit 1, a clock selecting circuit unit 2, and a clock counting circuit unit 3. In this case, the range of the input signal whose output can be locked is generally expressed by the following equation.

_TH · NTT _L · N (1) where the high frequency of the clock signal (CK) (CK _H )
The period of T _H and the period of the lower frequency (CK _L )
Let T _{L be} the period of the input signal V _IN , and let the count value of the clock counting circuit section 3 be N.

However, in the conventional circuit example, since the count value N of the clock counting circuit unit 3 is fixed, the frequency range of the input signal that can lock the output is limited to a narrow range.

An object of the present invention is to provide a digital PLL circuit capable of expanding the frequency range of an input signal whose output can be locked.

The present invention is summarized as follows: A clock pulse on the low frequency side obtained by inputting a clock pulse from the outside and dividing by X (X is an integer of 2 or more) and a clock pulse input from the outside. The clock frequency dividing circuit section that outputs the high-frequency side clock pulse as it is and one of the two clock pulses of the clock frequency dividing circuit section are input from the outside and the output of the clock counting output selection circuit section described later. A clock selection circuit section for selecting and outputting with an exclusive OR, and a clock counting circuit section for inputting the selected clock pulse and counting with an n-ary X-ary counter (n is an integer of 1 or more); A gate circuit for inputting an input signal from the outside and a clock pulse on the high frequency side that is the output of the clock divider circuit section, and a clock pulse on the high frequency side by the output of the gate circuit With a (n + 1) -stage X-adic counter, a (n + 1) -stage latch circuit for latching the counting result by the counting circuit, and a stage position where a high output first appears in the output of the latch circuit. From the upper stage, one of the outputs of the clock counting circuit unit is detected by the logic gate for detecting the number of stages required for counting the high frequency side clock pulse by the counting circuit and the output of the logic gate. And a switch to select, and (n +
1) In a counting circuit including a stage X-adic counter, when the stage required to count high-frequency clock pulses in the clock frequency dividing circuit unit is m (an integer of 2mn + 1), there are n stages of X-adic counting in the clock counting circuit unit. A clock count output selection circuit section for selecting and outputting the (m-1) th stage output of the counter;
This is a digital PLL circuit having, and by this, the output signal can be locked over a wide input signal frequency in accordance with the frequency of the external input signal V _IN .

Description of Embodiments FIG. 2 is a circuit block diagram of an embodiment of the present invention, which includes a clock frequency dividing circuit unit 1, a clock selecting circuit unit 2, a clock counting circuit unit 3, and a clock counting output selecting circuit unit 4. The configuration and operation of the circuit according to the embodiment of the present invention will be briefly described below with reference to FIG.

First, in the clock frequency dividing circuit unit 1, a clock pulse signal CK from the outside is input, CK itself is used as a high frequency side clock pulse CK _H, and CK is frequency-divided by X (X is an integer of 2 or more) at a low frequency. Output as CK _L as the side clock pulse.

In the clock selection circuit unit 2, the external input signal V _IN and the clock count output selected by the clock count output selection circuit unit 4
V _O is input to select one of the two clock pulses (CK _H , CK _L ) output from the clock frequency dividing circuit unit 1, and this is used as CK _S in the clock counting circuit unit 3. Supply. Here, a case where X = 2 is described as a typical example. The clock count output selection circuit section 4 determines the cycle T of the external input signal V _IN by the clock pulse CK _H on the high frequency side described above.
A simple explanation will be given by exemplifying a circuit which has a built-in circuit function of counting with a binary counter and the clock counting circuit section 3 is also composed of a binary counter.

The period T of the input signal input V _IN is expressed by the following equation, where m is the number of stages of the binary counter required for counting and T _H is the period of the divided clock pulse CH _H.

^{T = (2 m-1 +} a) · T H, (0a m-1 -1) ...... (2) , where two clock pulses CK _H output from the clock divider circuit 1, each of the CK _L The relationship between the periods T _H and T _L of
Since X = 2, T _L = 2T _H , and the equation (2) is
It can also be expressed as follows.

From the expressions (2) and (3), the following relationship is obtained.

2 ^m−1 · T _H T <2 ^m−1 · T _L (4) From the above relationship, the clock counting circuit unit 3 and the clock counting output selection circuit unit 4 are each configured by a binary counter, When the relationship between the two clock pulses CH _H and _C K _L obtained in the clock frequency dividing circuit unit 1 is T _L = 2T _H , the number of counter circuit stages of the clock counting circuit unit 3 is set to the clock counting output selection circuit. One of the above divided clock pulses CK in section 4
According to the number of stages obtained by subtracting one from the number of stages of the binary counter required when counting _H , this digital PLL circuit can lock the output at the cycle T of the input signal V _IN .

FIG. 3 is a detailed circuit diagram showing the configuration of the second embodiment shown in FIG.
It is an example circuit of the present invention. This circuit will be described in detail for each block unit in FIG. 2 together with its function.

It is composed of a clock frequency dividing circuit section 1 and a T-type flip-flop 5, and divides an externally applied input clock pulse CK by two. Therefore, among the divided clock pulses, the divided clock pulse CK _H on the high frequency side is the input clock pulse C
K itself is output, while the divided clock pulse CK _L on the low frequency side is the true value output terminal Q of the T-type flip-flop 5.
It is a pulse of 2 frequency division output from.

The clock selection circuit unit 2 is composed of an exclusive OR (EXOR) / comparator that outputs a gate signal according to the phase relationship of two inputs, and a transmission gate for supplying the clock pulse CK _S to the clock counting circuit unit 3. . EXOR
The comparator sends the gate signal V _C determined by the phase relationship between the external input signal V _IN and the output V _O of the clock counting output selection circuit unit 4 to the transmission gate. Then, in the transmission gate, the gate signal V _C
Thus, one of the two clock pulses CK _H and CK _L from the clock frequency dividing circuit unit 1 is selected and the selected clock pulse CK _S is supplied to the clock counting circuit unit 3. FIG. 4 shows an operation timing chart of the clock selection circuit section 2. As shown in this figure, the output pulse CK _S of the clock selection circuit unit 2 in FIG. 3 is the EXOR / comparator output V _C.
Is high level (“H”), CK _H appears selectively, while V _C is low level (“L”), CK _L appears selectively.

The clock counting output selection circuit unit 4 is a gate circuit that regulates the high frequency side clock pulse CK _H obtained by the clock frequency dividing circuit unit 1 during one cycle T of the external input signal V _IN , and the high frequency side clock pulse CK. (N + 1) -stage T-type flip-flop circuit that counts _H and latches the counting result (n +
1) Select the outputs Q _{1 to} Q _n of the clock counting circuit unit 3 according to the D-type flip-flop circuit of the stage and the counting result, and output V _O
It consists of a logic gate and an analog switch. Looking at the overall operation in detail, the external input signal V
Two _IN cycles work as one unit operation cycle, and the operation timing chart is shown in FIG. First, the external input signal V _IN is input to the T-type flip-flop 6 and causes the true value output terminal Q to generate an output of frequency division by two. Then, the Q output and the clock pulse CK _H on the high frequency side are input to the AND gate 7, and CK _H is selectively taken out for one cycle of V _IN to obtain its gate output V _G. Next, this gate output V _G is input to the (n + 1) -stage T-type flip-flop circuit and counted. Further, during one cycle of the next external input signal V _{IN in which} the gate output V _G is cut off, the counting result of the (n + 1) stage T-type flip-flop circuit is added to the (n + 1) stage D It is held in a latch circuit composed of a flip-flop. (N + 1) reset signal T-type flip-flop circuit of the stage, the signal signal and the external input signal V _IN of Complement output terminal of the T-type flip-flop 6 which divided by 2 external input signal V _IN is inverted by an inverter (the output V _R obtained by synthesizing an inverted external input signal ▲ ▼ and the aND gate 8, by this signal V _R (n
The +1) -stage T-type flip-flop circuit returns to the initial state. On the other hand, the output of the latch circuit composed of (n + 1) -stage D-type flip-flops is input to the logic gate 9, and the analog switch 10 is turned on and off by the output, and the output from the outputs Q _{1 to} Q _n of the clock counting circuit unit 3 is output. Used to selectively take one output V _O. That is, in the case of FIG. 3, if the counting circuit composed of (n + 1) -stage T-type flip-flops that counts the gate output V _G operates up to n stages during one cycle T of the external input signal V _IN , output Q ₁ to Q _n of the clock counting circuit section 3, (n-1) output Q _n-1 th stage is selected, also the (n + 1) stage of the counter circuit, and operates to (n + 1) stage Then, the outputs Q _{1 to} Q _n of the clock counting circuit unit 3
The output Q _n of the n-th stage is selected, respectively, the output terminal V _O
Taken out.

The above is a clock counting circuit unit composed of n = 2 binary counters with X = 2, and composed of a binary counter (n + 1).
The case of the clock count output selection circuit section of the stage counting circuit and the clock division circuit section of 2 division has been described, but X = 3
The same can be applied to the above cases.

As described above, according to the circuit of the embodiment of the present invention, by detecting the frequency of the external input signal V _IN , the number of operating stages of the clock counting circuit unit 3 can be arbitrarily set according to the frequency, so that it can be set over a wide frequency range. , Its output signal can be locked.

Effect of the Invention According to the digital PLL circuit of the present invention, the output can be locked over a wide frequency range. Therefore, according to this, a digital PLL circuit that can handle all frequencies can be obtained, the design becomes simple, and the practical field can be greatly expanded.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional example, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a circuit diagram of the embodiment, and FIGS. 4 and 5 are main parts of the same embodiment. It is an operation timing chart. 1 ... Clock divider circuit section, 2 ... Clock selection circuit section, 3 ... Clock counting circuit section, 4 ... Clock counting output selection circuit section, 5,6 ... T-type flip-flop, 7,8,9 …
… And gate, 10… analog switch.

Claims (1)

[Claims] 1. A clock pulse is input from the outside and X (X
A clock frequency on the low frequency side obtained by frequency division, and a clock frequency dividing circuit section for directly outputting the clock pulse input from the outside as a clock pulse on the high frequency side; the clock frequency dividing circuit section A clock selection circuit section for selecting and outputting one of the two clock pulses by an exclusive OR of an input signal from the outside and an output of a clock counting output selection circuit section described later; And a clock counting circuit section for counting with an n-ary X-ary counter (n is an integer of 1 or more); and an input signal from the outside and a clock pulse on the high frequency side that is an output of the clock dividing circuit section. And a counting circuit for counting the high-frequency side clock pulse by the (n + 1) -stage X-adic counter by the output of the gate circuit. The (n + 1) -stage latch circuit that latches the counting result and the stage where the high output first appears in the output of the latch circuit are examined from the upper stage, and the counting circuit counts the high-frequency side clock pulse. A count consisting of a logic gate that detects the required number of stages, and a switch that selects one of the outputs of the clock counting circuit section by the output of the logic gate, and that is composed of the (n + 1) -stage X-adic counter. In the circuit
When the step required for counting the high frequency clock pulse of the clock frequency dividing circuit section is m (an integer of 2mn + 1), (m-
1) A digital PLL circuit having a clock count output selection circuit section for selecting and outputting the output of the first stage.